1. technology and computing

ISSN 2394-3777 (Print)
ISSN 2394-3785 (Online)
Available online at www.ijartet.com
International Journal of Advanced Research Trends in Engineering and Technology (IJARTET)
Vol. II, Special Issue XXIII, March 2015 in association with
FRANCIS XAVIER ENGINEERING COLLEGE, TIRUNELVELI
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
INTERNATIONAL CONFERENCE ON RECENT ADVANCES IN COMMUNICATION SYSTEMS AND
TECHNOLOGIES (ICRACST’15)
TH
25 MARCH 2015
CMOS STARTUP CHARGE PUMP WITH BODY BIAS
AND BACKWARD CONTROL USING 45 nm
TECHNOLOGY
Sunny Sinha
PG student, VLSI design
The Rajaas Engineering College
Tirunelveli, Tamilnadu
Abstract- A new low voltage charge pump is developed to help start up a step-up converter in energy harvesting
applications. The proposed charge pump is the first to utilize both backward control scheme and two branches of charge
transfer switches (CTSs) to direct charge flow. The backward control scheme uses the internal boosted voltage to
dynamically control the CTSs’ gate, and the two branches utilize both NMOS and PMOS to implement their switching
structure. The combination of backward control scheme and two-branch operation allows the CTSs to be completely turned
on and off. Thus, the reverse charge sharing phenomenon and switching loss are significantly reduced, which effectively
improves pumping efficiency. The last stage is specially designed to improve the charge pump’s charge and capacitance
drivability. Using subthreshold operation and body-bias technique, the charge pump and its clock generator can operate
under a low voltage supply. The proposed charge pump circuit is designed in a standard 45 nm CMOS process. It consists of
6 stages, each with a 24 pF pumping capacitor (total 288 pF pumping capacitance area). Under a 400 mV supply, the
measured output voltage of the proposed charge pump can rise from 0 to 2.27 V within 0.1 milliseconds.
I. INTRODUCTION
I N remote sensing applications, energy harvesting is often
utilized to provide a renewable power source for sensor nodes
.Mean while, most sensors require high operating voltage in
several volts. To solve this problem, a step-up converter can
be used to boost a low voltage source and to provide a high
voltage output to power a load. However, operating a step-up
converter under a low voltage supply is challenging. In steady
state operation, a step-up converter can use its own high
voltage output to power the control circuitry (self-sustained
condition), but initially, a sufficiently high voltage must be
applied to start up the system Apparently, a better approach is
to build an integrated startup charge pump, which can generate
a high-voltage pulse to bootstrap a step-up converter from a
low voltage input.
In this paper, a startup charge pump is proposed for low
voltage operation. The charge pump with an integrated ring
oscillator utilizes subthreshold operation and body bias
technique to enable startup and operation under a low voltage
supply. A startup charge pump only works during the startup
period of a step-up converter, and it only supports a
capacitive load.
MOS ICs have met the world’s growing needs for
electronic devices for computing,
communication,
entertainment, automotive, and other applications with
steady Improvements in cost, speed, and power consumption.
Such steady improvements in turn stimulate and enable new
applications and fuel the growth of IC sales. By making the
transistors and the interconnects smaller, more circuits can be
fabricated on each silicon wafer and therefore each circuit
becomes cheaper. Miniaturization has also been instrumental
in the improvements in speed and power consumption. Each
time the minimum line width is reduced, we say that a new
technology generation or technology node is introduced.
Examples of technology generations are 0.18μm, 0.13μm,
90nm, 65nm, 45nm...generations. The numbers refer to the
minimum metal line width. Poly-Si gate length may be
smaller. This practice of periodic size reduction is called
scaling. Since nearly twice as many circuits can be fabricated
on each wafer with each new technology node, the cost per
circuit is reduced significantly. Besides line width, some other
parameters are also reduced with scaling such as the MOSFET
gate oxide thickness and the power supply voltage. The
reductions are chosen such that the transistor current density
(Ion/W) increases with each new node. Also the smaller
transistors and shorter interconnects lead to smaller
capacitances. Together, these changes cause the circuit delays
to drop. Scaling does another good thing it
reduces
capacitance and, especially, the power supply voltage is
effective for lowering the power consumption. Scaling
249
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ISSN 2394-3777 (Print)
ISSN 2394-3785 (Online)
Available online at www.ijartet.com
International Journal of Advanced Research Trends in Engineering and Technology (IJARTET)
Vol. II, Special Issue XXIII, March 2015 in association with
FRANCIS XAVIER ENGINEERING COLLEGE, TIRUNELVELI
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
INTERNATIONAL CONFERENCE ON RECENT ADVANCES IN COMMUNICATION SYSTEMS AND
TECHNOLOGIES (ICRACST’15)
TH
25 MARCH 2015
improves cost, speed, and power per function with every new
technology generation. Compared with previous charge
pumps designed in similar CMOS processes, the proposed
charge pump offers the best performance.
II. PREVIOUS WORK
Fig. 1. Six-stage Dickson charge pump.
The Dickson charge pump circuit is basically a DC to DC
boost converter .Which provides high output even low input
voltage. In the Dickson charge pump circuit, the coupling
capacitors are connected in parallel and must be able to
withstand the full output voltage. This results in lower output
impedance due to the voltage drop across the switches as the
number of stages increases. The body effect makes this
problem even worse at higher voltages. Dickson charge pump
circuits where diodes are used as switches and can be
implemented with diode connected MOSFETs. Dickson
charge pump is not properly suitable for low-voltage
applications.
Many modifications to the Dickson charge pump have been
Proposed to enable it to operate at low input voltage levels.
For example, the diode voltage drop is eliminated by using
charge transfer switch (CTS.
The following observations are made from the Dickson charge
Pump’s structure:
1. In every clock cycle, due to Vth drop, there is a
remaining charge given by ΔQ = Cpump × Vth that
cannot be transferred from one stage to the next
stage.
2. Each diode-connected switch device has an
equivalent drain-to-source resistance. This causes
conduction loss, which degrades pumping efficiency
and charge transferability. A wider diode-connected
switch device with a shorter channel length can be
used to reduce Req , but it will increase Vth.
3. A higher clock voltage can transfer more charge in
each clock cycle and more effectively turn on/off the
switches to decrease and the charge sharing
phenomenon.
Static charge transfer switches (CTSs) refers to a type of
charge pump that uses dynamic feedback control to eliminate
voltage loss resulted from Vth drop .By using the predicted high
voltage in the later stages to control the earlier stages of CTSs,
the switches can be turned on/off more effectively.
Wu and Chang’s charge pump, shown in Fig. 2, has a
better voltage pumping gain than the Dickson charge pump.
The corresponding waveform of each node is also shown in
Fig. 2. During the time interval T1, the voltage at node 1 is 1
VDD, and the voltage at node 2 is 3 VDD. Thus, MN1 is off,
and MP1 is on. The high voltage from node 2 is borrowed to
completely turn on switch MS1, which transfers the charge
from the power supply (VDD) to node 1.
During the time interval T2, the voltage at node 1 increases
to 2 VDD, and the voltage at node 2 decreases to 2 VDD.
Thus, MN1 is turned on, MP1 is turned off, and MS1 can be
completely turned off to prevent the reverse charge sharing
phenomenon between node 1 and the power supply VDD.
Succeeding stages of the charge pump operate similarly.
Although this charge pump offers some pumping efficiency
improvement, it is not optimal for low voltage operation for the
following reasons:
1.
Since charge from the power source is
pushed into one CTSs branch, the “redistribution
loss" between the last stage and the output
capacitor is not negligible.
2.
3.
4.
When a CTS is turned on, there is a conduction loss
(Req) in the channel .Increasing the turn-on gatesource voltages and the device width can reduce the
conduction loss .When we increases the width of a
transistor it increases the Vth.
When CTS is turned off the reverse charge sharing
phenomenon is not completely lost .Longer channel
length is used to control the leakage .But it would
affect the pumping efficiency.
MDO at last stage suffers from body effect and Vth
loss.
Fig. 2. Circuit and corresponding voltage waveforms of the six-stage Wu and
250
All Rights Reserved © 2015 IJARTET
ISSN 2394-3777 (Print)
ISSN 2394-3785 (Online)
Available online at www.ijartet.com
International Journal of Advanced Research Trends in Engineering and Technology (IJARTET)
Vol. II, Special Issue XXIII, March 2015 in association with
FRANCIS XAVIER ENGINEERING COLLEGE, TIRUNELVELI
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
INTERNATIONAL CONFERENCE ON RECENT ADVANCES IN COMMUNICATION SYSTEMS AND
TECHNOLOGIES (ICRACST’15)
TH
25 MARCH 2015
two-branch charge pump.
Chang charge pump
III. SUBTHRESHOLD AND BODY-BIAS RING OSCILLATOR
Fig. 3. Six-stage linear charge pump circuit with all PMOS switches.
Here the author proposed a six-stage linear charge pump
(LCP), shown in Fig. 3, which was modified from Wu
and Chang’s charge pump. With PMOS CTSs, the circuit
utilizes a systematic gate control method to achieve high
pumping Efficiency. Here NMOSs in the branch of CTSs are
replaced by PMOSs, which reduces reverse charge sharing.
PMOS size has less impact on the absolute threshold
Voltage than NMOS, and thus, wider devices can be used to
reduce conduction loss. The control signals of branches A
and B are intertwined, and their clock signals are out of
phase.
Advantages of this architecture are:
1. Improves pumping efficiency and reduces output
ripples. Two pumping branches can provide better
charge transferability.
2. Redistribution loss is reduced.
3. Lower reverse charge sharing loss.
4. Pumping efficiency is improved.
Although the TBCP has many advantages, it is still not
suitable for low voltage applications. If VDD is only several
hundred millivolts, the CTSs cannot be completely turned on.
Fig. 4. Circuit structure and corresponding voltage waveforms of the six-stage
Fig. 5. Five-stage subthreshold and body bias ring oscillator with two parallel
buffer stages
The first challenge is to build a ring oscillator, which can
generate out-of-phase clock signals. The oscillator must be able
to work under a voltage supply of several hundred millivolts.
The device must operate in the subthreshold region. Therefore
permitting a very small current flow due to a weak inversion
channel between its source and drain. This reduces the
oscillator’s drivability. Body biasing a MOSFET can decrease
its threshold voltage and increase its inversion area, which then
effectively increases the device’s transient response and current
drivability. Therefore, implementing body bias technique in
deep n-well process can allow standard CMOS devices to
function under a low voltage supply.
The designed subthreshold and body-bias ring oscillator is
shown in Fig. 5. Clk and clkb are two out of phase clock
signals. The oscillator has five stages of inverters operating in
the subthreshold region. The W/L size ratio of the devices is
kept small to lower the Vth. Two phase shifting circuits with
large size buffers are used to improve the clock output swing
and the current drivability. Body-bias is applied to the
MOSFETs constructing the inverters, phase shifters, and
buffers to lower the threshold voltage Vth . The body bias
voltage can be generated by a simple resistor voltage divider.
The control signal Vstart can come from the output of a step- up
converter. During the startup period of the step-up converter,
Vstart is low, which enables and initializes the ring oscillator
.Here the W/L ratio is kept 2.Length is kept 45nm and the width
is kept 90 nm. This helps us to reduce the entire area of the ring
251
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ISSN 2394-3777 (Print)
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International Journal of Advanced Research Trends in Engineering and Technology (IJARTET)
Vol. II, Special Issue XXIII, March 2015 in association with
FRANCIS XAVIER ENGINEERING COLLEGE, TIRUNELVELI
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
INTERNATIONAL CONFERENCE ON RECENT ADVANCES IN COMMUNICATION SYSTEMS AND
TECHNOLOGIES (ICRACST’15)
TH
25 MARCH 2015
oscillator.
IV. PROPOSED SIX-STAGE CHARGE PUMP
Fig. 6. (a) Circuit and (b) corresponding waveforms of the proposed sixstage charge pump.
252
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ISSN 2394-3777 (Print)
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International Journal of Advanced Research Trends in Engineering and Technology (IJARTET)
Vol. II, Special Issue XXIII, March 2015 in association with
FRANCIS XAVIER ENGINEERING COLLEGE, TIRUNELVELI
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
INTERNATIONAL CONFERENCE ON RECENT ADVANCES IN COMMUNICATION SYSTEMS AND
TECHNOLOGIES (ICRACST’15)
TH
25 MARCH 2015
The Proposed six stage charge pump basically made by
using 45 nm technology which reduces the entire area of the
charge pump and thus improves the over all power
consumption of the charge pump .As in the previous work we
showed that 180 nm technology was used and here in the
proposed system entire technology has been scaled down by to
45 nm technology. Since nearly twice as many circuits can be
fabricated on each wafer with each new technology node, the
cost per circuit is reduced significantly. Besides line width,
some other parameters are also reduced with scaling such as
the MOSFET gate oxide thickness and the power supply
voltage. Also the smaller transistors and shorter interconnects
lead to smaller capacitances. Scaling does another good thing
it reduces capacitance and, especially, the power supply
voltage is effective for lowering the power consumption.
Scaling improves cost, speed, and power per function with
every new technology generation.
VDD, 3 VDD, 5 VDD, and 5 VDD, respectively, and the
voltage levels of node 8, node 9, node 10 and node 11 are
2 VDD, 4 VDD, 4 VDD, and 6 VDD, respectively.
Therefore, the output of Inv3 is pulled down to node 3 (3
VDD), and the output of Inv8 is pulled up to node 11 (6
VDD). The gate source voltage of MP2 is VDD, and the
gate-source voltage of
The First and Second Pumping Stages
In the time interval T1, the clock signal clk is low and clkb is
high. The voltage levels of node 1, node 2, node 3, and node 4
are VDD, 3 VDD, 3 VDD, and 5 VDD, respectively, and the
voltage levels of node 7, node 8, node 9 and node 10 are 2
VDD, 2 VDD, 4 VDD, and 4 VDD, respectively. The output
of inverter Inv6 is pulled up to node 9 (4 VDD), and the
output of inverter Inv7 is pulled down to node 8 (2 VDD). The
gate-source voltage of MP1, i.e., between the gate of MP1 and
node 1, is 3 VDD. The gate-source voltage of MN2, i.e.,
between the gate of MN2 and node 2, is VDD. So, bothMP1
andMN2 are tightly turned off, and there is no chance for the
charge to be reversely transferred from the high voltage of
node 2 to the low voltage of node 1. At the same time, the
gate-source voltage of MN1 is 3 VDD, which can strongly
turn on MN1 even under a low voltage supply, and the charge
can be directly transferred from the power supply to capacitor
C1.
Similarly, during the time interval T1, the output of
inverter Inv1 is pulled down to node 1 (VDD), and the output
of inverter Inv2 is pulled up to node 4 (5 VDD). The gatesource voltages of MP7 and MN8 are -1×VDD and 3 VDD,
respectively, and so the charge transfer switch MN8 can be
turned on even under a very low voltage supply VDD.
However, because the gate-source voltage of MP7 is only
VDD, the body-bias technique should be applied on MP7 to
decrease its threshold voltage for operation at low voltage.
As illustrated in Fig. 6(a), the third stage in branch A is
controlled by inverters Inv3 and Inv8. In the time interval T1,
the voltage levels of node 2, node 3, node 4, and node 5 are 3
Fig. 7. Bulk connections of PMOS of the proposed charge pump
MN3 is 3 VDD. Hence, the charge can be transferred
from node 2 to node 3. This operation is very similar to
that of the second stage in branch B. In the same way,
the operation of the third stage in branch B is similar to
that of the second stage in branch A. The operations of the
fourth and fifth stages are similar to the third stage. The
compensated structures of branch A and branch B
alternatively turn on and turn off the charge transfer
switches. Thus, in any time interval, charge is always
pumped to the output by one of the branches, and the
output voltage ripples are reduced.
B. The Last Stage
The last stage includes the 6th stage in branch A and
the 12th stage in branch B. Their gate control signals
come from the inverters N1-P1 and N2-P2. In the
preceding stages, the inverters borrow voltages of later
stages to supply their plus terminals, and so they have 2
VDD between their plus and minus terminals to operate.
However, the last stage has no next stage from which to
borrow a high voltage. So, if VDD is low, the inverters
do not have enough overdrive voltage to turn on N1/N2
and P1/P2. Therefore, the connection of the last stage’s
inverters is modified, as shown in Fig. 6(a). During the
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International Journal of Advanced Research Trends in Engineering and Technology (IJARTET)
Vol. II, Special Issue XXIII, March 2015 in association with
FRANCIS XAVIER ENGINEERING COLLEGE, TIRUNELVELI
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
INTERNATIONAL CONFERENCE ON RECENT ADVANCES IN COMMUNICATION SYSTEMS AND
TECHNOLOGIES (ICRACST’15)
TH
25 MARCH 2015
time interval T1, the gate voltage and source voltage (node
Vout ) of P1 are 5 VDD and 7 VDD, respectively, and the
gate voltage and source voltage of N1 are both 6 VDD. Thus,
P1 is turned on, N1 is turned off, and the gate of the 12th
stage is pulled up to 7 VDD. A similar situation
occurswithN2 andP2 in branch A, and the gate voltage of
the sixth stage is pulled down to 5 VDD. The operation in
the time interval T2 is similar, which guarantees enough
voltage to turn on/offMP6 andMP12 to reduce the
redistribution loss between the last stage and the output
capacitor. However, during T1, the gate- source voltage of
MN12 is only 1 VDD, and so cross-coupling the bulk of
MN12 to node 6 is implemented to reduce its Vth , as shown
in Fig. 6(a). Also, the size of MN12 and MN6 is larger
than that of previous stage switches, in order to improve their
charge transferability.
In time interval T1, MP6 is turned on to transfer the
charge from node 6 to the output node, but MP12 is turned
off to cut off the path from the output node back to node
12. Similarly, during time interval T2, MP6 is turned off,
and MP12 is turned on. Therefore, in both T1 and T2,
output capacitive load is driven by either of the two
branches alternatively, which effectively lowers output
voltage ripple and improves pumping efficiency. Also, when
output current increases, degradation of the output voltage is
less severe than it would be if only one charge transferring
branch is used. When the charge pump starts up, the
voltage in each pumping node is not established; initially,
most of the devices work in the subthreshold region. To help
establish the initial state, rather than using diode-connected
devices as in , the threshold voltage of the NMOSs in the
earlier stages is made smaller than those in the later stages.
In our process, a smaller threshold voltage can be achieved
by reducing the width-to- length ratio of the device.
However, small width-to-length ratio limits the amount of
charge flow through the switches. Thus, the width-to-length
ratio is gradually increased from the earlier stages to the
later stages.
C. Advantages of the Proposed Charge Pump
1.
2.
3.
Since here we used 45 nm technology instead of 180
nm technology therefore the entire area is reduced and
overall power consumption is reduced .The W/L ratio
is kept 2.
Body leakage current is reduced by applying body
biasing to PMO.S
The last two stages are modified to turn on/off more
effectively under low supply voltage, which transfer
more charge and decreases the redistribution loss.
4.
5.
6.
Lower threshold voltage reduces the conduction
loss.
Reverse charge sharing loss is been reduced by
using both PMOS and NMOS.
A ring oscillator is also designed by using 45 nm
technology to generate two out of phase clock
signals under low supply voltage.
V. VERIFICATION AND DISCUSSION
A. Simulation and Result
A charge pump circuit provides a voltage that is higher
than the voltage of the power supply or a voltage of
reverse polarity. In many applications such as Power IC,
continuous time filters, and EEPROM, voltages higher than
the power supplies are frequently required. Increased
voltage levels are obtained in a charge pump as a result of
transferring charges to a capacitive load and do not involve
amplifiers or transformers. For that reason a charge
pump is a device of choice in semiconductor technology
where normal range of operating voltages is limited.
Charge pumps usually operate at high frequency level in
order to increase their output power.
The pumping capacitors of a startup charge pump play
an important part in the charge pump’s performance and
occupy a large silicon area. Thus, choosing a proper
capacitor size is very important .Generally, for charge
pumps, the charge transferability to a capacitor decreases
linearly with increased output voltage, and so does its
pumping efficiency. To achieve higher charge transferability
at a fixed output voltage, the pumping capacitor’s size
should be as large as possible. All of these charge pumps
consist of six stages. Higher output charge transferability
results in a faster output ramp-up time for a specified load
capacitance.
The 45 nm standard CMOS device model is used to
verify the design of charge pumps. As shown in Fig. 10,
the simulated output voltage of the proposed charge pump
is much higher than those of the other charge pumps. So,
the proposed charge pump obviously has the highest
ramp-up current i.e., charge transferability.
The improved charge pump has been designed and
simulated using T- spice and H - Spice, 45 nm technology.
All the simulations are carried out at 500MHz and with
MOSFETs of same size (W/L=90nm/45nm). Amplitude of
CLK1 and CLK2 are same as the input voltage (VIN).
The charge pumps could operate at a much lower
voltage supply. However, they were fabricated in a 45 nm
CMOS process, which offered devices with lower
254
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International Journal of Advanced Research Trends in Engineering and Technology (IJARTET)
Vol. II, Special Issue XXIII, March 2015 in association with
FRANCIS XAVIER ENGINEERING COLLEGE, TIRUNELVELI
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
INTERNATIONAL CONFERENCE ON RECENT ADVANCES IN COMMUNICATION SYSTEMS AND
TECHNOLOGIES (ICRACST’15)
TH
25 MARCH 2015
threshold voltage.
scaling. Process designers scale both the applied voltage and
the oxide thickness to maintain the same electric field.
This approach reduces power by about 50% with every
new technology node However, as the voltage gets smaller,
the threshold voltage also must scale down to meet the
performance targets of that technology. This scaling
unfortunately increases the sub-threshold current and hence
the leakage power, each technology usually has two
variants. One variant aims for high performance, and the
other shoots for low leakage. The primary differences
between the two are in the oxide thickness, supply voltage,
and threshold voltage. The technology variant with the
thicker gate oxide aims for low-leakage design and must
support a higher voltage to achieve a reasonable
performance.
Fig. 8, the simulated output voltage of theproposed
charge pump
Fig. 9. Simulated clkb and clk waveforms from the proposed ring oscillator
under 400 mV power supply.
Therefore the MOSFETs can effectively turn on/off
under 400 mV supply without any difficulty. Considering the
overall performance, the proposed charge pump achieves the
lowest operating voltage, the largest capacitance driving
capability and the best pumping efficiency and reduction in
overall area which further lowers the power consumption.
A. The Role of Technology Selection
Proper technology selection is one of the key aspects of
power management. The goal of each
technology
advancement is to improve performance, density, and power
consumption. The typical approach in developing a new
generation of technology is to apply constant-electric-field
VI. CONCLUSION
A new CMOS charge pump module with integrated
two- phase clock generator has been designed to provide
startup function for energy harvesting step-up converters
using 45nm technology. Using subthreshold operation and
body bias technique, the charge pump and its clock
generator can operate at as low as 400 mV power supply.
Using internal boosted voltages, the backward control
scheme increases the clock amplitude, and together with a
compensated two-branch structure, it can completely turn on
and off the CTSs under a low voltage supply. Thus, the
reverse charge sharing phenomenon and switching loss are
mitigated sharply. Meanwhile, a modified output structure
increases the last pumping stage’s drivability by avoiding
the diode connection, which further improves the pumping
efficiency.
In conclusion, the proposed charge pump circuit can be
effectively used to start up a step-up converter in energy
harvesting applications, where the available voltage can be
as low as 400 mV, which is below the threshold voltage of a
standard 45 nm CMOS process. Compared with other
charge pumps designed in similar processes, the proposed
charge pump has the largest capacitance drivability and the
highest pumping efficiency and small area and low power
consumption. Since the W/L ratio is kept 2 for the entire
MOS used in the construction of ring oscillator .But while
constructing Six stage charge pump, the each stage MOS
W/L ratio must vary in order to drive the other stages, or
else due to low output voltage it will not able to drive other
stages .So my future work is to nicely verify each and every
stages and should select their W/L ratio correctly.
255
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International Journal of Advanced Research Trends in Engineering and Technology (IJARTET)
Vol. II, Special Issue XXIII, March 2015 in association with
FRANCIS XAVIER ENGINEERING COLLEGE, TIRUNELVELI
DEPARTMENT OF ELECTRONICS AND COMMUNICATION ENGINEERING
INTERNATIONAL CONFERENCE ON RECENT ADVANCES IN COMMUNICATION SYSTEMS AND
TECHNOLOGIES (ICRACST’15)
TH
25 MARCH 2015
switched-current techniques using sub-threshold MOS operation,”
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