1. No category

HW#3 第一題
1. An ABCD-to-seven segment decoder is a combinational circuit that converts a decimal
digit in BCD to an appropriate code for the selection of segments in an indicator used to
display the decimal digit in a familiar form. The seven outputs of the decoder (a, b, c, d,
e, f, g) select the corresponding segments in the display, as shown in Fig. 1(a) below.
The numeric display chosen to represent the decimal digit is shown in Fig. 1(b).
(a) Show the truth table for the seven outputs. (10%)
(b) Use Karnaugh maps to simplify this BCD-to-seven-segment decoder to a
minimal Sum-of-Product (SOP) form. Note that the six invalid input
combinations should result in a blank display. (20%)
Fig. 1
1
Electrical Engineering
National TsingHua University, Taiwan
HW#3 第一題 (a)
„ Show the truth table for the seven outputs. (assume blank = logic-0)
„ ANS:
Inputs
Outputs
A
B
C
D
a
b
c
d
e
f
g
0
0
0
0
1
1
1
1
1
1
0
0
0
0
1
0
1
1
0
0
0
0
0
0
1
0
1
1
0
1
1
0
1
0
0
1
1
1
1
1
1
0
0
1
0
1
0
0
0
1
1
0
0
1
1
0
1
0
1
1
0
1
1
0
1
1
0
1
1
0
1
0
1
1
1
1
1
0
1
1
1
1
1
1
0
0
0
0
1
0
0
0
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
0
1
1
1
0
1
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
1
1
0
1
0
0
0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
0
2
Electrical Engineering
National TsingHua University, Taiwan
HW#3 第一題 (b)
„ Use Karnaugh maps to simplify this BCD-to-seven-segment decoder to a minimal
Sum-of-Product (SOP) form. Note that the six invalid input combinations should
result in a blank display.
„ ANS:
a = A’C + A’BD + AB’C’ + B’C’D’ (or A’C + A’BD + AB’C’ + A’B’D’)
b = A’B’ + B’C’ + A’C’D’ + A’CD
c = A’B + A’D + B’C’
d = A’B’C + A’CD’ + AB’C’ + B’C’D’ + A’BC’D (or A’B’C + A’CD’ + AB’C’ + A’B’D’ + A’BC’D)
e = B’C’D’ + A’CD’
f = AB’C’ + A’BC’ + A’BD’ + A’C’D’ (or AB’C’ + A’BC’ + A’BD’ + B’C’D’)
g = AB’C’ + A’BC’ + A’B’C + A’CD’ (or AB’C’ + A’BC’ + A’B’C + A’BD’)
EX: K-MAP for “c”
C’D’ C’D
CD
CD’
A’B’
1
1
1
0
A’B
1
1
1
1
AB
0
0
0
0
AB’
1
1
0
0
3
Electrical Engineering
National TsingHua University, Taiwan
HW#3 第二題
„
Explain the function of the circuit specified by the following HDL description.
module Prob4_43(A, B, S, E, Q);
input
[1:0]
A, B;
input
S, E;
output [1:0]
Q;
assign Q = E ? (S ? A : B) : ‘bz;
endmodule
„ ANS:
A
Tri-state MUX
1
MUX
B
0
S
E
(Circuit)
Input Combination
Q
Output Function
Signal “E”
Signal “S”
Signal “Q”
E=0
S=X
High Impendence (Z)
E=1
S=1
Q=A
E=1
S=0
Q=B
(Specification)
4
Electrical Engineering
National TsingHua University, Taiwan
HW#3 第三題
„
Using a case statement to write a behavioral Verilog description of an eight-bit
arithmetic-logic unit (ALU). The circuit has a three-bit select bus (Sel), eightbit input data buses (A[7:0] and B[7:0]), an eight-bit output data bus (y[7:0]),
and performs the arithmetic and logical operations listed below.
Sel
Operation
Description
000
y = 8’b0
001
y=A&B
Bitwise and
010
y=A|B
Bitwise or
011
y=A^B
Bitwise exclusive or
100
y=A+B
Add (A, B are unsigned)
101
y=A-B
Subtract
110
y = ~A
Bitwise complement
111
y = 8’hFF
5
Electrical Engineering
National TsingHua University, Taiwan
HW#3 第三題 (cont.)
„ ANS:
module alu_8bits (Sel, A, B, y);
input [2:0] Sel;
input [7:0] A, B;
output [7:0] y;
reg [7:0] y;
always @ (Sel or A or B) begin
case (Sel)
3’b000: y = 8’b0
3’b001: y = A&B;
3’b010: y = A|B;
3’b011: y = A^B;
3’b100: y = A+B;
3’b101: y = A-B;
3’b110: y = ~A;
3’b111: y = 8’hFF;
endcase
end
endmodule
6
Electrical Engineering
National TsingHua University, Taiwan
HW#3 第四題
„
Draw the waveform generated by the following testbench statement:
(a) initial begin
w = 0; #15 w = 1; #60 w = 0; #25 w = 1; #40 w = 0;
end
(b) initial fork
w = 0; #15 w = 1; #60 w = 0; #25 w = 1; #40 w = 0;
join
„ ANS:
(a)
15
25
40
75
100
140
15
25
40
75
100
140
(b)
7
Electrical Engineering
National TsingHua University, Taiwan
HW#3 第五題
„
Consider the design of a one-input one-output serial 2’s complementer. The
circuit accepts a string of bits from the input and generates the 2’s complement
at the output. The circuit can be reset asynchronously to start and end the
operation.
(a) Draw the state transition graph.
(b) Write a behavioral Verilog code for this design.
‡ Hint:
觀察 2’s complement 的結果
010100
010100
(2’s complement)
101100
101100
假設從 LSB 開始輸入:
當輸入值出現 logic-1 之後，其之後的
輸出值皆是原輸入值的反相值。
8
Electrical Engineering
National TsingHua University, Taiwan
HW#3 第五題 (a)
„ (a) Draw the state transition graph
„ ANS:
S0: initial state
0/1 or 1/0
1/1
0/0
S0
S1
reset = 0
(note: input value/output result)
9
Electrical Engineering
National TsingHua University, Taiwan
HW#3 第五題 (b)
„ (b) Write a behavioral Verilog code for this design
„ ANS:
module one_one_complementer (clk, rst, in_bit, out_bit);
input clk, rst, in_bit;
output out_bit;
reg out_bit, cur_state, next_state;
always @ (posedge clk or negedge rst) begin
if(rst == 0) cur_state <= 1’b0;
else cur_state <= next_state;
end
always @ (in_bit or cur_state) begin
case (cur_state)
1’b0: begin
if(in_bit == 1) begin
out_bit <= in_bit; next_state <= 1’b1;
end
else begin
out_bit <= in_bit; next_state <= 1’b0;
end
end
1’b1: begin
out_bit <= ~in_bit; next_state <= 1’b1;
end
endcase
end
endmodule
10
Electrical Engineering
National TsingHua University, Taiwan