Special Half-‐Day Event at EPFL: Neuromorphic Systems Research at IBM Wednesday, 10 June 2015 Room SV 1717A 14:00-‐14:40 Neuromorphic Engineering Chung Lam, IBM Research, Yorktown Heights, NY, USA Microprocessors designed with von Neumann architecture are hitting the power and performance limits as silicon CMOS continues to scale the critical dimensions of the circuit components towards single digit nanometer size limit. Multi-‐core processor, parallel processing without increasing operating frequency of the cores, was introduced in the early 2000 to extend the power and performance scaling, keeping Moore’s Law viable. Amdahl’s Law, however, argues that the performance speedup with parallel processing is governed by the percentage of algorithm that needed be serial. Evolution has provided us with the most efficient parallel processing architecture: the biological brain. In this talk, we shall examine what we can do with little that we know about how the brain works to design machines to mimick the brain. 14:40-‐14:50 14:50-‐15:00 15:00-‐15:40 Questions/Discussion Coffee break HTM-‐based saccadic vision system Kamil Rocki, IBM Research–Almaden, San Jose, CA, USA In this project, Hierarchical Temporal Memory is used for rapid object categorization and tracking. Various studies have demonstrated the remarkable speed and efficiency with which humans process natural scenes. Despite the fact that our eyes' fovea region is very limited, we can efficiently view the world by redirecting the fovea between points of interest using eye movements called saccades. Using HTM, we are able to learn both simple spatial patterns representing such small fovea region, as well as predictable and invariant temporal patterns comprising whole sequence of saccades. Such an approach has two advantages: first, storing images as temporal sequences of small spatial building blocks is much more resource efficient than storing entire complex images. The second one is that there is no need to distinguish between storing and recognizing still and moving images. 15:40-‐15:50 15:50-‐16:00 16:00-‐16:40 Questions/Discussion Coffee break Crossbar arrays for Storage Class Memory and non-‐Von Neumann computing Geoffrey W. Burr, IBM Research–Almaden, San Jose, CA, USA For more than 50 years, the capabilities of Von Neumann-‐style information processing systems — in which a "memory" delivers operations and then operands to a dedicated "central processing unit" — have improved dramatically. While it may seem that this remarkable history was driven by ever-‐increasing density (Moore's Law), the actual driver was Dennard's Law: a device-‐scaling methodology which allowed each generation of smaller transistors to actually perform better, in every way, than the previous generation. Unfortunately, Dennard's Law terminated some years ago, and as a result, Moore's Law is now slowing considerably. In a search for ways to continue to improve computing systems, the attention of the IT industry has turned to Non-‐Von Neumann algorithms, and in particular, to computing architectures motivated by the human brain. At the same time, memory technology has been going through a period of rapid change, as new nonvolatile memories (NVM) — such as Phase Change Memory (PCM), Resistance RAM (RRAM), and Spin-‐
Torque-‐Transfer Magnetic RAM (STT-‐MRAM) — emerge that complement and augment the traditional triad of SRAM, DRAM, and Flash. Such memories could enable Storage-‐Class Memory (SCM) — an emerging memory category that seeks to combine the high performance and robustness of solid-‐state memory with the long-‐term retention and low cost of conventional hard-‐disk magnetic storage. Such large arrays of NVM can also be used in non-‐Von Neumann neuromorphic computational schemes, with device conductance serving as the plastic (modifiable) “weight” of each “native” synaptic device. This is an attractive application for these devices, because while many synaptic weights are required, requirements on yield and variability can be more relaxed. However, work in this field has remained highly qualitative in nature, and slow to scale in size. I will discuss our recent work towards large crossbar arrays of NVM for both of these applications. After briefly reviewing earlier work on PCM, SCM, and access devices based on copper-‐containing Mixed-‐Ionic-‐
Electronic-‐Conduction (MIEC), I will discuss our recent work on quantitatively assessing the engineering tradeoffs inherent in NVM-‐based neuromorphic systems. 16:40-‐16:50 Questions/Discussion About the speakers: Chung H. Lam received his B.Sc. at Polytechnic University of New York in 1978, his M.Sc. and Ph.D. at Rensselaer Polytechnic Institute in 1987 and 1988, all in Electrical Engineering. Since joining IBM in 1978, Chung has taken responsibilities in various disciplines of semiconductor research, development and manufacturing including circuit and device designs as well as process integrations for memory and logic applications in IBM Microelectronic Division. In 2003, Chung transferred to IBM Research Division at T.J. Watson Research Center. Chung was named IBM Distinguished Engineers in 2007 and Master Inventor in 2009. Chung was a member of the Technical Committees for IEEE Non-‐Volatile Memory Work Shop, VLSI-‐TSA and IEDM Memory Technology. Currently, he serves in the Technical Committees for CSTIC and ITRS PIDS. Chung manages Phase Change Memory Research Joint Projects at T.J. Watson Research Center since 2004. He has more than 250 granted US patents and published more than 65 technical papers. Kamil Rocki is a Research Staff Member at IBM Research. Prior to joining Almaden Research Center in California in 2013 he has spent 5 years in Japan at the University of Tokyo where he graduated with a PhD degree in Information Science in 2011. Before that he received his M.Sc. and B.Sc. degrees in Computer Science from Warsaw University of Technology. His research focuses on high performance parallel algorithms, hardware design, supercomputing, AI, computer vision and robotics. He has been working in the field of high performance computing for the past 9 years. Geoffrey W. Burr received his Ph.D. in Electrical Engineering from the California Institute of Technology in 1996 under the supervision of Professor Demetri Psaltis. Since that time, Dr. Burr has worked at the IBM Almaden Research Center in San Jose, California, where he is currently a Principal Research Staff Member. He has worked in a number of diverse areas, including holographic data storage, photon echoes, computational electromagnetics, nanophotonics, computational lithography, phase-‐change memory, storage-‐class memory, and novel access devices based on Mixed-‐Ionic-‐Electronic-‐
Conduction (MIEC) materials. Dr. Burr's current research interests include non-‐volatile memory and cognitive computing. An IEEE Senior Member, Geoff is also a member of MRS, SPIE, OSA, Tau Beta Pi, Eta Kappa Nu, and the Institute of Physics (IOP). He is a member of the Editorial team for the ITRS Emerging Research Devices (ERD) working group.