EE 140/240A Spring 2015 Prof. Pister Homework Assignment #8 Due by online submission Wednesday 4/1/2015 (Thursday 9am) 5V M9 200/1 M5A 200/1 VG5 M5B 200/1 400uA VS4A VS4B M4A 100/1 VG4=4V M4B 100/1 Vout M1A 50/1 M1B 50/1 M3A 50/1 VG3 Vtail VG6 M6 100/1 M7 100/1 M8 100/1 M3B 50/1 VS3B M4 200/1 M2A 50/1 VG2 M2B 50/1 0V Figure 1: NMOS input folded cascode. 1. The book gives three circuit examples for removing the RHP zero associated with Cc in a 2-stage CMOS op-amp. For each of the approaches shown in Figures 9.21, 9.22, and 9.23, draw the NMOSinput versions of these op-amps, and for each explain how a. the circuit provides Miller compensation (why the capacitance looks big from one side) b. the circuit removes the RHP zero (why the output doesn’t see any current injection from Cc) 2. You have a two-stage op-amp where each stage has a gain of 30 and a pole at 1Mrad/sec before compensation. You choose a value of Cc such that the phase margin is 45 degrees. You may ignore the mirror pole/zero doublet, and assume that you have removed the RHP zero associated with Cc. a. Draw a Bode plot of the uncompensated amplifier, and the compensated amplifier on the same plot. b. If the capacitance of the output stage increases by a factor of 10, what will that do to the phase margin? 3. The amplifier in Figure 1 is implemented in a process with the following process parameters: nCox=200A/V2, pCox=100A/V2, =1/(10V), -Vtp=Vtn=0.5V. a. Calculate and tabulate i. the current in all transistors (useful order: M6, M7, M8, M9, M1AB, M5AB, M4AB). For these calculations you can assume that =0. ii. the voltage bias on all nodes, assuming VICM=2V. Specifically: tail, G2, G3, G5, G6, S3B, S4AB, Vout iii. the gm and ro parameters for M1 through M5 b. Calculate Gm, Ro, and Av c. Calculate the input common mode range and output swing. d. What is the maximum voltage that could be used on the gates of M4AB to still keep M5AB in saturation? If you used that voltage, what is the new input common mode range and output swing? e. If the output capacitance is 1pF, i. what are the pole and unity gain frequencies? ii. What is the phase margin? iii. What are the frequencies of the pole/zero doublets from the current mirror? 4. [ee240A] With this process, assuming sub-threshold operation, what is the smallest VDD for which this amplifier would work? Compare the sub-threshold performance (gain, frequency response, input and output swings) of this amplifier to a similar two-stage design in the same process. Be as specific as you can for the case when Vgs=Vt for all devices.