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IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 62, NO. 2, APRIL 2015
Stuck Bits Study in DDR3 SDRAMs Using
45-MeV Proton Beam
Chulseung Lim, Hyun Soo Jeong, Geunyong Bak, Sanghyeon Baeg, Member, IEEE,
Shi-Jie Wen, and Richard Wong
Abstract—This work shares the observations of stuck bits by
proton beam in DDR3 components in 3x-nm technologies. The
DDR3 SDRAMs from four major DRAM manufacturers were
tested with a 45-MeV proton beam at an operating frequency of
800 MHz. The beam exposure resulted in single bit upset (SBU)
and multiple bit upsets (MBUs), as well as single and multiple
stuck bits in a word due to micro-dose and displacement damage
effects. The number of stuck bits reduced as the refresh interval
duration was decreased. Moreover, for the tested samples, the
stuck bits were recovered completely and could be run in the
normal operation mode after annealing at
. The occurrence
of multiple stuck bits in a word was likely due to damages to the
control logic and those stuck bits were recovered as well after
annealing at
.
Index Terms—DDR3, displacement damage effect, DRAM cell
retention time, DRAMs, proton beams, SDRAM, stuck bits, TID
effect.
I. INTRODUCTION
W
ITH technology scaling, the soft error rate (SER) due to
high energy particles is generally expected to increase,
not only in memory cores but also in logic functional blocks in
dynamic random access memory (DRAM) components. This is
because in a memory component, the critical charge typically
decreases with shrinking bit size. However, as the technology
has scaled, the capacitance in a DRAM bit cell has stayed relatively constant, the area shrinkage of a memory bit has helped
to maintain the SER of a memory component constant over
multiple generations of technology [1]. Additionally, the stuck
bits—due mainly to the leakage current—because of microdose and displacement damages on a bit cell also appear in synchronous dynamic random access memories (SDRAMs). The
radiation sensitivity of SDRAMs has been reported in [2]–[9].
Furthermore, reports of micro-dose and displacement damages
Manuscript received March 25, 2014; revised September 18, 2014; accepted
January 06, 2015. Date of publication March 02, 2015; date of current version
April 10, 2015. This work was supported in part by the National Research Foundation of Korea grant funded by the Korean government Ministry of Education,
Science and Technology (2012R1A2A2A01015719), the Brain Scouting Program funded by the National IT Industry Promotion Agency (HB615-12-2001),
and the “GRRC” Project of Gyeonggi Provincial Government.
C. Lim, H. S. Jeong, G. Bak, and S. Baeg are with the Department of Electronics and Communication Engineering, Hanyang University, Sa 3-dong Sangrok-Gu Ansan, Kyeong-gi-Do 426-791, Korea (e-mail: [email protected];
[email protected]).
S.-J. Wen and R. Wong are with the Component Engineering Group, Cisco
Systems Inc., San Jose, CA 95134 USA.
Color versions of one or more of the ﬁgures in this paper are available online
at http://ieeexplore.ieee.org.
Digital Object Identiﬁer 10.1109/TNS.2015.2392851
caused by single particles appearing in SDRAMs have been
published [10]–[14].
In contrast to bit cells, the control logic elements inside
DRAMs are expected to scale with shrinking technologies and
become more vulnerable to high-energy particles due to two
main reasons: reduced critical charge in control logic primitives
and increased area owing to additions of increasingly complex
features in recent DRAMs. SDRAM has many logic blocks:
control logic, mode registers, decoders, and bank control logic
[3]. Any upset in the logic units can lead to the simultaneous
ﬂipping of numerous bits, which can be catastrophic to a system
with DRAMs.
Charged particles can cause single event effects (SEE) as well
as stuck bits. For instance, the accumulated particle damage in
a MOSFET can alter transistor characteristics such as threshold
voltage shift [15], [16]. In the reversed-biased depletion region,
carrier generation due to displacement damage can increase the
leakage current characteristics of affected bits, and this increase
in the leakage current can contribute to destruction of the data
stored in the corresponding bit cells [20]. The above mentioned
damages can be recovered by high temperature annealing [16],
[17].
In this work, SEE tests were performed using a 45-MeV
proton beam on DDR3 samples prepared with 3x-nm technologies by four different manufacturers, where x value represents
various values. This present study focused mainly on analyzing
stuck bits. As a result, the progressive removals of stuck bits
was demonstrated successfully by passing damaged DRAMs
through multiple annealing tests conducted with four different
temperatures higher than
.
II. TEST FACILITY AND PREPARATION
The beam experiments were performed with protons from
the MC-50 cyclotron at the Korea Institute of Radiological &
Medical Science (KIRAMS) in South Korea [19]. The facility
provides a 45-MeV proton beam, as well as beams with energies lower than 45 MeV. Changing beam energies on the ﬂy is
not supported conveniently. In our experiments, only a 45-MeV
beam was used.
A total of eight DDR3 samples from four different manufacturers–(two samples per manufacturer)–were used in the beam
test. One sample from each manufacturer was exposed to the
beam while it was operating, while the other sample was beamed
without supplying power to it. The main object of this work was
to observe variations across the manufacturers instead of variations in the same type of samples. The samples were 4 Gb DDR3
components with a maximum operating frequency of 800 MHz.
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LIM et al.: STUCK BITS STUDY IN DDR3 SDRAMs USING 45-MeV PROTON BEAM
521
Fig. 1. MC-50 cyclotron proton beam line and setup of memory tester system.
All samples had 8 banks, 13-bit pages, and 10-bit column addresses with 3-bit burst addresses, and VDD and VDDQ operating voltage of 1.5 V. These samples are referred to using
XY format throughout this paper, where X denotes manufacturer name, and Y denote sample number. The manufacturer
names and the technologies used in the samples could not be
disclosed owing to the agreements between the manufacturers
and Cisco for the use of the sample Cisco products.
To use DDR3 memories, we built in-house memory testers
with hardware and software tools. These testers can communicate with a daughter card loaded with memory samples, as
shown in Fig. 1. The memory testers recorded the individual
failing addresses and read-data during the experiments. The device under test (DUT) and the mother board were connected by
a SO-DIMM interface and followed the JEDEC standard [20].
Three different test patterns were employed under room temperature: all zero (ALL0), all one (ALL1), and checker board
(CB). The beam room in the radiation facility is located underground and is air-conditioned to maintain a room temperature
of around
. The typical operating temperature for commercial SDRAMs, is 0 to
as measured at the center or top side
of the chip. The following JEDEC standard values for temperature and refresh cycle parameters were used in the tests:
s
refresh cycle for 0 to
and
s refresh cycle for the temperatures over
[21].
III. EXPERIMENT RESULTS
Multiple proton tests runs were performed with various predetermined beam times over several days. During the proton exposures, single-bit upset (SBU) and multiple-bit upset (MBU)
were observed, and many of them appeared repeatedly at the
same addresses. After the removal of beam exposure, the recurring upsets occurred, and they were classiﬁed as stuck bits.
Fig. 2 shows the statistics of observed stuck bits after beam
irradiation when the samples were accessed actively. The horizontal axis shows the four different samples A1, B1, C1, and
D1. The vertical axis shows the scaled ratios of stuck bits in
Fig. 2. Observed stuck bits under different test patterns for four different
samples after irradiations; (a) shows percentage of stuck bits in each pattern,
(b) shows cross sections.
each test pattern, as shown in Fig. 2(a). The three vertical bars in
each column of Fig. 2(a), correspond to three different patterns:
ALL0, ALL1, and CB. Notably, not all samples were exposed
to the same amount of beam radiation; sample B1 was exposed
to about 1.3x the ﬂux that other samples were exposed to, and
accordingly, it had a greater absolute number of stuck bits than
the other samples.
The observed stuck bits are attributed to the accessed logical
address: if a logical address returns a different bit pattern than
that expected, it is considered a stuck bit. The stuck bit can be
classiﬁed as a multiple stuck bits (MSBs) in cases where multiple bits do not match or as a single stuck bit (SSB) in cases
where one bit is mismatched.
Please note that not all stuck bits appeared in all patterns.
Some stuck bits were masked by the test pattern and some stuck
bits were intermittent. Although the upsets were observed under
the ALL0 pattern during irradiation, stuck bits with the same
pattern after beam exposure were not observed in samples C1
and D1. To ensure that the results were not inﬂuenced by the
test setup, the same tests were repeated several times. Retention tests were performed to check whether the results in Fig. 2
are from design speciﬁc to manufactures. The ALL0 pattern retention tests also did not indicate the presence of stuck bits in
sample C1 and D1. Detailed retention test results are given in
Section IV.
Fig. 2(b) shows the cross section for different test patterns
with the error bars. The error bars indicate 95% of the conﬁdence interval of a Poisson mean. Generally, no signiﬁcant differences are observed across different patterns, except for the
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IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 62, NO. 2, APRIL 2015
ALL0 pattern in samples C1 and D1. Sample A1 was most sensitive, while sample C1 had the lowest cross section compared
with the other samples.
Fig. 3 shows the failed bit distribution of all stuck bits after
proton irradiation. This ﬁgures show the entire array space of
DUTs. The bit map is based on a logical structure because the
physical structure is unavailable. There are 8 K bits in each row
address, which are further accessed by 10-bit column addresses
including 3-bit burst addresses; each address returns 8-bit data
and one burst address returns 64-bit data. The horizontal axis
shows the addresses composed of both 3-bit banks and 16-bit
row addresses. The 8 bank blocks are placed equidistantly in the
horizontal direction. The two different types of stuck bits–SSBs
and MSBs–are shown in the ﬁgure. The stuck bits appear to be
distributed randomly over the entire array regardless of the test
patterns. Please note that the symbols overlap at times because
of that large symbols are used for clarity, therefore overlapping
symbols appear darker in Fig. 3. All overlapping addresses in
Fig. 3 are burst addresses. All or most of the 64 bits from each
burst address were shown to be ﬂipped and were classiﬁed as
MSBs. Further discussions of such MSBs are made in terms of
control logic damage in the next section. Most stuck bits were
MSBs for the CB pattern in Fig. 3(c). Some SSBs with the ALL1
or ALL0 pattern appeared as MSBs when the test pattern was
changed to CB because of the pattern dependent masks in ALL1
and ALL0.
IV. DISCUSSIONS OF STUCK BITS
The stuck bits shown in Figs. 2 and 3 were observed many
days after the irradiation. The stuck bits due to micro-dose and
displacement damage effects were primarily ascribed to high
leakage in a cell [18], [22]. For further insight into stuck failures,
two types of experiments–refresh dependencies, and annealing
by high temperature–were performed to ensure that the presence of the stuck bits could primarily be ascribed to micro-dose
and displacement damage effects instead of other failure mechanisms [18]. In the rest of this section, stuck bits are discussed
from various aspects.
A. Refresh Time Dependency Test
Fig. 4 shows that the number of stuck bits is reduced as the
refresh interval is shortened. This is the typical observation for
bit cells with dose- and displacement damage effects. The
s
and
s refresh cycle duration were selected based on the
JEDEC standards and the samples’ speciﬁcations. As expected,
the number of stuck bits decreased when the refresh time was
reduced to
s from
s, and this observation was applicable to all samples. The SSB ratio was the highest in sample
B1. For the
s refresh interval, relatively fewer stuck bits of
both types still remained.
Many MSBs failed at many bit locations, as shown in Fig. 3.
Those MSBs could not be corrected by single error correctiondouble error detection (SEC-DEC) which method commonly
uses the Hamming code [23].
Fig. 3. Bit maps of stuck bits after irradiation for four samples; (a) is for ALL0,
(b) is for ALL1, and (c) is for CB.
Fig. 4. Number of stuck bits is reduced when refresh time is reduced from
s to
s.
B. Multiple Stuck Bits
Table I summarizes the MSB read-data before the annealing
process. Please note that the address and the read data are pre-
sented in the hexadecimal format. The data shows that the most
data bits were ﬂipped regardless of the background patterns. As
LIM et al.: STUCK BITS STUDY IN DDR3 SDRAMs USING 45-MeV PROTON BEAM
TABLE I
MULTIPLE STUCK BITS CASES
523
components were baked for 12 hours at four different temperatures in a sequence:
,
,
, and
. After
annealing at each temperature, the samples were tested at room
temperature using the three patterns: ALL0, ALL1, and CB.
The test results of the samples are shown in Fig. 5. The horizontal axis represents the annealing temperatures. The number
of SSBs decreased consistently as the annealing temperature increased. However, at a certain annealing temperature, the cross
section of the SSBs increased. This increase in stuck bits seemed
to be caused by random re-sticking of the displacement damages
during annealing [13], [18]. The MSBs increased randomly as
well, which could be due to similar reasons as the SSBs, but in
the control logic elements. After annealing at
, all stuck
bits were removed.
D. Experiments with no Power to Samples
can be inferred from the table, some of the read data seemed
to be SSBs depending on the background pattern. For example,
in sample A1, an SSB was observed at 0A3E9BB under ALL0;
however, MSBs were also observed under the ALL1 pattern at
the same address. It seems that a SSB at a bit cell and the damage
to control logic coexist.
Displacement damage is known to affect local segments, typically single bits. Moreover, gate oxide trapping owing to the
dose effect leads to the formation of local stuck bits because
of the increased leakage current. However, the MSBs listed in
Table I cannot be explained by stuck bits on local memory cells.
Additionally, the physical damage mechanisms reported in [22]
could not explain the presence of those MSBs. Since the MSBs
in Table I appeared consistently and intermittently during the
annealing process, we believe that the MSBs are related to damages in the control logic.
Unfortunately, it is difﬁcult to explain which portion of the
damaged control logic can possibly ﬂip most of the 64-bit
data, as summarized in Table I. However, if we could borrow
the experiences from typical design practice, the default
values—during the burst operation—can be read if the I/O
multiplexer logic is not switched properly in time. Because
the tests were performed at the full speed of 800 MHz, the
timing may have been affected when the control logic became
leaky because of damage due to proton beam irradiation. The
default value can be all 0 or all 1 depending on the speciﬁc
implementation; here, it was 0 for manufacturers A and B and
1 for manufacturers C and D.
C. High-temperature Annealing Test
High-temperature annealing tests were performed to see if
they would result in progressive removal of the stuck bits. The
Fig. 6 shows the experimental cross sections of stuck bits in
the samples (A2, B2, C2, and D2) that were irradiated without
being supplied operational power. The partial ﬂux (about 3%)
exposed in sample A2 was ascribed to the radiation during active sample operations.
Fig. 7 shows the ratios of the cross sections of stuck bits from
powered and unpowered irradiations. In the case sample C2,
there were no stuck bits under unpowered irradiation. The cross
section of samples A1 and D1 was about 2.5 time higher than
those of samples A2 and D2. A. M. Chugg et al. previously
reported that the stuck bits due to displacement damages occurred equally in both the powered and unpowered states [13];
in context, the stuck bits in Fig. 7 are present not exclusively
because of the displacement damage effect in the products of
manufacturers A and D. Detailed examinations of failing mechanisms with respect to power dependency will be reported further studies.
E. Progressive Occurrences of Stuck Bit with Increasing
Annealing Temperatures
In Fig. 8, the stuck bits from all high-temperature annealing
tests are re-classiﬁed by their recurrence. Five tests were conducted in total. However, the maximum number of stuck bit
recurrence events was three. Many stuck bits disappeared progressively after annealing at low temperatures. Moreover, it was
observed that some stuck bits changed their type from MSB to
SSB, as test temperatures were elevated; however, the reverse
case–from SSB and MSB–was observed once. In certain cases,
the stuck bits that were not detected at a lower temperature
showed up after higher temperature annealing. For example, all
stuck bits from the sample C1 appeared once; however, the stuck
bits in sample D1 had appear up to three times before disappearing completely after annealing at
.
F. Retention Time Experiments with Post Annealed Samples
Fig. 9 shows the number of failing words with the ALL0
pattern by using previously annealed samples of A1, C1, and
D1. Sample B1 was excluded from this experiment because the
sample was irradiated again with the proton beam after the ﬁrst
annealing process. The numbers of failing words in samples C1
and D1 were zero. It should be noted that the result in Fig. 2(a)
shows that no stuck bit was observed with the ALL0 patterns for
524
Fig. 5. Cross-section depending on high-temperature annealing tests of sams refresh
ples irradiated with power supplied to samples: (a) is for SSB with
s refresh cycle, (c) is for SSB with
s recycle, (b) is for MSB with
s refresh cycle.
fresh cycle, and (d) is for MSB with
samples C1 and D1. Somehow, the nature of cell design with
0 state from two manufactures C and D is not affected by the
leakage current failure mechanism in both the retention time test
and the stuck bit.
IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 62, NO. 2, APRIL 2015
Fig. 6. Cross section depending on high-temperature annealing tests of samples
s
irradiated when power was not supplied to samples: (a) is for SSB with
s refresh cycle, (c) is the SSB with
refresh cycle, (b) is for MSB with
s refresh cycle, and (d) is for MSB with
s refresh cycle.
Since the number of stuck bits could be characterized further
based on the temperature as well as retention time, a bleed-down
LIM et al.: STUCK BITS STUDY IN DDR3 SDRAMs USING 45-MeV PROTON BEAM
525
Fig. 7. Cross section ratios of stuck bits in powered samples versus unpowered
samples for four different manufactures. The ratio is cross section of sample X1
divided by the same of sample X2 where X represents a manufacturer.
Fig. 8. Stuck bits are re-classiﬁed based on ratio of their appearance across ﬁve
s.
annealing tests with refresh time of
Fig. 10. Number of failing words for various retention time under ALL1 pat(room temperature), (b)
, and (c)
.
tern; at (a)
Fig. 9. Number of failing words with various retention times usingALL0 pattern under room temperature for annealed samples of A1, C1 and D1.
test was performed for three different temperatures with annealed samples A1, C1, and D1 and the results are shown in
Fig. 10. The number of failing words increased rapidly with increasing temperature. Samples C1 and D1 showed similar tendencies in terms of the number of failing words for the three
temperatures in Fig. 10. For sample A1, there was a sharp increase in the number of failing words at
.
It is important to note that bit failures were not observed
within the retention time of 64 ms. However, it was evident that
the irradiated samples showed worse retention time even after
annealing at up to
in comparison with generally observed
SDRAMs retention time, which is about 4 seconds [24], [25].
The results in Fig. 10 indirectly imply that the stuck bits in this
work can be ascribed to the leaky failing mechanism rather than
stuck-at type failure.
V. CONCLUSIONS
In this paper, an experimental study was performed for stuck
bits in DDR3 components from four different manufacturers by
using the MC-50 proton beam. Intermittently repeated SSBs or
MSBs were detected during and after the beam test. Different
number of stuck bits were detected under different test patterns, and they were fully recovered after annealing at
.
The retention tests with annealed samples showed worse retention times compared with un-irradiated samples, even after annealing at
. It conﬁrmed that the stuck bits observed in
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IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 62, NO. 2, APRIL 2015
this work were due to the leaky failure mechanism than due to
stuck-at type damage.
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