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Lecture 15
Biasing and Loading Single Stage FET and BJT Amplifiers
The Building Blocks of Analog Circuits - III
In this lecture you will learn:
• Current and voltage biasing of circuits
• Current sources and sinks in CS/CE, CG/CB, and CD/CC amplifiers
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
The Common Source Amplifier
VDD
R
ID
RS
vs
+
+
VOUT  v out
+
-
VBIAS
-
Open circuit voltage gain:
Av 
v out
i R
  d   g m ro || R 
v in
v in
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
1
The Common Source Amplifier: Problems
Open circuit voltage gain:
Av 
v out
  g m ro || R 
v in
In saturation:
gm 
I D
 2k n I D 1  nVDS 
VGS
To achieve large gain one needs:
1) A large DC current bias ID in order to get a large gm
2) A large value of the resistor R
Both these requirements cannot be met easily;
 Not easy to realize large resistors on chips
 A large resistor R will limit the maximum value of the DC current bias ID (because
the potential drop IDR can become large enough to put the FET in the linear region
where gm and the gain will be small
 Resistors also cannot supply a constant current to a load connected to the
amplifier (we will discuss this more when we discuss digital logic circuits)
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
The Common Source Amplifier with a Current Source
VDD
I BIAS
RS
+
vs
+
ID
+
VOUT  v out
-
VBIAS
-
What is needed is an ideal
current source in the drain that
can supply a large DC current
and at the same time has a
large small signal resistance
The incremental (or differential
or small signal) resistance
looking into an ideal current
source is infinite
Av 
v out
  g m ro
v in
An ideal current source, of course, does not exist
But one can certainly do much better than using a resistor in the drain
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
2
The Common Source Amplifier with a Current Source: DC Biasing
I D  I BIAS 
W
 n Cox VGS  VTN 
2L
2
1  nVDS 
The above equation determines VDS = VOUT
for a given value of VGS = VBIAS
ID
I BIAS
Increasing VBIAS
0
0
VDS
VOUT
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
The CS Amplifier with a Current Source: Small Signal Analysis
ig
+
v in
-
id
Drain
Gate
+
v gs
-
0
g mv gs
g mbv bs
Source
ro
+
v out
v bs
Base
+
Open circuit voltage gain:
Av 
v out
  g m ro
v in
Output resistance:
Rout  ro
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
3
Large Signal Model of a Current Source
Large signal circuit model
I BIAS
The output
resistance of
the current
source
Ideal
current
source
roc
I BIAS
 A large signal model of a current source
 roc is large for a good current source and
infinite for an ideal current source
A current source
IOUT
+
roc
I BIAS
VOUT
Slope
IOUT
dIOUT
1

dVOUT roc
IBIAS
VOUT
One can have any voltage at the at the output terminals of a good current source and
the current delivered will remain mostly constant
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
Small Signal Model of a Current Source
IOUT
+
roc
I BIAS
VOUT
Slope
IOUT
dIOUT
1

dVOUT roc
IBIAS
VOUT
Small signal circuit model
I BIAS
roc
A current source
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
4
PFET Loaded NFET Common Source Amplifier
A PFET
approximation
to a current
source
V
VDD
I BIAS
ID
RS
vs
-
VBIAS
ID
+
+
VOUT  v out
+
vs
A PFET
load
B
RS
+
+
VDD
VOUT  v out
+
-
VBIAS
-
-
An ideal current source, of course, does not exist
But one can certainly do much better than using a resistor in the drain
Use a PFET!
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
Current Sources and Transistors
Slope
IOUT
Current Sources:
dIOUT
1

dVOUT roc
IOUT
IBIAS
I
I
roc
VOUT
VOUT
One can have any voltage at the at the output terminals of a good current source
and the current delivered will remain mostly constant
Slope
IOUT
ID
IOUT
dIOUT
 go
dVOUT
VOUT
VOUT
Characteristics in saturation resemble
that of a non-ideal current source!
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
5
PFET Loaded NFET: Large Signal Analysis
ID
NFET
PFET
M2
VB
VBIAS
M1
VDS1  VOUT  VDD  VDS 2
0
0
DC value of the output
voltage (Both FETs in
saturation)
I D1  I D  I D 2
VDD VOUT
Instead of the resistive load line, we now have the full ID vs VDS curves of the PFET
The biasing voltages need to be selected carefully, otherwise one of the transistors
can go into the linear region!!
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
PFET Loaded NFET: Large Signal Analysis
ID
PFET
VB
NFET
M2
VBIAS
M1
VDS1  VOUT  VDD  VDS 2
I D1  I D  I D 2
0
0
DC value of the output VDD VOUT
voltage (PFET in the
linear region)
Instead of the resistive load line, we now have the full ID vs VDS curves of the PMOS
The biasing voltages need to be selected carefully, otherwise one of the transistors
can go into the linear region!!
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
6
PFET Loaded NFET: Transfer Curve
I: VIN < VTN
M2
M1 cut-off
II: VIN > VTN & VOUT > VIN - VTN & VOUT > VB - VTP
M1 saturation, M2 Linear
III: VIN > VTN & VOUT > VIN - VTN & VOUT < VB - VTP
M1
M1 saturation, M2 saturation
IV: VIN > VTN & VOUT < VIN - VTN & VOUT < VB - VTP
M1 linear, M2 saturation
VOUT
II
VIN  VTN
VDD
VB  VTP
III
III
I
Increasing VIN
IV
II
IV
0
I
0
VTN
VIN
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
PFET Loaded NFET: Large Signal Analysis
Assuming the biasing is correct, both the FETs are in
saturation
M2
Equate the drain current magnitudes of the two FETs
Then the only unknown will be VOUT ; solve for it
M1
Verify that the obtained value of VOUT does indeed
result in both the transistors being in saturation
NFET
I D1 
kn
VGS1  VTN 2 1  nVDS1   k n VBIAS  VTN 
2
2
2
1  nVOUT 
PFET
ID2  
kp
2
VGS 2  VTP 2 1   pVDS 2   
kp
2
VB  VDD  VTP  2 1   p VOUT
 VDD 
Equating:
I D1  I D  I D 2

kn
VBIAS  VTN 
2
2
1  nVOUT  
kp
2
VB  VDD  VTP  2 1   p VDD  VOUT 
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
7
PFET Loaded NFET: Small Signal Analysis
i g 2 Gate2
M2
+
v gs 2
-
PFET
M1
Drain2
id 2
ro 2
g m 2v gs 2
Source2
Looking into the drain end of
the PFET, what does one see?
NFET
RS
vs
Drain1 i d 1
i g 1 Gate1
+
+
v in
-
-
+
v gs1
-
ro1
g m1v gs1
+
v out
-
Source1
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
PMOS Loaded NMOS: Small Signal Analysis
Drain2
id 2
M2
ro 2
M1
Looking into the drain end of
the PFET, what does one see?
NFET
RS
vs
Drain1 i d 1
i g 1 Gate1
+
+
v in
-
-
+
v gs1
-
g m1v gs1
Source1
ro1
+
v out
-
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
8
PFET Loaded NFET: Small Signal Analysis
id 1
i g1
M2
+
v gs1
-
+
v in
g m1v gs1
ro1
-
ro 2
+
v out
-
M1
Open circuit voltage gain:
Av 
v out
  g m1ro1 || ro 2 
v in
Output resistance:
Rout  ro1 || ro 2
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
PFET Loaded NFET: The Cascode PFET Load
VDD
PFET
load
VB 3
VB 2
M3
ID
+
+
M1
+
VBIAS
This topology is called the
“Cascode”
M2
RS
vs
This load has a larger resistance
looking into it
VOUT  v out
-
-
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
9
Cascode PEFT Load: Small Signal Analysis
The image part with relationship ID
rId19 was not found in the file.
Drain3
Gate3
PFET
load
PFET
+
v gs 3
-
id 3
ro 3
g m 3v gs 3
Source3
i g 2 Gate2
PFET
+
v gs 2
-
Drain2
id 2
ro 2
g m 2v gs 2
Source2
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
Cascode PFET Load: Small Signal Analysis
Drain3
PFET
load
id 3
ro 3
i g 2 Gate2
PFET
+
v gs 2
-
Drain2
g m 2v gs 2
id 2
ro 2
Source2
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
10
Cascode PFET Load: Small Signal Analysis
i g 2 Gate2
+
v gs 2
-
PFET
load
Drain2
id 2
ro 2
g m 2v gs 2
Source2
ro 3
Resistance looking into the current source is:
ro 2  ro 3  g m 2 ro 2 ro 3  g m 2 ro 2 ro 3
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
Cascode PFET Load: Small Signal Analysis
NFET
PFET
load
id 1
ig1
+
v in
+
v gs 1
-
g m1v gs1
ro1
g m 2 ro 2 ro 3
-
+
v out
-
Open circuit voltage gain:
Av 
v out
  g m1ro1 || g m 2ro 2 ro 3    g m1ro1
v in
Output resistance:
Rout  ro1 || g m 2 ro 2ro 3   ro1
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
11
The Common Source Amplifier: General Topology
V
V
I BIAS
VIN
VOUT
VOUT
VIN
I BIAS
V
V
NFET
PFET
Large input resistance
Large output resistance
Large voltage gain
Large current gain
 Good transconductance
amplifier
V + is the most positive voltage in the circuit
V - is the most negative voltage in the circuit
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
The Common Gate Amplifier: General Topology
V
V
I BIAS
VIN
VOUT
VG
VOUT
VG
VIN
I BIAS
V
V
NFET
Small input resistance
Large output resistance
Large voltage gain
Small current gain
 Good current buffer
PFET
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
12
The Common Drain Amplifier: General Topology
V
V
I BIAS
VOUT
VIN
VOUT
VIN
I BIAS
V
NFET
V
PFET
Large input resistance
Small output resistance
Small voltage gain
Large current gain
 Good voltage buffer
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
The Common Emitter Amplifier: General Topology
V
V
I BIAS
VIN
VOUT
VOUT
VIN
I BIAS
V
V
NPN
PNP
V + is the most positive voltage in the circuit
V - is the most negative voltage in the circuit
Medium input resistance
Large output resistance
Large voltage gain
Large current gain
 Good transconductance
amplifier
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
13
The Common Base Amplifier: General Topology
V
V
I BIAS
VIN
VOUT
VB
VOUT
VB
VIN
I BIAS
V
V
NPN
PNP
Small input resistance
Large output resistance
Large voltage gain
Small current gain
 Good current buffer
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
The Common Collector Amplifier: General Topology
V
V
I BIAS
VOUT
VIN
VOUT
VIN
I BIAS
V
V
NPN
PNP
Large input resistance
Small output resistance
Small voltage gain
Large current gain
 Good voltage buffer
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
14
Chip-Based Current Sources and Voltage Sources
We have realized a decent load but ……
How does one generate voltage levels on a
chip for biasing??
Current and voltage biasing of circuits require
transistor based current and voltage sources
on a chip!
What are the good figures of merit of chipbased voltage and current sources?
ECE 315 – Spring 2007 – Farhan Rana – Cornell University
15