Agenda - How to characterize and debug high speed digital links on your physical prototype – what part of your design is eating up your Eye margins? Part 2: • • • Eye closure analysis RJ/DJ separation ISI/Equalization RNDN separation BER contour Margin is not for free Lower power (example MIPI Mphy) Lower cost (PCB material etc.) Higher speed or Robustness Practical application of instrumentation -> T&M contribution must be reduced (scope techniques to reduce jitter+ noise) Separating receiver test from the Tx/channel TX Channel RX Capturing an eye diagram The easiest way to get an overall idea of the quality of the serial signal Trigger on Clock signal (if available) as the rough first pass to build Eye Diagram Eye Diagram is the superposition in the middle of the screen of 3 bits Multiple case combined form the Eye (000,001,010,011,100,101,110,111) Preceding bits might impact the ones you’re seeing - this is called Inter Symbol Interferences Use Clock Recovery with PLL Emulation on 8B/10B signal and memory folding to build eye Building an Eye diagram the synchronous way: Explicit Clock used as Trigger 101 Sequence 011 Sequence Overlay of all combinations What represents “good enough”? The eye-mask is the common industry approach to measure the eye opening Failures usually occur at mask corners • But what is cause of failure? Violating USB FS 12Mb/s Eye Diagram Good Displayport Eye Diagram What Is jitter? What are Inter-Symbol Interferences? AGILENT SI Seminar 2012 by Pascal GRISON ISI Jitter is coming from Signal Distorsions in Transmission Channel Page 6 Impact of Tx De-Emphasis on Rx Signal To reduce ISI at RX Side, Most TX implement De-Emphasis AGILENT SI Seminar 2012 by Pascal GRISON 7 Press ESC during Video to Skip Video Where does jitter come from? Transmitter Receiver •Lossy interconnect (ISI) •Impedance mismatches (ISI) •Crosstalk (PJ) •Thermal Noise (RJ) •DutyCycle Distortion (DCD) •Power Supply Noise (RJ, PJ) •On chip coupling (PJ, ISI) •Termination Errors (ISI) Total jitter components TJ: Total Jitter (convolution of RJ (based on BER) & DJ, and measured in peak-to-peak. RJ: Random Jitter (rms) DJ: Deterministic Jitter (peak-to-peak). • PJ: Correlated & uncorrelated Periodic Jitter (caused by cross-talk and EMI) • DDJ: Data Dependent Jitter • DCD: Duty Cycle Distortion (caused by threshold offsets and slew rate mismatches). • ISI: Inter-Symbol Interference (caused by BW limitation and reflections). Jitter probability: BER J pk - pk = J deterministic = n ´ s random How do real time ‘scopes measure jitter? NRZ Serial Data Recovered Clock Jitter Trend Jitter Spectrum Units in Time Units in Time Jitter Histogram Why is Noise important? Noise eats up margin •By adding vertical noise •By increasing jitter Noise is a significant concern in real-time scopes: • Wideband front end • High-speed digitizer Why is vertical noise floor important ? Let’s consider theoretical signals with Zero jitter and fixed voltage noise with three different edge speeds and crossing a Threshold at 50% 1)Voltage noise translates directly to Timing uncertainty (Jitter) 2)Higher Vertical Noise Floor translates to higher Timing uncertainty 3)At constant amplitude noise floor, slower edge speed translates to higher Timing uncertainty Noise sources Probe Probe Noise Quantify your scope noise!: • AC Vrms Measurement • Histogram-standard deviation • FFT Amplifier Attenuator A/D Noise Quantization Noise What about eye height closure? Page 17 Technology Deployment Agilent Private September 22nd, 2008 Noise Analysis Analyze the amplitude characteristics to support receiver sensitivity design. • Arbitrary location in the eye • Noise component decomposition • Extrapolation to specific target BER • Analysis graphs ala Jitter Separation • Removal of Oscilloscope Noise 18 EZJit Complete Graphs Ones and Zeroes Composite Interference Histograms 19 EZJit Complete - ISI vs Bit: affect of channel on bit levels 21 VdiVW measurement procedure Ringback could cause the measurement using the mask corners to be incorrect. Worst case VdiVW – voltage must stay above/below VdiVW for TdiVW time. Margin should really be the min voltage in the entire TdiVW range. 22 Confidentiality Label June 5, 2013 New Tests (tDIVW and vDIVW) The smallest margin to the mask of the 6 timing points is reported as tDIVW measurement result. The smallest margin to the mask of the 6 voltage points is reported as vDIVW measurement result. 23 Confidentiality Label June 5, 2013 DDR 4 tDIVW Margin to Mask Detail (up to 2133). 62.5ps 62.5ps 125ps % Margin is then (Actual-Spec)/Spec*100% or (118.8ps-62.5ps)/62.5ps * 100% = 90% 24 Confidentiality Label June 5, 2013 DDR 4 Eye Margin to Mask (2400 and greater) BER contour 1E-12 At DDR4/2400 and above the extrapolated BER contour is used. Since direct measurement beyond 1e-7 is extremely slow a standard dual Dirac model is used to compute the contour from actual measured waveforms. 25 Confidentiality Label June 5, 2013 DDR 4 Eye Margin to Mask (2400 and greater) Margin is really calculated the same, to BER contour rather than direct measurement. TdiVW margin = min time from mask corner VdiVW margin = min voltage from mask corner Margin = (Actual-Spec)/Spec *100% 26 Confidentiality Label June 5, 2013 Where is the Receiver – Transmitter boundary? 2) Want to see here Driver Trace Vias PCB Trace 1) Measure here? 4) Want to see here Die Package Card Receiver Backplane Die Package Card 3) Measure here? Specify here! JITR: New Meas in HS Buses May 2013 Summary – Tx Channel Characterization • Tx Channel characterization is all about the ‘eye’ • ALL measurements essentially measure noise. • ISI is the dominant issue at high data rates. • Rj is a dominant source of jitter (14x S.D.) in measurements. • Rj is proportional to Voltage noise. • Wideband measurement systems are inherently prone to noise. • Moving the reference plane can significantly simplify electrical layer testing. Page 28 Technology Deployment Agilent Private September 22nd, 2008 Q-Series Acquisition System Each Board Implements 80 GSa/s Faraday Caged Front-End Module CMOS A/D Converter Memory Controller Standard DDR-2 Acquisition Memory 640 Gb/s at this interface (320 lanes at 2 Gb/s each) Analog Signal Path 6 Custom ASICs in Proprietary Indium Phosphide Process Sampling Demux Preamp Probe Amplifier • • • • ~2 mm2, 100 devices, 1 Watt Adjustable RIN Adjustable common-mode VOUT Thermal compensation Calibration Generator • • • • ~4 mm2, 150 devices, 2 Watts Adjustable RIN Selectable gain and bandwidth Thermal compensation Trigger • • • • ~6 mm2, 350 devices, 7 Watts Adjustable aperture Adjustable delay and skew ISI compensation ADC Buffer Amp • • • • ~4 mm2, 350 devices, 2 Watts Internal oscillator Adjustable calibration signal Adjustable edge speed • • • • ~4 mm2, 450 devices, 2 Watts Adjustable threshold Adjustable hysteresis Thermal compensation • ~3 mm2, 50 devices, 1 Watt • Adjustable RIN • ISI compensation Compound Semiconductor Choices Material Properties Parameter SiGe GaAs InP (depends on alloy composition) Energy gap (eV) 0.9 1.42 1.34 Mobility (cm²/V·s) 3300 8500 5400 300K Max electron velocity (107 cm/s) 1 2 2.5 Critical field (V/µm) 20 40 50 Compared to other semiconductors, Indium Phosphide has: 1. Highest electron velocity  higher device speed 2. Highest critical field  higher voltage swings and power BVceo versus Ft for Bipolar Technologies InP SHBT & GaAs UM BVceo (Volts) InP DHBT HB2A Velocium GCS Lucent TRW HB2B SFU (Agilent) Si &SiGe NTT HRL IBM 0 50 Hitachi 100 AG100 • IBM Conexant 150 NTT 200 Ft (GHz) 250 300 Custom Packaging Technology Used for Front-End and Probe Amplifier Multichip Modules Front view with lid Custom Packaging Technology Construction Details Conductive silicone substrate-to-PCB attach Coaxial Connector AluminaSubstrate Substrate Ceramic IC Laminate Substrate Metal Lid Host PCB Conductive silicone lid-to-substrate attach Back view with SMPM connectors Custom Packaging Technology Integrated Coaxial Transmission Lines Single-ended preamp input 10 GHz differential sample clock Custom A/D Architecture 80 x 250 MSa/s Conversion with 80 Lanes of 2 Gb/s Outputs Agilent’s 90000 Q-series Oscilloscope Real-time Bandwidth: 4 channels @ 33 GHz, 2 channels @ 63 GHz 5-chip Module Probe Amp ADC Amp Trigger IC Input Preamp InP Chipset Sampling DeMux Acquisition Board Calibration IC Differentiating Technology… • High bandwidth InP chipset in Agilent’s proprietary “HB2B Process” • Proprietary epitaxial material • Packaged in Agilent’s proprietary “QuickFilm” modules Enables Differentiating Performance… • Analog bandwidth to 63 GHz • Industry leading low-noise and superior signal integrity In The World’s Fastest and Most Accurate Scope… RealEdge Technology Lab measurement summary System Design Interconnect Design Active Signal Analysis Compliance Test HSD Design: To optimise mutually HSD Lab Verification: To prove trade-off exclusive cost, power consumption and decisions through margin analysis and robustness tradeoffs compliance test This requires you to:  Fully understand your Rx chain requirements (for which you need Symbol error rate awareness and accurate jitter injection…)  Tighten design margins as far as possible on timing/power/cost tradeoff for maximum product competitiveness (for which you need smallest possible contribution from measurement system) Agilent calibrated jBERT and low noise/jitter ‘Scope technology lets you sign off most competitive designs!