How to Identify and Prevent ESD Issues Using PathFinder™

How to Identify and Prevent ESD Issues
Using PathFinder™
Design Automation Conference 2014
6/23/2014
© 2014 ANSYS, Inc.
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What is ESD?
Electrostatic Discharge
“A transfer of charge between two bodies at different electrostatic potentials, either
through contact or via an ionized ambient discharge (a spark).”
I/O pin
Intended path
Unintended path
ESD Clamps
Drain/Source junction
or gate-oxide damage
I/O buffers
ESD Clamps
IO Pad
High current event causing
latent or catastrophic failures to IC
Metal/via melt-down
6/23/2014
© 2014 ANSYS, Inc.
2
What is ESD?
Human Body/Machine Model(HBM/MM)
Charged Device Model(CDM)
+++
Discharge currents for different
types of ESD events
Source: http://www.esda.org/documents/IndustryCouncilWhitePaper2.pdf
6/23/2014
© 2014 ANSYS, Inc.
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PathFinder™: SoC and IP ESD Integrity
Layout (DEF/GDS)
Spice Netlist/
Clamp Models
Technology
gndA
vdd
vddA
PathFinder
gnd
ESD rules
gndB
6/23/2014
© 2014 ANSYS, Inc.
vddB
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PathFinder™: SoC and IP ESD Integrity
Layout (DEF/GDS)
Spice Netlist/
Clamp Models
Technology
ESD rules
R-Extraction
gndA
vddA
PathFinder
gnd
vdd
gndB
6/23/2014
© 2014 ANSYS, Inc.
vddB
5
PathFinder™: SoC and IP ESD Integrity
Layout (DEF/GDS)
Spice Netlist/
Clamp Models
Technology
Layout Connectivity
Checks
Layout Connectivity Checks
gndA
X
vddA
PathFinder
gnd
vdd
Disconnected
clamps
Missing pin2pin
ESD path
Isolated
bumps
gndB
6/23/2014
ESD rules
© 2014 ANSYS, Inc.
vddB
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PathFinder™: SoC and IP ESD Integrity
Layout (DEF/GDS)
Layout Connectivity
Checks
gnd
vdd
gndA
R?
vddA
R?
R?
Any
Point
R?
R?
gndB
6/23/2014
ESD rules
Resistance Checks
PathFinder
Resistance Checks
Spice Netlist/
Clamp Models
Technology
© 2014 ANSYS, Inc.
R?
vddB
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PathFinder™: SoC and IP ESD Integrity
Layout (DEF/GDS)
Layout Connectivity
Checks
gnd
gndA
X
vddA
Interconnect Failure
Checks
vdd
R?
Metal/via
bottlenecks
Disconnected
Any
R?
clamps Point
Missing pin2pin
ESD path
R?
R?
R?
R?
Isolated
Current crowding
bumps
on diode fingers
gndB
6/23/2014
ESD rules
Interconnect
Failure
Checks
Layout
Connectivity
Checks
Resistance
Checks
R-Extraction
PathFinder
Resistance Checks
Spice Netlist/
Clamp Models
Technology
© 2014 ANSYS, Inc.
vddB
8
PathFinder™: SoC and IP ESD Integrity
Layout (DEF/GDS)
Layout Connectivity
Checks
Dynamic Checks
gnd
gndA
X
vddA
Interconnect Failure
Checks
vdd
R?
Root-cause Analysis
Metal/via
bottlenecks
Disconnected
Any
R?
clamps Point
IP/Full-chip Capacity
Missing pin2pin
ESD path
Monitor
device stress
R?
R?
R?
R?
Early Stage to Sign-off
Isolated
Current crowding
bumps
on diode fingers
gndB
6/23/2014
ESD rules
Dynamic
Checks
Interconnect
Failure
Checks
Layout
Connectivity
Checks
Resistance
Checks
R-Extraction
PathFinder
Resistance Checks
Spice Netlist/
Clamp Models
Technology
© 2014 ANSYS, Inc.
vddB
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Common ESD Issues in SoCs
ESD Failure Types
ESD
Device
40%
BEOL
30%
misc
5%
ESD
Cross Network
Domain 10%
15%
Device breakdown
Interconnect melt-down
Cross-domain ESD issues
ESD failures impact first silicon success
6/23/2014
© 2014 ANSYS, Inc.
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Device Breakdown
Why is it more important now?
What are the common causes for such failures?
ESD Design window from
130 nm to 32 nm technology
High ESD bus resistance
+ve Zap
Power2 Ground Zap
vcc
V>V(break-down)
D1
sig
D2
Source: Cao et al., ESD design challenges and strategies in deeplyscaled integrated circuits, PhD dissertation, Stanford Univ, 2010.
6/23/2014
-ve Zap
vss
© 2014 ANSYS, Inc.
Functional
devices
Inefficient or
missing clamps
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Device Breakdown
# Signal bus R check
BEGIN_ESD_RULE
NAME sigbump2diode_Rcheck
TYPE BUMP2CLAMP
ARC_R 0.1
TERMINAL_NET_GROUP SIGNAL
CLAMP_TYPE1 D1 D2
END_ESD_RULE
How can PathFinder help ?
Power Bus Resistance check
Signal Bus R checks
#Power Bus R Check
BEGIN_ESD_RULE
NAME Pwr_Bus_R_check
TYPE CLAMP2CLAMP
ARC_R 0.1
TERMINAL_NET_GROUP POWER GROUND
FROM_CLAMP_TYPE D1 D2
TO_CLAMP_TYPE PWRCLMP
END_ESD_RULE
#Power2Ground R check
BEGIN_ESD_RULE
NAME PWR2GND_R_check
TYPE BUMP2BUMP
LOOP_R 5
PARALLEL_R 1
TERMINAL_NET_GROUP POWER GROUND
CLAMP_TYPE PWRCLMP
SHORT_BUMP_IN_NET_GROUP POWER GROUND
END_ESD_RULE
6/23/2014
vcc
D1
Functional
devices
sig
D2
vss
Power2Ground R check
© 2014 ANSYS, Inc.
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Interconnect Melt-down
Why is it more important now?
What are the common causes for such failures?
Current crowding on
ESD device
Insufficient via-cuts/
ineffective clamps
Positive Zap
VCC
IO Pad
D1
Clamps
Pad
D2
Negative Zap
Mx
My
Mz
RD
L
6/23/2014
VSS
Insufficient wire width
on ESD pathways
© 2014 ANSYS, Inc.
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Interconnect Melt-down
How can PathFinder help ?
# Signal bus CD check
BEGIN_ESD_RULE
NAME signal_bump2diode_CD_check
TYPE CD
ZAP_CURRENT 1.3A # ~2kV HBM zap
B2C_NET_GROUP SIGNAL
SHOTGUN_MODE 1
END_ESD_RULE
#Power Bus CD Check
BEGIN_ESD_RULE
NAME Pwr_Bus_CD_check
TYPE CD
ZAP_CURRENT 1.3A #~2kV HBM Zap
C2C_NET_GROUP POWER GROUND
FROM_CLAMP_TYPE D1 D2
TO_CLAMP_TYPE PWRCLMP
END_ESD_RULE
#Power2Ground CD check
BEGIN_ESD_RULE
NAME PWR2GND_CD_check
TYPE BUMP2BUMP
ZAP_CURRENT 1.3A # ~2kV HBM Zap
TERMINAL_NET_GROUP POWER GROUND
CLAMP_TYPE PWRCLMP
SHORT_BUMP_IN_NET_GROUP POWER GROUND
END_ESD_RULE
6/23/2014
Power2Ground CD checks
Signal Bus CD checks Power/Ground Bus CD checks
VCC
IO Pad
Power
Clamps
D1
Pad
D2
Define Interconnect CD limits
Mx = x mA/um
My = y mA/um
Mz = z mA/um
RDL = r mA/um
© 2014 ANSYS, Inc.
# Clamp IV Model
BEGIN_CLAMP_IV
NAME <I-V_clamp_name>
Ron <Ron+> [<Ron->]
VT1 <VT1+> [<VT1->]
VH <VH+> [<VH->]
ROFF <Roff+> [<Roff->]
END_CLAMP_IV
VSS
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Cross-domain ESD Issues
Why is it more important now?
CPU CORE
(VDDC)
High Speed I/O
GPU
(VDDG)
VDD2
VDD1
Power
Clamp
VSS1
Analog/RF
(AVDD)
Memory/Cache
(VDDM)
Unintentional ESD
discharge path
Intentional ESD
discharge path
RVSS
GPIO
Analog IO
GPIO
GPIO
What are the common causes for such failures?
GPIO
Bridge diodes
High Ground bus R
Power
Clamp
VSS2
Insufficient/unconnected
bridge diodes
Bridge diodes
6/23/2014
© 2014 ANSYS, Inc.
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Cross-domain ESD Issues
How can PathFinder help ?
# Clamp connectivity Checks in
PathFinder
TCL> perform clampcheck
# pin2pin connectivity
\ –allNetConn
# report disconnected net pairs
\ -rptDisconn
# Signal bus CD check
BEGIN_ESD_RULE
NAME VSS_bus_R_Check
TYPE C2C
FROM_CLAMP_TYPE PWRCLMP
TO_CLAMP_TYPE B2B_DIODE
ARC_R 0.5
END_ESD_RULE
#Cross-domain CD Check
BEGIN_ESD_RULE
NAME Cross_domain_CD_Check
TYPE CD
ZAP_CURRENT 1.3A #~2kV HBM Zap
NET_PAIR VDD1 VSS2
END_ESD_RULE
6/23/2014
Cross-domain
CD checks
VDD1
VDD2
Power
Clamp
VSS1
Power
Clamp
VSS2
RVSS
Bus Resistance
Checks
Bridge diodes
Bridge diodes
© 2014 ANSYS, Inc.
Clamp connectivity
checks
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PathFinder Core Technologies & Benefits
Capacity
Accuracy
Usability
IV curve support
Current crowding
on diode fingers
Root-cause the
bottleneck in ESD bus
Full-chip capacity with
package impact
6/23/2014
ESD snap-back device
modeling
© 2014 ANSYS, Inc.
Rich GUI for debug and
optimization
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ESD-aware SoC Design Flow
Analysis driven clamp
placement
gnd

ESD
Clamp

6/23/2014
IO Ring
IP level
Floor plan
© 2014 ANSYS, Inc.
X
GPU
(VDDG)
Analog/
RF
(AVDD)
CPU CORE
(VDDC)
Memory/Cache
(VDDM)
GPIO
ESD
Clamp
ESD
Clamp
High Speed I/O
GPIO
GPIO
vdd
IO Pad
level
Resistance and current
density limit sign-off
Analog IO
IO ring ESD bus planning
GPIO
Final sign-off
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Summary
•
Full chip-level ESD integrity analysis solution
•
PathFinder coverage:
– Layout connectivity checks
– Resistance checks
– Interconnect failure checks
– Dynamic CDM checks for IPs
•
6/23/2014
Part of ESDA reference flow and
TSMC reference flow
© 2014 ANSYS, Inc.
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