ESD Association Regional Tutorials October 7-8, 2014 ESD Device Design Essentials October 9, 2014 Advanced ESD Characterization and Test Methods Fraunhofer Institution for Modular Solid State Technologies EMFT Hansastr. 27d, 80686 Munich, Germany • Lunch and refreshments provided. Register Online at www.esda.org/onlineregistrations.html Be proactive! Get engaged! Learn from industry professionals to experience device protection technologies and limitations. ESD Device Design Essentials October 7-8, 2014 Instructors: Gianluca Boselli, Texas Instruments; Harald Gossner, Intel Corporation This two-day seminar consists of concentrated versions of twelve ESDA tutorials which comprise the ESDA Device Design Certification Program. Gianluca Boselli •ESD On-Chip Protection in Advanced Technologies •SPICE-Based ESD Protection Design Utilizing Diodes and Active MOSFET Rail Clamp Circuits •EOS/ESD Failure Models and Mechanisms •On-Chip ESD Protection in RF Technologies •Charged Device Model Phenomena and Design •Latch-up Physics and Design •Circuit Modeling and Simulation for On-Chip Protection •Troubleshooting On-Chip ESD Failures •Device Testing--IC Component Level: HBM, CDM, MM, and TLP •Impact of Technology Scaling on ESD High Current Phenomena and Implications for Robust ESD Design •Transmission Line Pulse Measurements: Parametric Analyzer for ESD On-Chip Protection •System Level ESD/EMI: Testing to IEC and other Standards Harald Gossner Day 1 October 7 PART I (8:00 AM-Noon) This part reviews the fundamentals of ESD testing, high-current physics, and ESD modeling. The focus is on device-level (HBM, CDM, MM, TLP) and system level testing, impact of technology scaling on ESD high current phenomena, as well as circuit modeling and simulation for on-chip protection. PART II (1:00 PM-5:00) The principles from part I are then applied to ESD Protection Design. This part describes ESD on-chip protection in advanced technologies, SPICE-based ESD protection design utilizing diodes, and active MOSFET rail clamp circuits. Day 2 October 8 PART III (8:00 AM-Noon) This part describes special ESD design cases, including Charged Device Model (CDM) phenomena and design, on-chip ESD protection in RF Technologies, and latch-up physics and design. PART IV (1:00 PM-5:00) The final section discusses EOS/ESD failure models and mechanisms. The seminar concludes with practical examples for troubleshooting of on-chip ESD failures. 3/12/2014 Setting the Global Standards for Static Control! EOS/ESD Association Inc. • 7900 Turin Rd Bld 3 • Rome NY 13440 Phone 315-339-6937 • Fax 315-339-6793 • [email protected] • www.esda.org ESD Association Regional Tutorials October 7-8, 2014 ESD Device Design Essentials October 9, 2014 Advanced ESD Characterization and Test Methods Fraunhofer Institution for Modular Solid State Technologies EMFT Hansastr. 27d, 80686 Munich, Germany • Lunch and refreshments provided. Register Online at www.esda.org/onlineregistrations.html Advanced ESD Characterization and Test Methods October 9, 2014 Instructors: Horst A. Gieser and Heinrich Wolf, pAdvanced ESD Characterization 9:00 a.m. - 10:30 a.m. How to gain accurate insight in the electrical behavior of protection elements and of elements to be protected. DC characterization, electrothermal characterization, (very fast) transmission line pulsing, repetitive ps-Pulsing. Results using the Agilent 62 GHz Single Shot Oscilloscope, Failure criteria leakage and RF-degradation. pESD Failure Reproduction and Alternative Models 10:30 a.m. - 12:00 Noon How to look at a failure and how to reproduce it. CDM-Pitfalls; Capacitive Coupled TLP; Cable Discharge; Charged Board Model; ESD from Outside - straight through passivation ESD on LEDs. pLab Experience 1:00 p.m. - 5:00 p.m. Learn to know your structures in the ATIS test lab and discuss the results with the speakers and your colleagues. Learn to know characterization equipment and methods. Pls. contact [email protected] to discuss your individual test wishes at least before October 1, 2013 and send some devices to be tested during a demonstration at the workshop. The speakers reserve the right to prioritize projects in view of interest to the audience. 3/12/2014 Setting the Global Standards for Static Control! EOS/ESD Association Inc. • 7900 Turin Rd Bld 3 • Rome NY 13440 Phone 315-339-6937 • Fax 315-339-6793 • [email protected] • www.esda.org ESD Association Regional Tutorials October 7-8, 2014 ESD Device Design Essentials October 9, 2014 Advanced ESD Characterization and Test Methods Fraunhofer Institution for Modular Solid State Technologies EMFT Hansastr. 27d, 80686 Munich, Germany • Lunch and refreshments provided. Register Online at www.esda.org/onlineregistrations.html About the instructors Gianluca Boselli completed his Master in EE at the University of Parma, Italy, in 1996. In 2001 he completed his Ph.D. at the University of Twente, The Netherlands. In 2001 he joined Texas Instruments, Dallas, Texas, where he focused on ESD and Latch-up development for advanced CMOS technologies. Recently his responsibilities extended into ESD development of Analog technologies. He authored several papers in the area of ESD and Latch-up. He presented his work at major conferences, including EOS/ESD Symposium, IEDM, and IRPS. He also presented several invited papers and/or tutorials at the EOS/ESD Symposium, IRPS, IEDM, ESREF and RCJ. Dr. Boselli has been the recipient of the “Best Paper Award” on behalf of Microelectronics Reliability Journal in 2000. He received “The Best Paper Award” at the EOS/ESD Symposium 2002. He also received the “The Best Presentation Award” at the EOS/ESD Symposium in 2002 and in 2006. Dr. Boselli is a member of ESD Association and an IEEE senior member. He is currently a member of the Board of Directors of the ESD Association, where he is the Symposium Business Unit Manager. Dr. Boselli serves on the TPC of the EOS/ESD Symposium, IRPS and ESREF. Dr. Boselli has served as TPC Chair at the EOS/ESD Symposium 2006, Vice-General Chair at the EOS/ ESD Symposium 2007 and General Chair at the EOS/ESD Symposium 2008. Dr. Boselli holds fourteen patents with several pending. Dr. Boselli serves in the Editorial Board of the IEEE Transactions on Device and Materials Reliability (T-DMR). Harald Gossner is Intel Architecture Group Principal Engineer for ESD. He received his degree in physics (Dipl. Phys.) from the LudwigMaximilians-University, Munich in 1990 and his Ph. D. in electrical engineering from the Universität der Bundeswehr, Munich in 1995. For 15 years he has worked on the development of ESD protection concepts for bipolar, BiCMOS and CMOS technologies with Siemens and Infineon Technologies. Recently, he has joined Intel Mobile Communications overseeing the development of robust mobile systems there. Harald Gossner has authored and coauthored more than 100 technical papers and one book in the field of ESD and device physics. He holds 30 patents on the same topic. He received the best paper award of EOSESD 2005. He has served in several conference committees of IEDM, IEW and EOSESD Symposium, where he is currently technical program chair. He is member of the board of directors of ESD Association. In 2006 he became cofounder of the Industry Council on ESD Target Levels. Since then he is co-chairing this committee of 50 leading electronics and IC companies. Horst A. Gieser is head of the ATIS (Analysis and Test of Integrated Systems) team at the Fraunhofer-Institution for Modular Solid State Technologies EMFT (the former Munich branch of Fraunhofer-Institute for Reliability and Microintegration until June 30, 2010). He received his diploma in Electrical Engineering and his Ph.D. from the Technical University in Munich. He has authored and contributed to more than 55 publications. Four papers in the field of electrostatic discharge (ESD) won awards at international conferences. Currently, he is chairing the ESD FORUM e.V. www.esdforum.de, the German non-profit ESD association furthering the exchange of scientific and professional experience. He has been serving in organizing several international conferences and workshops. Further interests are in the field of reliability and failure analysis of devices, circuits, and systems as well as characterization techniques with ultra-short transients. For lateral and vertical integration of modules and systems his team has been working on Aerosol Jet Printing, through silicon vias, and polymer electronics. Heinrich Wolf received his diploma degree in Electrical Engineering from the Technical University of Munich (TUM) and his PhD from the Technical University of Berlin, Germany. He joined the Chair of Integrated Circuits at the TUM as a member of the scientific staff working on Electrostatic Discharge (ESD) related issues. This involved modeling of ESD-protection elements, parameter extraction techniques and test chip design. In 1999 he joined Munich branch of the Fraunhofer Institute for Reliability and Microintegration (IZM) which became the Institution for Solid State Technologies EMFT in 2010. He was involved in the investigation of ESD phenomena for CMOS and Smart Power Technologies. Furthermore he published on the development of ESD test methods and tester characterization. Currently he is coordinating the ESD related activities at the EMFT and is also working in the field of RF transmission line design which includes simulation and characterization up to 110 GHz. Furthermore, he serves for the TPC of the EOS/ESD Symposium and the IEW. 3/12/2014 Setting the Global Standards for Static Control! EOS/ESD Association Inc. • 7900 Turin Rd Bld 3 • Rome NY 13440 Phone 315-339-6937 • Fax 315-339-6793 • [email protected] • www.esda.org ESD Association Regional Tutorials October 7-8, 2014 - ESD Device Design Essentials October 9, 2014 - Advanced ESD Characterization and Test Methods Fraunhofer Institution for Modular Solid State Technologies EMFT Hansastr. 27d, 80686 Munich, Germany • Lunch and refreshments provided. Register Online at www.esda.org/onlineregistrations.html First Name: Last Name: Company Name: Street: City: State/Province: Country Address is (please circle the one that applies) Zip/Postal Code: Home or Company Fax: Phone: E-mail: Before Aug 27 After Aug 27 Oct. 7-8Oct. 9Oct. 7-8Oct. 9 Member Registration Fees 1,510 USD 510 USD 1,710 USD 710 USD Non-member Registration Fees 1,610 USD 610 USD 1,710 USD 710 USD Cancellation & refund requests will be honored only if received in writing no later than Reg is Aug 27, 2014, and are subject to a $50 fee. Any other approved dispositions will also onli ter n be assessed a $50 fee. e www .esd at a.or g Payment Information Payment is required at time of registration. Only checks drawn in U.S. currency on a U.S. bank that is a member of the Federal Reserve will be accepted; make checks payable to ESD Association. Visa®, Mastercard®, and American Express® and Discover® are accepted. Amount enclosed $ Credit card type: Check Visa® Mastercard® Credit card number: Name on card: Credit Card American Express® Discover® Expiration date: Security code: Cardholder’s signature: Accomodations: Be sure to make your reservations early to guarentee room availability. Sheraton Munich Westpark Hotel Garmischer Str.2 80339 München Phone: +49 (0)89- 51 96-0 Fax. +49 (0)89- 51 96-30 00 E-Mail: [email protected] www.arabellasheraton.com/westpark Ars Vivendi Hotel Anglerstr. 19 80339 München Phone: +49 (0)89- 50 80 70-0 Fax : +49 (0)89- 50 80 70-70 E-Mail: [email protected] www.hotel-ars-vivendi.de Hotel ibis München City West Westendstrasse 181 80686 München Phone: +49 (0)89- 579497-0 Fax: +49 (0)89- 579497-499 E-Mail: [email protected] www.ibishotel.com Setting the Global Standards for Static Control! EOS/ESD Association Inc. • 7900 Turin Rd Bld 3 • Rome NY 13440 Phone 315-339-6937 • Fax 315-339-6793 • [email protected] • www.esda.org