How to Test Complex VLSI/SoC 2010 Sungho Kang Outline What is Testing? Faults, ATPG & Fault Simulation Ad-Hoc Scan Logic BIST & Memory BIST P1149.1 & P1500 Conclusion 2 VLSI Implementation Customer’s need Determine requirements Write specifications Design synthesis and Verification Test development Fabrication Manufacturing test Chips to customer 3 Design Constraints Area Speed Power Testability 4 Testing Defect z Physical deviation from some specified properties Test z An experiment whose purpose is to detect the presence of detects and to diagnose the source of defects Byproduct of testing z Reliability measurement of the product and process z Quality assurance z Assistance to verification and validation 5 Testing Process Rule of thumb: spend 5-10% die area on DFT (10% of die is state and scan is 50% overhead per state!) 6 Verification vs Testing Verification z z z z Correctness of design Simulation, Emulation and Formal verification Performed once before manufacturing Responsible for quality of design Testing z z z z Correctness of manufactured hardware Test generation and test application Performed every manufactured devices Responsible for quality of devices 7 Testing Costs To detect problems early (Rule of Ten) z z z z z Test Chip Test Board Test System Test Field Test Failure Component Failure Board Failure System Failure Field Failure Cost $0.3 $3 $30 $300 8 Test Cost vs Manufacturing Cost 9 VLSI Chip Yield A manufacturing defect is a finite chip area with electrically malfunctioning circuitry caused by errors in the fabrication process A chip with no manufacturing defect is called a good chip Fraction (or percentage) of good chips produced in a manufacturing process is called the yield Good chips Faulty chips Defects Wafer Unclustered defects Wafer yield = 12/22 = 0.55 Clustered defects (VLSI) Wafer yield = 17/22 = 0.77 10 Bathtub Curve Failure Rate Infant Mortality Working Life Wearout Wearout Failures Early Failures Random failure Time 11 Test Process Bad parts which fail Test (BF) Parts for Manufacturing Line Test Process Defect Level = BP Good parts which pass Test (GP) Bad parts which pass Test (BP) GP + BP 12 Quality of Test Quality of Test z z z z Y : Yield DL: Defect Level d : defect coverage DL = 1 - Y 1-d defect level (%) 1.0 Y = 0.01 0.8 Y = 0.1 Y = 0.25 0.6 Y = 0.5 0.4 Y = 0.75 0.2 Y = 0.9 Y = 0.99 0.0 0 20 40 60 fault coverage (%) z Consider a 0.5 yield process To achieve 0.01 defect level, 99% coverage is required To achieve 80% coverage, 0.2 defect level 80 100 13 Design for Testability Refers to those design techniques that make test generation and test application cost-effective Why need? z Difficulty in preparing test patterns Advantages z Test generation is easy z High quality testing Disadvantages z Area overhead z Timing overhead 14 How Much Testing Is Enough? Test Development Time as a Percentage of Total Design Time 40 30 20 10 0 0 20 40 60 80 100 Testability of a Circuit (%) 15 Test Costs vs Manufacturing Costs costs Total costs Processing costs Packaging costs Testing costs No special test provision Additional silicon area Overhead for test purposes 16 Current Situation Increase of complexity z Moore’s Law No. of transistors doubles every 18 months Increase of speed z 30% increase per year Timing and signal integrity Increase of test cost z 30-40% of overall cost Increase of ATE performance z 12% increase per year Time to Market z Exhaustive testing is no good 8080 takes 1020 years at one million tests per second 17 Test Cost Factors Test Test Low Cost Equipment Equipment Spec. Design Methodology SoC Test Controller BIST Mem BIST Test Access Low cost external ATE User Defined Core ROM User Defined Core RF/Analog Core UDL Design for Appropriate DFT Testability IP DRAM IP IP IO Pad IO Pad TestTest Efficient Engineering Engineering TestTest Sound Methodology Methodology Powerful Test CAD Tools Test CAD Tools 18 Manufacturing Defects In fabrication, defects get introduced from many sources: z z z z z z Contamination Metalization Defect Implant Defect Wafer Defect Oxide Defect Interconnect Defect 19 Logical Fault Models Gate Level Faults z Stuck-at Short between signal and ground or power z Bridging Short between two signals Transistor Level Faults z Short Connecting points not intended to be connected z Open(break) Breaking a connection z Stuck-on (stuck-short) z Stuck-open (stuck-off) Delay Faults Temporary Faults 20 Single Stuck-at Fault (SSF) Only one line in the circuit is faulty at a time The fault is permanent (as opposed to transient) The effect of the fault is as if the faulty node is tied to either Vcc (s-a-1), or Gnd (s-a-0) The function of the gates in the circuit is unaffected by the fault Fault: A s-a-1 A 0 0 1 1 B 0 1 0 1 Vcc C 0 0 0 1 Fault-Free Gate A B A C 0 0 1 1 B 0 1 0 1 C 0 1 0 1 Faulty Gate 21 Relative Performance of Fault Models HP(1996) : 25K std. cell design, 0.8micron z z z z Full scan : 1497FFs, 33MHz Functional pattern : 83.7% fault coverage Stuck-at fault coverage : 99% with 284 patterns Transition fault coverage : 99.4% with 554 patterns slow functional 0 0 0 0 0 at-speed functional 5 190 4 stuck-at scan 8 22 6 2 24 at-speed scan 22 Fault Coverage and Efficiency Fault coverage = Fault efficiency # of detected faults Total # faults # of detected faults = Total # faults -- # undetectable faults 23 Fault Simulation Test Patterns Fault Simulator Fault Coverage Circuit Fault List 24 ATPG Circuit ATPG Fault Model Tests Fault List 25 ATPG Example G output s-a-1 A F B C D G H E A 1 1 1 G H E 0 F J 0/1 K I X J 0/1 0 K 0 I Fault Excitation 1 1 1 G H 0 0 F 0 J 0/1 K 0 I 0/1 1 Fault Propagation 26 Sequential ATPG 27 DFT Flow Verilog/VHDL Netlist DFT Rule Checking DFT Rule Checking Test Synthesis Scan Design, Boundary Scan Design Memory BIST Design, Logic BIST Design DFT Rule Checking Static Timing Analysis DFT Rule Checking ATPG Test Pattern Generation Full Timing Simulation Logic Simulation Test Vector Translation 28 Classification of DFT Ad-Hoc Design z Initialization z Adding extra test points z Circuit partitioning Structured Design z Scan design z Boundary Scan z Built-in Self Test 29 Partitioning Physically divide the system into multiple chips or boards On board-level systems, use jumper wires to divide subunits Can have performance penalties Module 2 System Module 1 Module 3 30 Test Point Insertion Employ test points to enhance controllability and observability Large demand on extra I/O pins Example 31 Sequential Circuit PI PO Combinational FF logic FF FF 32 Adding Scan Structure PI PO Combinational logic FF SCANOUT FF FF Test/Normal SCANIN A MUX is added 33 Automated Scan Design Behavior, RTL, and logic Design and verification Rule violations Scan design rule audits Gate-level netlist Combinational ATPG Scan hardware insertion Scan netlist Combinational vectors Scan sequence and test program generation Test program Scan chain order Design and test data for manufacturing Chip layout: Scanchain optimization, timing verification Mask data 34 Sources of DFT Rule Violation Reset/preset violations z Controllability through PIs or disabled during test Clock rule violations z Controllability/gating Tristate bus violations z Ensures there is no contention Bidirectional I/O violations z Controls direction to avoid contentions Latch violations z Ensures transparency during test mode Shift constraint violations z Ensures proper shifting of data through the scan chain 35 Scan Chain Reordering To reduce the routing congestions To reduce the hold-buffer insertion during placement z May need skew-based optimization Before After 36 Built In Self Test Capability of a product to carry out an explicit test of itself z Test patterns are generated on-chip z Responses to the test patterns are also evaluated on chip z External operations are required only to initialized the built-in tests and to check the test results (go/no-go) Pattern Generator Logic BIST Controller CUT Response Analyzer 37 Linear Feedback Shift Register The state of shift register depends only on the prior state cc1 1 D Q D Q Q1 Next State Current State cn D Q Q2 a-1 am am-1 =1 am-1 D Q Q3 Qn a-n+1 a-n am-2 am-n+1 am-n cn-1 c2 D Q Q1 cn = 1 a-2 cc1 1 D Q Current State cn-1 c2 D Q Q2 am-2 D Q Q3 Qn am-n 38 LFSR Example Characteristic Polynomial : 1+x2+x3 z z z z Initial condition (1,0,0) : x Q1 : x / (1+x2+x3) Q2 : x2 / (1+x2+x3) Q3 : x3 / (1+x2+x3) 39 LFSR Example When initial state is 100 z z z z z z z z z z z Q1 Q2 Q3 1 0 0 0 1 0 1 0 1 1 1 0 1 1 1 0 1 1 0 0 1 1 0 0 0 1 0 1 0 1 When initial state is 000 z Q1 Q2 Q3 z 0 0 0 z 0 0 0 40 MISR Multiple input signature analysis + D Q + Q1 Cn D3 D2 D1 Cn-1 D Q + Q2 D Q Q3 ... Cn-2 Dn + D Q Qn C1 ... 41 Test-per-Clock Test patterns are applied to CUT every clock cycle Additional logic and delay are required between the input FF and CUT BILBO like type: Cannot perform compression and pattern generation concurrently Entire test is scheduled and divided into sessions Complex test control unit is required PRPG CUT MISR 42 STUMPS Self Testing Using MISR and Parallel SRSG z Centralized and separate BIST z Multiple scan paths Reduction in test time Lower overhead than BILBO but takes longer to apply PRPG Scan chain Scan chain Scan chain Scan chain Logic BIST controller MISR 43 Complete Fault Coverage Hybrid test pattern generation z Combination of pseudo-random test and deterministic test Deterministic test pattern generation z Store-and-generate scheme z Test set embedding scheme Bit-flipping or Bit-fixing LFSR reseeding or multiple-polynomial reseeding Hybrid BIST trade-off ( Short test time Heavy H/W overhead Time random deterministic) Long test time Light H/W overhead Time Optimal test time Optimal H/W overhead Time 44 Multiple Seed / Reseeding Seed ROM v v v Seed0 Seed1 Seed2 LFSR CUT Test clock BIST Controller MISR v 45 Bit Fixing/Bit Flipping Method Scan chain t0 t1 … ... tL-1 … ... Bit Flipping Circuit s0 s1 … ... sn-1 Signature Analyzer Sequential CUT 46 Why Need Test Compression ? Today’s SoC environments z Large and complex VLSI circuits z Need an enormous amount of test data Limitations of ATE based test methods z Channel width and memory size z Modified or more expensive ATE must be required Reducing test data by eliminating useful test patterns z Can be reduced for the size of the ATE memory z Deceases the accuracy of testing Test Compression Compress the test input sequences Need a decompression units to make original test sequences Can be reduced for both limitations of ATE z The size of ATE memory z The width of ATE channel Can be reduced test application time Embedded Memory Testing Source: ITRS 2001 – Percentage of Logic Forecast in SoC Design Year Node (nm) % Area New Lo gic % Area Reused Logi c % Area Memory 1999 180 64 16 20 2002 130 32 16 52 2005 100 16 13 71 2008 70 8 9 90 2014 35 2 4 94 49 Memory Functional Model 50 MBIST Basic Architecture Fault Model z Stuck-at Fault z Address Decoding Fault z Coupling Fault z Pattern-Sensitive Fault Memory Test Algorithms z March Test z Checkerboard z Zero-One Normal Inputs Embedded RAM MUX Module BIST MODE Test Test Inputs Outputs Normal Outputs BIST Pattern Generation & Response Comparison 51 Concept of Boundary Scan Improve testability by reducing the requirements placed on the physical test equipment Also called • JTAG (Joint Test Action Group) Boundary Scan Standards • IEEE P1149.1 Why use it? • Testing interconnections among chips • Testing each chip • Snapshot observation of normal system data Why testing boards? • To test board is easier than to test systems 52 IEEE 1149.1 Device Architecture I/O Pad Boundaryscan cell Boundaryscan path BS Test bus circuitry TDI IDCODE Register TMS TRST T A P TCK TDO Instruction register Glue Logic Bypass register M U X S out 53 The Principle of BS Architecture 54 SOC Design Evolution Emergence of very large transistor counts on a single chip Mixed technologies on the same chip Creation of Intellectual Property (IP) Reusable IP-based design Boundary Scan TAP Controller Logic BIST Memory BIST`Test Access DSP Core IP Core CPU Core UDL DRAM IO Pad IO Pad ROM IP Core Data Path IP Core 55 IEEE P1500 56 System Chip with P1500 Wrapped Cores TAM-Source TAM-Sink User Defined Test Access Mechanism TAM-In TAM-In TAM-Out Standard P1500 Standard P1500 Chip Inputs Chip Outputs Core N Core 1 Core Test Wrapper WSI1 TAM-Out WSO1 WSIN Core Test Wrapper Wrapper control WSON P1500 WIP TAM Source/Sink System Chip z From chip I/O, test bus/rail/port, BIST, etc.. TAM In/Out z 0 to n lines for parallel and/or serial test data, or test control P1500 Wrapper Interface Port(WIP) z From chip-level TAP controller, chip I/0, … 57 Test Access No Direct Physical Access Method z Test access mechanism is required Today’s chip is tomorrow’s core 2nd Generation Core 1st Generation Core Test Control I/F Test Access 3rd Generation Core Test Control I/F Test Control Interface 58 Core Level Testing Summary • • • • Testable core design Logic BIST Test reuse Hierarchical testing • Core access architecture • Parallel access & bypass • Core isolation SoC Test Controller BIST Mem BISTTest Access ROM User Defined Core UDL RF/Analog Core • Analog Fault modeling • Mixed signal Built-In Self Test • Built-In Self Calibration DRAM IO Pad IO Pad • Test spec. • Test hardware control • Test scheduling IP User Defined Core • IP-system test interface Test Automation • Automatic test pattern • Fault simulation • Testability measure • Scan insertion & synthesis • BIST circuit synthesis • Boundary scan insertion & synthesis IP IP • Testable design Low cost external ATE • Memory test algorithm • Memory BIST, BISR 59 Test Challenges Test quality Test cost reduction At-speed test Reduction of design efforts Test design reuse 60