Download Report

What is SOI?
With Silicon-On-Insulator (SOI) wafers, transistors are formed in thin layers of silicon that are isolated from the main
body of the wafer by a layer of electrical insulator, usually silicon dioxide. The silicon layer thickness ranges from
several microns for electrical power switching devices to less than 500 Å for high-performance microprocessors.
Isolating the active transistor from the rest of the silicon substrate reduces the electrical current leakage that would
otherwise degrade the performance of the transistor. Since the area of electrically active silicon is limited to the
immediate region around the transistor, switching speeds are increased and sensitivity to "soft errors", a major
concern for large-scale data storage and high-volume servers, is greatly reduced.
SOI Fundamentals
Silicon-On-Insulator (SOI) is a new way of starting the chipmaking process, by replacing the bulk silicon wafers
(approximately 0.75 mm thick) with wafers which have three layers; a thin surface layer of silicon (from a few
hundred Angstrom to several microns thick) where the transistors are formed, an underlying layer of insulating
material and a support or "handle" silicon wafer. The insulating layer, usually made of silicon dioxide and referred to
as the "buried oxide" or "BOX", is usually a few thousand Angstroms thick. When transistors are built within the thin
top silicon layer, they switch signals faster, run a lower voltages and much less vulnerable to signal noise from
background cosmic ray particles. Since on an SOI wafer each transistor is isolated from its neighbor by a complete
layer of silicon dioxide, they a immune to "latch-up" problems and can spaced closer together than transistors built on
bulk silicon wafers. Building circuits on SOI allows for more compact chip designs, resulting in smaller IC devices
(with higher production yield) and more chips per wafer (increasing fab productivity).
Why is SOI important?
SOI enables increased chip functionality without the cost of major process equipment changes (such as higher
resolution lithography tools). The advantages of IC devices built on SOI wafers (mainly faster circuit operation and
lower operating voltages) have produced a powerful surge in the performance of high-speed network servers and
new designs for hand-held computing and communication devices with longer battery life. Advanced circuits, using
multiple layers if SOI-type device silicon, can led the way to a coupling of electrical and optical signal processing into
a single chip resulting in a dramatic broadening of communication bandwidth with new applications such as globalranging, direct-link entertainment and communication to hand-held devices.
Some types of SOI devices, using radiation-resistant buried insulators, will increase the reliability and functionality of
communication satellites and other orbiting and deep-space systems. SOI devices also extend the operating range of
silicon devices to high temperature environments such as built in diagnostics and controls for automotive and other
combustion engines.
Technology Issues
Silicon-on-Insulator (SOI) wafers consist of three layers: a thin (200 A to several microns, depending on the
application) layer of single-crystal silicon on a thick (1000 to 4000 A) silicon dioxide layer that is bonded to a
conventional "handle" wafer. The entire transistor is located in the thin top layer of silicon and electrically isolated
from the bulk wafer by the buried oxide (BOX) layer.
Figure 1 (above). Sketch of metal-oxide-semiconductor (MOS) transistors on a bulk silicon wafer (left) and siliconon-insulator (SOI) wafer (right).
The essential operation of an MOS transistor is the controlled flow of electrical current from a source junction to a
drain junction (as indicated by the arrow) when the voltage on the gate is switched beyond the threshold or "turn-on"
voltage. For an MOS transistor formed on a bulk silicon wafer, the region around the source and drain junctions need
to be depleted of local charge during signal switching. This slows the switching process down. In an MOS transistor
formed on an SOI wafer, the entire transistor is in a thin (usually less than 0.2 um thick) silicon layer insulated from
the bulk of the silicon "handle" wafer by a thick (usually 0.1 to 0.4 um) oxide. The smaller volume of silicon that is
depleted during switching of an SOI transistor increases the speed of signal processing and allows operation at lower
drive voltages.
The core circuit of CMOS ICs is an inverter, consisting of a linked pair of complementary transistors. On a bulk silicon
wafer, the transistors are formed in a pair of doped "wells". On an SOI wafer, the transistors are formed in a thin
silicon layer insulated by a thick buried oxide (or "BOX"). Because of the increased efficiency of the SOI device
isolation the surface area of the circuit can reduced, allowing for smaller die size and increased device count per
wafer.
Figure 2 (above): CMOS inverter transistors on bulk silicon and SOI wafers sketched with the same gate size
(critical dimensions). The smaller size of the SOI inverter is due to the more efficient isolation of SOI transistors.
The principal advantages of electrical devices fabricated in SOI wafers are:
1.
2.
3.
4.
a 20% to 50% increase in switching speed compared to similar circuits built on conventional "bulk" silicon
wafers
the ability to operate at lower voltages (less battery power drain and chip heating)
events from cosmic ray particle showers (reducing the need for error correction operations in high-speed
data flow servers and memory arrays)
increased circuit packing due to simplification of the lateral and vertical isolation structures, increasing chip
yield and die count per wafer
Even though the widespread use of SOI materials is relatively recent, the range of applications and types of SOI
wafers is extensive. The thickness of the top Si layer ranges from several microns for MEMS (Micro MechanicalElectrical Systems) and sensors to a few hundred Angstroms for fully-depleted CMOS transistors. BOX thickness
range from 500 Angstroms to several microns. The thickness of the SOI layers are determined by voltage isolation
and device scale requirements.
Figure 3 (above): SOI layer thickness for various applications.
Types of SOI-CMOS transistors are characterized by the thickness of the Si-SOI layer. For partially-depleted SOICMOS, the device Si layer is thicker than the depletion layer under the channel, in the range of 100 to 200 nm. As
CMOS gates are scaled to 5-65 nm and smaller, CMOS devices will be formed in thin Si layers which are fullydepleted in the channel region between the source and drain junctions. For fully-depleted CMOS, the Si device layer
is of the order of 50 nm and shrinking towards 10 nm, or the "nano-SOI" regime. Fully-depleted CMOS devices will
take advantage of the ability of advanced SOI fabrication processes (such as NanoCleave) to provide wafers capable
of forming dual-gate transistors, with control gates both above and below the thin channel.
Figure 4 (above): SOI-CMOS transistor types.
On a more fundamental level, SOI wafers provide the most viable path for extension of CMOS-VLSI transistor circuits
beyond the "end of the roadmap" barriers detailed in the ITRS99 (International Technology Roadmap for
Semiconductors-1999) for planar CMOS on bulk silicon wafers. The large number of basic problems with continuing
scaling of conventional CMOS on bulk wafers are expected to become limiting factors for gate sizes less than 65 nm,
anticipated to be the scale of leading product by 2006. By using thin (less than 500 A) silicon SOI layers, research
CMOS transistors have already been fabricated with excellent performance with 25 nm gates. According to the ITRS
schedule, CMOS gates of 25 nm are expected to be characteristic of advanced technology circuits by 2014.
Figure 5 (above): The International Technology Roadmap for Semiconductors (ITRS99) projects a steady decrease
in gate size and CMOS junction depths with time. The limitations of planar CMOS transistors are projected to reach
crisis proportions at and below a gate size of 65 nm in 2006-2008. After this time (and transistor scale), most
advanced transistors are expected to use fully-depleted, dual-gate architectures on SOI wafers.
The principal technology advances needed for the migration of CMOS devices to SOI wafers are:
1.
2.
fabrication techniques for high quality SOI wafers; and
modification of transistor designs to take account of the special characteristics of SOI layers.
The requirements for circuit modification for SOI are minimized by using a "partially depleted" SOI transistor on
relatively thick (1000 to 2000 A) device silicon, such as the production conditions used by IBM. Many circuit
development groups are working on "fully depleted" CMOS, where the full circuit advantages of SOI are realized,
with production introductions scheduled in 2001 through 2005. After the "end of roadmap" scaling to sub-65 nm gates,
the majority of advanced technology CMOS transistors will be fully depleted SOI. The successful fabrication of high
quality SOI wafers depends on development of second-generation technologies, such as SiGen's NanoCleave
process. Full adoption of SOI technologies will follow with the expansion of SOI wafer fabrication capacity and the
resulting reductions in wafer cost and increased range of available SOI wafer types.