CMR INSTITUTE OF TECHNOLOGY Internal Assessment Test 3 – May 2014 Sub: Microprocessors USN: In this case I/O devices are treated as memory device Date: 16/05/14 Duration: Code: 10CS45 Branch: ISE/CSE I/O devices are treated as I/O devices. 90 mins Max Marks: 50 Scheme and Solution Sem: IV 1. a. What is the need of memory banking? Explain the memory banking in 8086 with a neat block diagram. Need of Banking -2marks Banking memory diagram explanation-3 marks -the wider bus presents a unique set of problems, processors must be able to write data to any ,16-bit location—or any 8-bit location This means the 16-bit data bus must be divided into two separate sections (or banks) 8 bits wide so that the processor can write to either half (8-bit) or both halves (16-bit) BHE A0 0 0 – read 16 bit data from both banks 0 1 -read 8 bit data from lower bank 1 0 -read 8 bit data from higher bank 1 1 inactive state 1b. Differentiate between memory mapped I/O and direct I/O. Any five differences 5X1= 5marks 2. Memory and I/o has 16 bit addresses Memory and I/o Devices have 8 bit addresses Possible addresses i.e. memory space is 64 K bytes and range is 0000H to FFFFH Possible address i.e. memory space is 256 bytes and range is 00H to FFH Some of the available addresses are assigned to the memory devices and the remaining are assigned to the I/O devices. In this case addresses assigned to the memory devices can be assigned to the I/O devices. No special instructions are required. Instructions used for the data transfer between a memory and accumulator are same that are used for data transfer between an I/O device and accumulator. E.g. instruction Mov A, M is applicable in both the cases. Other instructions used are LDA, STA, ADD M etc. For the transfer of Data Between microprocessor and I/O device. It requires special instructions such as IN and OUT. More hardware is required to decode 16 bit address. Less Hardware is required to decode 16 bit addresses. Less memory space is available because of the partition of memory between memory and I/O devices. It is not so in this case. Complete address space is available Speed is low because length of instructions LDA, MOV A , M etc is high. Speed is high, because length of IN and OUT instructions is less. Data Transfer can take place between any register and I/O device. In this case data transfer takes place between accumulator and I/O only Arithemetic and logical operations can be directly performed with I/O devices. Arithmetic operations cannot be performed directly data in is first brought into accumulator and then arithmetic operations are performed only in accumulator. With internal block diagram, explain 8254 PIT. Give any two applications of the 8254. 8254 Block diagram- 3marks Explanation – 5 marks Applications -2 marks Applications Generating delays Generating a Waveform with the 8254 Reading a Counter DC Motor Speed and Direction Control 3. Write a C/C++ program to declare a structure containing name, usn and age. Read the structure member using _asm block and display the members using _asm block. struct stud { Char name[20],usn[10]; Int age; } s1; void main() { Printf(“ Enter the name “); Readstr(s1.name); Printf(“enter the usn”); Readstr(s1.usn); Printf(“enter the age” ); Readnumb(&s1.asge); Printf( “ Name is :”); Displaystr(s1.name); Printf( “ usn is :”); Displaystr(s1.usn); Printf(“age is:”); Display numb(s1.age) Getch(); } Void readstr(char *s) { _asm { Lea si,s L2: Mov ah,01 Int 21h Cmp al.0dh Jz l1 Mov [si],al Inc si Jmp l2 L1: } } Void readnumb(int *a) { _asm { Mov ah,01 Int 21h Mov cl,al Int 21h Mov ah,cl Sub ax,3030h Aad Mov a,al } } Void display str( char *s) { Int len= strlen(s); _asm { Mov cx,len Lea si,s L3: mov ah,02 Mov dl,[si] Inc si Loop l3 } } Void displaynumb(int i) { _aam { Mov al,i Aam Mov bx,ax Add bx,3030h Mov dl,bh Mov ah,02 Int 21h Mov dl,bl Int 21h } } 4. Explain address decoding using simple NAND Gate decoder and 3-to-8 line decoder. NAND Gate and example -5 marks 3-to-8 Decoder and example – 5marks Simple NAND Gate Decoder • When the 2K × 8 EPROM is used, address connections A10–A0 of 8088 are connected to address inputs A10–A0 of the EPROM. – the remaining nine address pins (A19–A11) are connected to a NAND gate decoder • The decoder selects the EPROM from one of the 2K-byte sections of the 1M-byte memory system in the 8088 microprocessor. • In this circuit a NAND gate decodes the memory address, as seen in Figure 10-13. The 3-to-8 Line Decoder (74LS138) 5. Interface 512 KB RAM and 512KB ROM to 8088 microprocessor using 64 KB RAM and 64KB ROM with 3:8 decoders. Address of memory starts at 80000H for RAM and 00000H for ROM. Clearly mention decoding logic and memory map. Memory Design-4 Marks Memory Map- 4 Marks Explanation -2 marks A19A18A17A16 A15A14A13A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Memory Chip ADDRESS 0000 0111 0000 1111 0000 1111 0000 1111 0000 1111 ROM(1-8) 00000H 7FFFFH 1000 1111 0000 1111 0000 1111 0000 1111 0000 1111 RAM(1-8) 80000H FFFFFH D7-D0 RD A16 A17 A18 A19 A15-A0 3-8 decoder G1 G2A G2B IO/M 9 A15-A0 A15-A0 A15-A0 A15-A0 A15-A0 ROM 64KB A15-A0 A15-A0 A15-A0 OE OE OE CS OE CS OE CS OE CS OE CS OE CS CS CS WR A16 A17 A18 3-8 decoder G1 G2A G2B A15-A0 A15-A0 A15-A0 A15-A0 RAM 64KB A15-A0 A15-A0 WE A15-A0 WE A15-A0 OE WE OE WE OE CS WE OE CS WE OE CS WE OE CS WE OE CS OE CS CS CS 6. Explain the pin diagram of 82C55 along with different operational modes. 8255 Pin diagram- 3marks Explanation -3 marks I/O Mode control word- 2marks BSR mode2 marks 7. Interface 8-digit seven segments / 8088 microprocessor through 82C55 and explain the logic to program LED Display Design diagram -4 marks LED display to Logic -3 marks Program- 3 marks