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Chapter 2
Basic MOS Device Physics
Department of Microelectronics,
School of Electronics & Information Eng.
Xi’an Jiaotong Univ.
Hong Zhang （张 鸿）
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 1
Outline
•
•
•
•
General consideration
MOS I/V characteristics
MOS small signal model
Second-order effects
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 2
Outline
• General consideration
– MOS physical structure
– MOS symbols
• MOS I/V characteristics
• MOS small signal model
• Second-order effects
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 3
MOSFET Structure
A NMOS transistor on a p-type substrate ( or p “body”)
W
design parameters:
Ldrawn : length
W:
width
Process parameters:
tox : thickness of oxide
Nsub: doping concentration of sub
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 4
Substrate potential
• Sub potential influences MOS characteristics
• MOS is essentially a 4-terminal device
– G: gate
– S: Source
– D: drain
– B: body
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 5
Obtain NMOS and PMOS on a p-sub
• Use N-well to fabricate PMOS
• We call this double-well CMOS process
– Question: if we have 2 NMOS on this wafer, can we
connect the B terminals of them to different
potentials? Why?
– The same question for PMOS.
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 6
MOS symbols
Sub potentials must be
considered for analog IC
4-termial symbols are often
adopted
Design of Analog CMOS Integrated Circuits
In digital IC:
NMOS BGND
PMOS BVDD
Adopt 3-terminal symbols
--Ch.2 Basic MOS Device Physics # 7
MOS as a switch
• MOS transistor can be thought as a switch
– Digital IC
– Control transistors in analog IC
– Question: how to turn on (or off) the MOS ?
• Need to know the threshold voltage (Vth)
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 8
MOS as a VCCS
• MOS is also a voltage controlled current source
(VCCS)
– In analog circuit
– Question: how dose the gate voltage control the
drain/source current?
• Need to derive the I/V characteristics
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 9
Outline
• General consideration
• MOS I/V characteristics
– Threshold Voltage
– I/V characteristics derivation
• MOS small signal model
• Second-order effects
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 10
Turn-on process for a NMOS
When VG=0, MOS is off, no current
VG increases a bit，surface is depleted.
Still off, still no current.
Width of depletion region and surface
potential increases with VG, The
structure resembles two caps in series.
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 11
When VG increases to a sufficiently positive value,
the surface is “inverted”, the MOS is turned on.
The value of VG at this point is called VTH
If VG rises further, the charge density in channel
continues to increase (ID increases).
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 12
Threshold Voltage Definition
• VTH: the gate voltage when the surface is inverted
• Inversion definition: electron concentration in the
channel equals to the hole concentration in substrate
VTH   MS  2 F 
Qdep
Cox
MS: Work function difference between the gate and substrate
F ：Fermi potential
Qdep : Charge in the depletion region
Cox：Gate oxide capacitance per unit area
See Chapter 8, “Semiconductor Physics” for detail derivation
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 13
Important note about VTH
VTH   MS  2 F 
 F  ( kT / q ) ln( N sub / ni )
Qdep
Cox
Qdep  4q si |  F | N sub
For NMOS:
the higher the substrate doping, the higher the VTH
For a given process under given temperature, VTH is
almost a constant.
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 14
Outline
• General consideration
• MOS I/V characteristics
– Threshold Voltage
– I/V characteristics derivation
• MOS small signal model
• Second-order effects
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 15
Derivation of I/V Characteristics
VGS>VTH, inverted, but VD=VS, no current flows
VD>VS, current flows from D to S
How to obtain functions between IDS and terminal voltages?
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 16
Derivation of I/V Characteristics
1st observation:
Charge density along the current direction is Qd (C/m)
Charge velocity is v (m/s)
I  Qd  v
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 17
• Second observation
– Assume VGS>VTH, and S and D are all connected to
ground,
– Uniform charge density is obtained
Qd  WC ox (VGS  VTH )
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 18
• Then suppose VD is a little bit larger than VS
• Charge density is no longer distributed uniformly,
but a function of position x
Qd ( x)  WCOX [VGS  V ( x)  VTH ]
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 19
Qd ( x)  WCOX [VGS  V ( x)  VTH ]
I D  Qd  v  WCox [VGS  V ( x)  VTH ]  v
dV ( x)
Given    n E , E ( x)  
dx
dV ( x)
I D  WCox [VGS  V ( x)  VTH ] n
dx
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 20
dV ( x)
I D  WCox [VGS  V ( x)  VTH ] n
dx
• Considering boundary conditions: V(0)=0, V(L) =VDS
• Multiplying both sides with dx, and perform
integration

L
VDS
x 0
I D dx   WCox  n [VGS  V ( x)  VTH ]dV
V 0
W
1 2
I D   n Cox [(VGS  VTH )VDS  VDS ]
L
2
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 21
More simple method
I D  Qd  v
• Use average Qd (at L/2), and average electrical field
I D  WCox [VGS  V ( x) x  L / 2  VTH ]  n E
VDS
1
 WCox (VGS  VDS  VTH )  n
L
2
W
1 2
 nCox [(VGS  VTH )VDS  VDS ]
L
2
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 22
I/V Characteristics in “triode region”
2
VDS
W
I D  nCox [(VGS  VTH )VDS 
], for VDS  (VGS  VTH )
L
2
If VDS≤VGS-VTH , we define:
NMOS operates in “triode region” or “linear region”
In triode region:
ID is influenced both by VGS and VDS
W/L is called “aspect ratio”, a design parameter
nCox is a process parameter
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 23
I/V Characteristics in “triode region”
2
DS
V
W
I D  nCox [(VGS  VTH )VDS 
], for VDS  (VGS  VTH )
L
2
I D,max
1
W
 nCox [(VGS VTH )2 ], whenVDS  VGS VTH
2
L
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 24
Application of NMOS in Triode Region
W
I D  nCox (VGS  VTH )VDS
L
1
if VDS  VGS  VTH
2
VDS
1

Ron 
I D  C W (V  V )
n ox
GS
TH
L
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 25
I/V Characteristics in Saturation Region
Triode region
• What happens if VDS > VGS-VTH ?
• Will it follow the parabolic curve?
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 26
Operation in Saturation Region
Recall that: Qd ( x)  WCOX [VGS  V ( x)  VTH ]
Qd(x) drops to 0, if V(x) approaches VGS –VTH
So, if VDS is slightly greater than VGS –VTH, “pinch
off” happens at x1
Pinch off point moves to left when VDS increases
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 27
Saturation Region (VDS >VGS-VTH)
W
1 2
I D  nCox [(VGS  VTH )VDS  VDS ]
L
2
'
DS
V
 VGS  VTH , (pinch - off)
1
W
2
I D  nCox (VGS  VTH )
2
L
For long channel MOS,
L  L
1
W
2
I D  nCox (VGS  VTH ) for VDS  VGS  VTH
2
L
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 28
Saturation Region
Linear
region
ID 
nCOX W
2
L
(VGS  VTH )
2
ID is controlled by VGS, independent of VDS, “saturated”
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 29
Application of MOS in Saturation
• Saturated MOS can be used as current source
ID 
nCox W
2
L
(VGS  VTH ) 
2
nCox W
2
L
 VOD2
VOD=VGS-VTH, is called “overdrive voltage”
VOD  VGS  VTH 
2I D
nCox (W / L)
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 30
Operation region changes with VG
• For NMOS, if VGS<VTH, it is in off state.
• When VGS increases, it operates from saturation
region to triode region.
VG increases
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 31
NMOS I/V characteristics summary
• Off：VGS - VT≤0
I DS  0
• Triode region：0<VDS≤VGS-VT
I DS
2
DS
V
W
  n Cox [(VGS  VTH )VDS 
]
L
2
• Saturation region：0<VGS-VT<VDS
I DS 
nCox W
2
L
(VGS  VTH )
Design of Analog CMOS Integrated Circuits
2
--Ch.2 Basic MOS Device Physics # 32
Understanding
On and off
Design of Analog CMOS Integrated Circuits
Triode and saturation
--Ch.2 Basic MOS Device Physics # 33
Outline
• General consideration
• MOS I/V characteristics
• MOS small signal model
– Notations
– Understanding the concept of small signal
– Transconductance of MOS
– Ideal small signal model of MOS
• Second-order effects
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 34
Important notations
• DC or bias quantities: Uppercase symbol with
upper case subscript
– DC quantities or bias voltage, currents
– VGS, ID, VDS, VB
• Small signal: Lowercase symbol with lower case
subscript
– Incremental change of currents or voltages
– vgs, id, vds,….
• Transient quantities: Uppercase symbol with lower
case subscript
– Vgs=VGS+vgs
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 35
Explanation of notations
VB
t
Bias
vin
∞
Vin = ？
Vin = VB + vin
Signal
t
∞
VB
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 36
DC or Bias analysis of a simple amplifier
VDD
RD
VB
Assume MOS operates in saturation
region.
VOUT
mnCox W
2
ID =
(VB -VTH )
2 L
VOUT = VDD - I D RD
can we use “VOUT/VB” to denote gain of the amplifier?
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 37
Transient analysis
Vin = VB + vin = VB + va sin(wt )
VDD
vin=va
t
VB
Vin=VB+vin
Vout =
VIN
va
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 38
Quantitive analysis
Vin = VB + vin = VB + va sin(wt )
mnCox W
mnCox W
2
Id =
(Vin -VTH ) =
[(VB -VTH ) + va sin(wt )]2
2 L
2 L
mnCox W
W
= I D + [mnCox (VB -VTH )]⋅ va sin(wt ) +
⋅ [va sin(wt )]2
L
2 L
I d = I D + id
id
nonlinearity
Vout = VDD - I d RD = (VDD - I D RD ) - id RD
= VOUT - vout
vout
W
= id RD = mnCox (VB -VTH )]⋅ RD ⋅ va sin(wt )
L
Amplification factor
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 39
Transient response
VDD
Vin=VB+vin
Vout = VOUT vout
VOUT
VOUT
VB
vout
W
mnCox (VIN -VT )]⋅ RD ⋅ va
L
vin = va sin(wt )
vout
Amplification factor
W
= id RD = mnCox (VB -VTH )]⋅ RD ⋅ va sin(wt )
L
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 40
Small signal model
vin = va sin(wt )
transconductance: gm
vout
W
= -id RD = -[mnCox (VB -VTH )]⋅ vin ⋅ RD
L
• Problem：Can we analyze small signal directly?
• Solution: Small signal equivalent model.
• decomposition of the signal transfer process:
gm
RD
vout=-gmvinRD
id
vin
Convert to current
Back to voltage
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 41
Basic small signal model
vin
gm
Convert to current

id
RD
Back to voltage
vout=-gmvinRD
Key point：How to calculate gm?
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 42
gm：Transconductance
gm
I D

 VGS
V D S  co n stan t
Control capability of VGS on ID
mnCox W
(VGS -VTH ) 2
ID =
2 L
gm
W
  n C ox
(V G S  V T H )
L
W
 2 nCox I D
gm µ I D
L
2I D
=
VGS -VTH
Design of Analog CMOS Integrated Circuits
or
gm µ I D
?
--Ch.2 Basic MOS Device Physics # 43
Three elements for calculating gm
• There are only two independent elements in W/L, ID,
and VGS-VT
• Any one can be derived from another two
gm 
2  n C ox
W
2I D
W
I D  nCox (VGS  VTH ) =
L
VGS -VTH
L
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 44
Outline
•
•
•
•
General consideration
MOS I/V characteristics
MOS small signal model
Second-order effects
– Body effect
– Channel length modulation
– Sub-threshold conduction
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 45
Body Effect (1)
What happens if VB ≠ VS?
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 46
Influence of body effect on MOS
• Consider that VS=0, VB < 0
─More holes are extracted from the surface to the body
electrode
─Negative charge increases, depletion region wider.
VB↓, Qd↑. Therefore, larger VGS is needed to
obtain inversion at surface.  VTH increases .
We call this “body effect” or “backgate effect”.
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 47
Quantitive analysis of body effect on VTH
Qdep  2qN sub si (2 F  VSB )
Qdep 0  2qN sub si 2 F
VTH   MS  2 F 
Qdep
  MS  2 F 
 VTH 0  

Cox
Qdep 0
Cox
From Qdep0 to Qdep,
 VTH ↑

Qdep  Qdep 0
Cox
2 F  VSB  2 F

1

Cox
2q si N sub
─  is called body effect coefficient, and is
provided by foundry.
─ For a 0.5um CMOS process, NMOS  =0.4V1/2；
PMOS =-0.4V1/2
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 48
A example: influence of body effect on MOS circuit
(a) The source-bulk voltage varies with input level;
(b) input and output voltages with no body effect;
(c) input and output voltages with body effect
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 49
Influence of body effect on small-signal model: gmb
gmb：body transconductance
— Control capability of body voltage on drain current
g mb
I D
  VT H
W

  nC OX
(V G S  V T H )(
)
V BS
L
V BS
A lso ,
 VT H
  VT H


  ( 2  F  V SB ) 1 / 2
2
V BS
 V SB
g mb  g m

2 2  F  V SB
  gm
  gmb / gm , typical value is 0.1～0.3
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 50
Small-signal model with body effect
VDD
RD
vout
vin
G
D
vin
B
G
S
vbs
VBS
D
+
vgs
gmvgs
gmbvbs
- S
vbs
+ B
RD
Body transconductance provides another freedom to
control the drain current
In N-well process, body of all NMOS is connected to ground.
However, the body of PMOS can be used as a control terminal
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 51
Channel length modulation effect
• A NMOS operated in
saturation region with large
enough length
– ID is independent of VDS
– MOS is an ideal current
source
– Infinite output resistance
• Short channel MOS
– ID is influenced by VDS
– Finite output resistance
• The influence of VDS on ID is called
Channel length modulation effect
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 52
Quantitive analysis
L'  L  L
L
1
1
1
1
1


 (1 
)
L' L  L L (1  L / L) L
L
assume L / L  VDS , 1 / L' 
ID 
1
(1  VDS )
L
1
W
 nCox (VGS  VTH ) 2 (1  VDS )
2
L
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 53
How to get ?
VA  VDS 1
I D1

VDS 2  VDS 1 I D 2  I D1
I D 2  I D1
1


VA I D1VDS 2  I D 2VDS 1
ID1
ID2
Early voltage
-VA =
1 L
1
  ( )
L VDS
L
Different with different L
L＝0.5m，  ≈0.1V-1
L＝1m ，  ≈0.05V-1
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 54
Influence of  on small-signal model
• ID varies with VDS  non-ideal current source
• Finite output resistance ro ，or gds=1/ro
ID 
nCOX W
2
L
(VGS  VTH ) 2 (1  VDS )
VDS
1
1
1
ro 



I DS I DS / VDS 1  C W (V  V ) 2    I DS
n OX
GS
TH
L
2
Important note:
MOS small-signal output resistance can be changed
by adjusting bias current (ID), or transistor length
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 55
Small-signal model considering 
VDD
RD
vout
vin
D
vin
B
G
S
vbs
VSB
Design of Analog CMOS Integrated Circuits
G
D
+
vgs
gmvgs gmbvbs
- S
vbs
+ B
ro
RD
--Ch.2 Basic MOS Device Physics # 56
Sub-threshold Conduction
• “Weak inversion” for VGS< VTH
• Current is not zero but exhibits exponential
dependence on VGS
• What is the influence of this effect on real IC?
VGS
I D  I 0 exp
, (   1, VDS  200mV )
VT
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 57
MOS parasitic capacitance
• C1：Oxide capacitance
• C2：Depletion-layer capacitance
• C3, C4 ： Overlap capacitance
– Overlap capacitance of unit width is Cov；
• C5, C6: Junction capacitance, decomposed into Cj and Cjsw
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 58
Parasitic capacitance model
• A capacitance is modeled between every two of the
four terminals
– CGS and CGD are more important
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 59
Elaborate layout design to reduce parasitic cap.
“folded or “multi-finger” structure
C DB  CSB  WEC j  2(W  E )C jsw
W
W
CDB  EC j  2(  E )C jsw
2
2
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 60
• Multi-finger structure reduces parasitic resistance
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 61
CGS，CGD in different operation region
Important note:
CGS is much larger than CGD in saturation region
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 62
Complete MOS small-signal model
CGD
gmvgs
vgs
CGB
CGS
CSB
gmbvbs
ro
CDB
vbs
CGB, CSB and CDB can be omitted for simplicity
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 63
summary
• General consideration
• MOS I/V characteristics
– Threshold Voltage
– I/V characteristics derivation
• MOS small signal model
– Notations
– Understanding the concept of small signal
– Transconductance of MOS
– Ideal small signal model of MOS
• Second-order effects
– Body effect
– Channel length modulation
– Sub-threshold conduction
– Complete small-signal model
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 64
Assignment -#1
• Problems: 2.5, 2.8, 2.16, 2.17, 2.18
• Hand in on next Thursday.
Design of Analog CMOS Integrated Circuits
--Ch.2 Basic MOS Device Physics # 65