Sample Quiz & Solutions
Sample Quiz & Solutions Q1. Determine the output frequency for a frequency division circuit that contains 12 flip-flops with an input clock frequency of 20.48 MHz. A. 10.24 kHz B. 5 kHz C. 30.24 kHz D. 15 kHz Ans: B Output frequency = Input Freq./2^N. Here N is no of filp-flops. N=12 flip flops = 2^12 = 4096. => 20.48*10^6=20480000. 20480000/4096 = 5000 i.e. 5 kHz. Q2. Which statement BEST describes the operation of a negative-edge-triggered D flip-flop? A. The logic level at the D input is transferred to Q on NGT of CLK. B. The Q output is ALWAYS identical to the CLK input if the D input is HIGH. C. The Q output is ALWAYS identical to the D input when CLK = PGT. D. The Q output is ALWAYS identical to the D input. Ans: A From the truth table of D flip flop, we can observe that Q always depends on D. Hence for every negative trigger pulse, the logic at input D is shifted to Output Q. Q3. How is a J-K flip-flop made to toggle? A. J = 0, K = 0 B. J = 1, K = 0 C. J = 0, K = 1 D. J = 1, K = 1 Ans: D Q4. How many flip-flops are required to produce a divide-by-128 device? A. 1 B. 4 C. 6 D. 7 Ans: D 128 equal to 2 power N where Nis the number of flip flops. 128= 2^N or N=7. 1 Q5. On a master-slave flip-flop, when is the master enabled? A. When the gate is LOW B. When the gate is HIGH C. Both of the above D. Neither of the above Ans: B Q6. Which of the following is correct for a gated D flip-flop? A. The output toggles if one of the inputs is held HIGH. B. Only one of the inputs can be HIGH at a time. C. The output complement follows the input when enabled. D. Q output follows the input D when the enable is HIGH. Ans: D Q7. With four J-K flip-flops wired as an asynchronous counter, the first output change of divider #4 indicates a count of how many input clock pulses? A. 16 B. 8 C. 4 D. 2 Ans: B 4 asynchronous JK ff requires 4 clk pulses to produce 1 output and again 4 clk pulses to produce 1st change in the output. Hence a total of 8 clk pulses. Q8. To completely load and then unload an 8-bit register requires how many clock pulses? A. 2 B. 4 C. 8 D. 16 Ans: D Q9. The bit sequence 0010 is serially entered (right-most bit first) into a 4-bit parallel out shift register that is initially clear. What are the Q outputs after two clock pulses? A. 0000 B. 0010 C. 1000 D. 1111 Ans: C 2 Q10. The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains ________. A. 01110 B. 00001 C. 00101 D. 00110 Ans: C 3
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