©International society of academic and industrial research www.isair.org International Journal of Academic Research in Applied Science IJARAS 1(1): 1-9, 2012 ijaras.isair.org A Unity-Gain Fully-Differential Sample-and-Hold Amplifier in CMOS 0.18µm Technology Win Toe, Samruay Thein Assumption University, Thailand [email protected] Abstract Sample-and-hold circuits are the essential front-end part of an analog-to-digital converter. In this work a fully-differential sample-and-hold circuit based on a two stage differential OpAmp, with sampling frequency of 20MHz is presented. The amplifier has a unity-gain bandwidth of 370MHz and phase-margin of 75°, which meets the requirements for fast settling of the output. Bootstrapped switches are used in order to reduce nonlinearity of conventional transmission gate switches and charge injection effect. A CMOS temperature and voltage-independent current reference is used with temperature and voltage coefficients of 81ppm and 4393ppm respectively. Average power consumption of the system is 2.2mw. Keywords Sample and Hold, operational amplifier, Bootstrapped switches, Analog IC design Int. J. Acad. Res. Appl. Sci., 1(1): 1-9, 2012 1. Introduction Sample-and-hold (S/H) is an important analog building block with many applications, including analog-to-digital converters (ADCs) and switched-capacitor filters. The function of the S/H circuit is to sample an analog input signal and hold this value over a certain length of time for subsequent processing. S/H is used as front-end stage of an ADC. To obtain an analog-to-digital converter with Nbit resolution, the sampling error must be less than 0.5 LSB. A part of this error, including finite-gain error and settling time error, is due to OpAmp's non-ideal properties. Gain error can simply be obtained of, Gain error  1 A (1) In this work, a unity-gain fully-differential S/H amplifier, with sampling frequency of 20MHz, and output voltage-swing of 2Vp-p,diff, for the front end stage of a 10Bit, 50MS/s ADC is presented. The design is in standard TSMC 0.18µm CMOS process and its operation in all corners of process; in temperature range of 0 ~ 85°C and input voltage of 1.8 V ±10% is guaranteed. Maximum allowed error to obtain given specifications is, 0.5LSB  1 V full Scale  0.98mV 2 2n (2) It is essential that the response settles at the sampling time. For sampling frequency of 20MHz, settling time must be less than 24nsec. The deviation of output of its final value at the end of sampling time is known as settling error. To obtain a settling error of less than 0.1%, the output takes more than 7τ, where τ is time constant of the output. 2. Op-Amp Design The needed Op-Amp for the S/H application is designed in two-stage implementation. The first stage is a folded cascade with N-type inputs, as shown in Figure 1. Figure 1 First stage: A folded cascode with CMFB circuit MOSFETs M15-M22 operates as the common-mode-feedback (CMFB) network of the circuit and set the common-mode voltage of the first stage at VREF=0.9V. M15 and M16 operate in deep-triode region. Vb is determined that ID17follows ID18and VREF, 2 Int. J. Acad. Res. Appl. Sci., 1(1): 1-9, 2012 W  W  W  W  W          ,      L 19  L 15  L 16  L 17  L 18 (3) Therefore ID17= ID18, if and only if Vo,cm= VREF. M21 and M22 are added to set VDS17=VDS18to eliminate finite-error due to channel-length modulation. Diode-connected M20 provides bias voltage of M5 and M6 and its size is chosen to equalize Ip and ID17; It is essential for avoiding slewing. To increase the gain of this stage, length of M5/M6 and M9/M10 are chosen twice bigger than Lmin, This will increase output impedance of the stage, by, R out ,stage 1  ( rO 3  rO 5  g m 3 rO 3 rO 5 ) || (rO 7  rO 9  g m 7 rO 7 rO 9 ) (4) To increase the unity gain bandwidth and hence the speed of the amplifier, transconductance of the amplifier should be large enough. Device sizes to meet the goals explained above are shown in tabel1. The second stage is a fully differential amplifier with active load. This architecture is chosen for its high output swing. Because the input common-mode level of this stage is the output common-mode level of the first stage which is fixed, the second stage does not need tail current biasing, therefore fewer voltage headroom consumption. This stage, with a simple structure of CMFB is shown in Fig. 2. In fact, M13/M14, that operate as current references, are biased through output common-mode voltage. Output common-mode voltage is in a level that M9 and M12 balance the current of M13 and M14. The size of M11 specifies the current of this stage to obtain desired gain. Therefore by changing the size of PMOS, the output voltage could be set in proper point, here 0.9V. Table 1 Device Sizes of the First Stage of the Designed Op-Amp. Figure 2 Second stage: A simple fully-differential amplifier with CMFB Network 3 Int. J. Acad. Res. Appl. Sci., 1(1): 1-9, 2012 2.1. Compensation Compensator capacitor (Cc=0.2 pF) is placed between source of cascode MOSFETs (M7, M8) and output node. Using the model of Fig. 3, One zero exists in frequency of gm7Reqgm11/CC, This value is much greater than gm11/CC. If other capacitances be neglected, dominant pole is approximately in frequency, 1/RLReqgm11CC as if Cc were connected to the gate of M11, rather than source of M7. Also, the first non-dominant pole is given by, gm7Reqgm11/CL. In Fig. 4, if Iss > Ip, then during slewing, M3 turns off and Vx falls to a low level such that M1 and the tail current source enters the triode region. Thus for the circuit to return to equilibrium after M2 turns on Vx must experience a large swing, slowing down the settling. To alleviate this issue, two clamp transistors can be added as shown in Fig. 5. The Idea is that the difference with Iss and Ip now flows through Diode-connected transistors, requiring only enough drops in Vx or VY to turn on one of these transistors. These two transistors are off in normal status operation. Figure 3 Equivalent circuit with compensator capacitor Figure 4 Slewing situation 4 Int. J. Acad. Res. Appl. Sci., 1(1): 1-9, 2012 Figure 5 Slewing corrector 2.2. Op-Amp Simulation Results In this section, H-SPICE simulation results of the designed Op-Amp are presented. Simulation is done in 8 corners of CMOS process. At TT, a DC Differential Gain of 8200 (78.3dB), 370 MHZ unity gain bandwidth and 74° Phase margin obtained. With this value of UGBW, the closed loop time constant (in unityfeedback) is of 2.7 nsec, and during 24 nsec, the output passes 8.88τ. Therefore the response is fast and settling time error is so small. HSPICE Simulation results are illustrated in Fig. 6. Notice, this frequency response is calculated where the load capacitance, CL=2pF, is brought in to account. Table 2 shows the simulation results of the Op-Amp in 8 corners of process. The operation of the amplifier is guaranteed in all corners. Figure 6 Simulation results for amplitude and bode plots of the designed Op-Amp Table 2 Gain, unity-gain bandwidth and phase margin of the Op-Amp in 8 corners of CMOS process. 5 Int. J. Acad. Res. Appl. Sci., 1(1): 1-9, 2012 3. Sample-And-Hold Circuit After design of op-amp with desired properties, we are prepared to implement the sample and hold circuit. A greatly used unity-gain differential structure is shown in Figure 7. Operation of differential architecture is similar to single ended, but the input-independent nature of the charge injected by the reset switch allows complete cancelation by differential operation. In the amplification mode, this circuit operates as a unity-gain Buffer, and produces an output voltage approximately equal to voltage stored across the capacitor. Generally, the input capacitance of Op-Amp is assumed finite and calculates the output voltage when the circuit is transferred from sampling mode to amplification mode. Assuming finite gain for the OpAmp, Vx ≠0 in amplification mode, a charge equal to CinVx is injected to Cin. The conservation of charge at X requires that CinVx Come from CH, raising the charge on CH to CinVx+ CHVO. It follows that the voltage across CH equals CinVx+ CHVO/CH. We therefore write V out  (C HV O  C inV X ) / C H V X VX  V out AV 1 (5) Therefore   1  C in V out V O 1   1     AV 1  C H (6) According to the equations above, Cin must be minimized to reduce error. Figure 7 unity-gain differential sample-and-hold 6 Int. J. Acad. Res. Appl. Sci., 1(1): 1-9, 2012 3.1. SWITCHSCLOCKING The switches S1 and S2 must work in same phase, but S2 should turn off a little sooner than S1. When S2 switches off, the input node of Op-Amp, X, get high-impedance, therefore injected charge due to S1 does not affect output voltage. In the on-state cycle of S1 and S2, output voltage will be sampled across CH .Switch S3 operates in a phase against that of S1 and S2. In this phase of operation, the sampled voltage on CH, will be held in the output. Switch Seq is used to solve the problem of different charge injection of Switches S2 and S2’ which cause nonlinearity. Seq switches off a little later than S2’, a little sooner than S1 and S1’, to guarantee equal level on nodes X and Y. 3.2. Simulation Results In this step, differential sinusoidal inputs with 1Vp-p and DC level equals to 1V and frequency of 1MHz and 8MHz are used for simulation. The input/output waveforms of the 1MHz input are illustrated in Fig 8. In table 3, sampling errors of some samples, calculated in a period of input signal are shown. The average of sampling errors is approximately 0.58mv that is smaller than maximum allowed error (0.98mv). In Fig. 9, output waveform, where the phase margin is 100°, is shown. The circuit with such phase margin has little ringing in settling. Average sampling error is 1.7mv, where the input signal frequency is 8MHz. Figure 8 S/H Input/Output waveforms, Cc=0.2pf and phase-margin is 75°. 7 Int. J. Acad. Res. Appl. Sci., 1(1): 1-9, 2012 Table 3 Sampling errors of some samples Figure 9 S/H Input/Output waveforms, where input frequency is 8MHz. 4. CONCLUSION A S/H circuit was simulated through H-SPICE. A robust fully differential amplifier which is the main part of Op-Amps highly needs a proper CMFB. To guarantee stability of the system, Miller consumption was used in the two-stage Op-Amp presented in this work. Switches are the essential part of S/H circuits; as a result, linear response of these blocks is necessary. Bootstrapped switches were used here because of their high linearity. A temperature and voltage independent current reference is designed to obtain a firm current, in spite of temperature and voltage fluctuations. The Op-Amp is the main power consumer part of the S/H circuits; therefore the power consumption of this block should be reduced as low as possible. 8 Int. J. Acad. Res. Appl. Sci., 1(1): 1-9, 2012 REFERENCES 1. B. Razavi, Design of Analog CMOS Integrated Circuit,Mc Graw-Hill, New York, 2003. 2. A. M. Abo and P. R. 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