3V CMOS Rail to Rail Op-Amp
K. M. AbdelMoneim
Department of Electronics and Electrical Engineering
German University of Cairo
Email: [email protected]
Abstract— In this paper, a new CMOS Op-Amp that operates
under low voltage supply having a rail to rail operation is
presented. The proposed Op-Amp has a constant
transconductance at the input stage over the entire common mode
input voltage. A cascode stage that achieves a gain greater than
100dB over almost full range of the common mode input voltage.
A common source configuration that increases the output swing
between the rails. A class AB control circuit is used to provide a
stable biasing at the output stage for the common source
configuration to avoid distortion. Simulation results are provided
using TMSC 0.25 µm CMOS technology.
S. A. Mahmoud
Department of Electronics and Electrical Engineering
German University of Cairo
Email: [email protected]
A. General Architecture
To achieve a rail to rail operation at the input stage over the
common mode input voltage, two complementary MOS
differential pairs are used [1-4] as shown in Fig. 1 where the ndifferential pair will operate for VCM near the positive supply,
the p-differential pair will operate for VCM near the negative
supply and both pairs will be operating for VCM at the mid-rail
values.
Index Terms— Low voltage, CMOS, Rail to rail, gm-Equalizer
circuit, Monitor circuit.
O
I. INTRODUCTION
P-AMPS
are one of the most essential analog building
blocks for analog signal processing [1-5]. One of its
crucial advantages is its use in implementing continuous time
filters that are used to convert the discrete manner of switched
capacitor filters to analog manner. However one of the main
drawbacks of using Op-Amps under low voltage is the
degradation of its performance over the input range specially
at the input stage where the transconductance “gm” is not
constant over the entire common mode input voltage “VCM”
resulting in stability problems. In this paper, an input stage
with constant transconductance over the entire common mode
input voltage is introduced with a rail to rail output stage that
achieves over 100dB gain over full range of input voltage
without distortion. This paper is organized as follows, section
II will introduce the rail to rail operation of the input stage and
discuss the proposed circuit techniques to obtain a constant gm,
section III will introduce each part of the rail to rail output
stage used, and finally in section IV the Pspice simulations for
the proposed CMOS Op-Amp using 0.25 µm CMOS
technology are presented.
II. RAIL TO RAIL INPUT STAGE WITH CONSTANT
TRANSCONDUCTANCE
Fig. 1 CMOS differential pair
The transconductance “gm” of a MOS transistor at saturation
is given by:
gm =
Where
K = µ n , p Cox (
KI bias
(1)
W
) n, p and Ibias is the biasing current of
L
the transistor. There are three regions of operation that are
responsible for the response of the total transconductance
“gmT” and in order to analyze this response in a simple way,
only one of the transistors from each pair is monitored and
thus
978-1-4244-1847-3/07/$25.00 ©2007 IEEE
δ I DS
=
δ VGS
I bias = I tail / , then
IEEE ICM - December 2007
For VCM near VSS,
g mT = g mp = I p K p
(2)
VSG 5 + VGS 6 = va
(5)
For VCM near VDD,
g mT = g mn = I n K n
(3)
VSG 4 + VGS 3 = vb
(6)
For VCM at mid-rail,
g mT = I p K p + I n K n
(4)
VSG 5 + VGS 6 = VSG 4 + VGS 3
(7)
Thus if gmT is made constant over the entire common mode
input voltage, a constant gm could be achieved and this will be
done by manipulating the sum of tail currents of the
differential pairs to be constant over the entire common mode
input voltage. Two circuits are used to achieve constant gmT as
shown in the general architecture in Fig. 2. The function of the
gm-equalizer circuit is to take Ip as an input and produce a tail
current that is dependant on Ip to bias the n-differential pair.
The function of the monitor circuit is to provide Ip for the gmTequalizer circuit after making it dependant on VCM and thus
obtaining In which is dependent on Ip and VCM resulting in not
only a constant gm but also a smooth response for gmT over the
entire common mode input voltage.
Then,
IC K p + I d K n = I n K n + I p K p
(8)
Thus gmT which is the right hand side of Eq.8 is always
constant. Another advantage of this circuit is it’s independence
on mismatches of the n-channel and p-channel transistors and
thus gmT is kept constant although K n ≠ K p which might be
caused during the fabrication process.
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Fig. 3 gm-Equalizer circuit
III. RAIL TO RAIL OUTPUT STAGE
Fig. 2 The complete input stage architecture with constant gmT
B. gm-Equalizer Circuit
For the circuit shown in Fig. 3[2], Ip is taken as the input at
the drain of M3 and the output is In which is maintained at
the drains of M7,M8 and M9 by the current mirror M7-M8
and M7-M9. The output at the drain of M8 is taken to bias
the n-differential pair. M5 and M6 are carrying constant
currents equal to Id and Ic respectively, thus their gate to
source voltages are constant therefore the source of M5 “va”
is always constant. The current mirror M12-M13 results in
equal drain currents at M11 and M10, thus M11 and M10
will have equal source to gate voltages, thus their sources are
equal resulting in a constant source node at M4 “vb”, then the
sources of M5 and M4 are the same and “va=vb”, thus
A. General Architecture
The purpose of the output stage is to provide as large gain
as possible and to obtain an output that swings from rail to rail
without distortion at high frequency signals. The output stage
architecture shown in Fig. 4 consists of a cascode gain stage
[5] that is used to provide a large amount of gain in a single
stage, another stage which is the common source configuration
with a class AB control circuit [4]. The common source
configuration acts as a buffer to the cascode stage and
compensate for its large output resistance and provide the OpAmp with low output resistance. The class AB control circuit
is used to avoid distortion.
B. Class AB Control Circuit
The purpose of the class AB control circuit shown in Fig. 5
is to provide stable biasing for the common source stage and
prevent distortion at the presence of high frequency signals
by providing feedback from the common source stage to the
cascode stage. From the current mirror MO15-MO1-MO2,
Ion is made at the drain of MO11 and MO14, Iop is made at
the drain of MO13 by MO8 and also at the drain of MO14
IEEE ICM - December 2007
by the current mirror MO7-MO6. By considering the loop
through transistors MO11 to MO14 starting from vd and
ending at va, thus
Kp
2
(vd − va ) = I op + I on − I min − I op + I on
(9)
Assuming that the output is near VSS, Ion will be very large
relative to Iop, thus Iop must be prevented from decreasing
below a minimum value to avoid turning off Ms1 so it could
be able to cope with a high frequency signal and prevent
distortion, thus at Ion very large relative to Iop, Eq.9 is reduced
to
Kp
2
(vd − va ) = I op − I min
thus as Iop keeps on decreasing,
expressed by the summation of the tail currents of the input
differential pairs that are almost constant over the entire
common mode input voltage and thus the gmT is also constant.
The complete Op-Amp shown in Fig. 8 was simulated with a
compensation capacitance CC=60pf to improve stability. Fig.
7(a) shows the frequency response of the Op-Amp to obtain
the open loop gain which is 110dB and it remains almost
constant over most of the range of VCM between the rails, Fig.
7(b) shows the input-output voltage characteristic at unity gain
configuration where the output is following the input from
0.2V to 2.8V which is accepted to be said a rail to rail
operation. Finally a transient analysis of the Op-Amp is shown
in Fig. 7(c) which verifies the improved stability of the OpAmp.
(10)
Kp
(vd − va ) will decrease
2
resulting in the decrease of the feedback signals “vc” and “vb”
and thus adjusting the cascode stage to increase Iop and prevent
it from decreasing below a minimum value and thus distortion
is avoided.
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Fig.5 Complete output stage
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V. CONCLUSION
##
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This paper introduced a new CMOS low voltage rail to rail
Op-Amp that has constant transconductance at the input stage
over full range of common mode input voltage with more that
100dB gain without loss of stability. The proposed Op-Amp
has been confirmed using Pspice simulations.
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REFERENCES
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[1]
-
Fig. 4 Output stage architecture
IV. SIMULATION RESULTS
In this section, the simulations of the complete input stage and
the complete Op-Amp will be shown. All simulations were
made with level 7 spice model for 0.25 µm CMOS technology,
with 3V supply voltage and aspect ratios given in tables 1 and
2 for the complete input stage and the output stage
respectively. Shown in Fig. 6 the simulation result of the
complete input stage where the total transconductance is
[2]
[3]
[4]
[5]
R.Hogervorst,
R.J.Wiegerink,
P.A.L de jong,
J.Fonderie,
R.F.Wassenaar and J.H.Huijsing “CMOS low-voltage operational
amplifiers with constant-gm rail-to-rail input stage” Proceedings of the
IEEE International Symposium on Circuits and Systems, pp. 28762879, 1992.
S. Sakurai and M. Ismail, “Robust design of rail-to-rail CMOS
operational amplifiers for a low power supply voltage,” IEEE Journal
of Solid-State Circuits, vol. 31, no. 2, pp. 146-156, 1996
C. Hwang, A. Motamed, and M. Ismail, “Universal constant-gm inputstage architecture for low-voltage op amps,” IEEE Trans. Circuits and
Systems-I, vol. 42. no. 11, pp. 886-895, 1995
S. Sakurai and M. Ismail, Low-Voltage CMOS Operational Amplifiers:
Theory, Design and Implementation, Kluwer Academic Publishers,
1995.
S. A. Mahmoud and A. M. Soliman, "The differential difference
operational floating amplifier: a new block for analog signal
processing," IEEE Trans. Circuits Syst. II, pp.148-158, 1998.
IEEE ICM - December 2007
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Fig. 6. Tail currents and their sum of the input differential pairs
Fig. 7(b). Input-output voltage characteristics
Fig. 7(a). Frequency response
Fig. 7(c). Transient response with 100KHz input pulse
Fig. 8 Complete CMOS Op-Amp
Table 1. Aspect ratios of the complete input stage
Table 2. Aspect ratios of the output stage
Transistors (CMOS
differential pairs)
Aspect Ratio
( µm / µm )
Transistors (gmequalizer circuit)
Aspect Ratio
( µm / µm )
M1a, M1
M2a, M2
170/1
17/1
M3
M4
M5
M6
M10, M11
M12, M13
2/1
21/1
95/1
12.5/1
12/1
13/1
Transistors
Aspect Ratio
( µm / µm )
M33, M44, M55, M66
290/1
M77, M88, M99, M111
10/1
Ms1, MO8
4.1/1
Ms2 (Vbias=1.6V)
17/1
MO15, MO1, MO2
1.8/1
IEEE ICM - December 2007