1. No category

ARM Cortex-A8 CPU Module Family
LITE Line
HARDWARE MANUAL
DAVE Embedded Systems
www.dave.eu
[email protected]
Maya Hardware Manual
v.1.0.3
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Table of Contents
1 Preface.....................................................................................................................................6
1.1 About this manual.............................................................................................................6
1.2 Copyrights/Trademarks.....................................................................................................6
1.3 Standards..........................................................................................................................6
1.4 Disclaimers.......................................................................................................................6
1.5 Warranty............................................................................................................................7
1.6 Technical Support.............................................................................................................7
1.7 Related documents...........................................................................................................9
1.8 Conventions, Abbreviations, Acronyms............................................................................9
2 Introduction.............................................................................................................................12
2.1 Product Highlights...........................................................................................................13
2.2 Block Diagram.................................................................................................................14
2.3 Feature Summary...........................................................................................................15
3 Design overview.....................................................................................................................17
3.1 “Sitara” DM814x/AM387x CPU.......................................................................................17
3.2 DDR2 memory bank.......................................................................................................19
3.3 NAND flash bank............................................................................................................19
3.4 Memory Map...................................................................................................................20
3.5 Power supply unit...........................................................................................................20
3.6 CPU module connectors.................................................................................................20
4 Mechanical specifications......................................................................................................21
4.1 Board Layout...................................................................................................................21
4.2 Connectors......................................................................................................................23
5 System Logic..........................................................................................................................24
5.1 Power..............................................................................................................................24
5.2 PMIC...............................................................................................................................24
5.3 Reset...............................................................................................................................24
5.3.1 MRST (J2.33)..........................................................................................................24
5.3.2 PORSTn (J2.39)......................................................................................................25
5.3.3 RSTOUTn (J2.37)....................................................................................................25
5.3.4 CPU_RESETn (J2.41).............................................................................................25
5.3.5 JTAG_TRSTn (J2.23)..............................................................................................25
5.4 Voltage monitor...............................................................................................................25
5.5 Boot options....................................................................................................................26
5.5.1 Default boot configuration.......................................................................................26
5.5.2 Boot sequence customization.................................................................................27
5.6 Clock scheme.................................................................................................................28
5.7 Recovery.........................................................................................................................28
5.7.1 JTAG Recovery.......................................................................................................28
5.7.2 UART Recovery.......................................................................................................29
5.7.3 SD/MMC Recovery..................................................................................................29
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5.8 Multiplexing.....................................................................................................................30
5.9 RTC.................................................................................................................................30
6 Pinout table............................................................................................................................31
6.1 CPU module mount options............................................................................................32
6.2 Carrier board mating connector J2.................................................................................33
6.3 Additional notes...............................................................................................................41
6.3.1 EN_BCK_LS............................................................................................................41
7 Peripheral interfaces..............................................................................................................42
7.1 Digital Video Output (DVO).............................................................................................42
7.1.1 VOUT0.....................................................................................................................42
7.2 Analog SDTV out............................................................................................................43
7.3 Digital Video Input ports..................................................................................................44
7.3.1 VIN0.........................................................................................................................44
7.4 Ethernet ports.................................................................................................................46
7.4.1 EMAC_RMREFCLK................................................................................................46
7.4.2 Ethernet 10/100.......................................................................................................47
7.4.3 Fast Ethernet EMAC1..............................................................................................48
7.5 CAN ports.......................................................................................................................48
7.5.1 DCAN0.....................................................................................................................48
7.5.2 DCAN1.....................................................................................................................49
7.6 UARTs.............................................................................................................................49
7.6.1 UART0.....................................................................................................................49
7.6.2 UART3.....................................................................................................................50
7.6.3 UART5.....................................................................................................................51
7.7 MMC/SD channels..........................................................................................................51
7.7.1 MMC/SD/SDIO0......................................................................................................52
7.7.2 MMC/SD/SDIO1......................................................................................................52
7.8 USB ports........................................................................................................................53
7.8.1 USB0.......................................................................................................................54
7.8.2 USB1.......................................................................................................................54
7.9 SPI buses........................................................................................................................55
7.9.1 SPI0.........................................................................................................................55
7.9.2 SPI3.........................................................................................................................55
7.10 I2C buses......................................................................................................................56
7.10.1 I2C1.......................................................................................................................56
7.10.2 I2C3.......................................................................................................................56
7.11 Audio interfaces.............................................................................................................57
7.11.1 McASP1.................................................................................................................57
7.11.2 McASP2.................................................................................................................57
7.12 GPIOs...........................................................................................................................58
7.13 Local Bus......................................................................................................................58
8 Operational characteristics....................................................................................................60
8.1 Maximum ratings.............................................................................................................60
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8.2 Recommended ratings....................................................................................................60
8.3 Power consumption........................................................................................................60
8.3.1 Set 1........................................................................................................................61
8.3.2 Use cases................................................................................................................61
8.4 Heat Dissipation..............................................................................................................62
9 Application notes....................................................................................................................63
Index of Tables
Tab. 1: Related documents........................................................................................................9
Tab. 2: Abbreviations and acronyms used in this manual........................................................10
Tab. 3: CPU, Memories, Buses................................................................................................15
Tab. 4: Peripherals...................................................................................................................16
Tab. 5: Electrical, Mechanical and Environmental Specifications............................................16
Tab. 6: DM814x/AM387x comparison......................................................................................19
Tab. 7: SDRAM specifications..................................................................................................19
Tab. 8: NAND flash specifications............................................................................................19
Illustration Index
Fig. 1: MAYA CPU module........................................................................................................12
Fig. 2: NAON and MAYA...........................................................................................................12
Fig. 3: MAYA plugged on MAYAEVB-Lite carrier board............................................................13
Fig. 4: Board layout - top view..................................................................................................21
Fig. 5: Board layout - size view.................................................................................................22
Fig. 6: Connector layout............................................................................................................23
Fig. 7: Boot sequence customization........................................................................................28
Fig. 8: Simplified schematics of EN_BCK2_LS internal pin configuration................................41
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1
1.1
v.1.0.3
Preface
About this manual
This Hardware Manual describes the MAYA CPU modules
series, their design and functions.
Precise specifications for the Texas Instruments
DM814x/AM387x processors can be found in the CPU
datasheets and/or reference manuals.
1.2
Copyrights/Trademarks
Ethernet® is a registered trademark of XEROX Corporation.
All other products and trademarks mentioned in this manual
are property of their respective owners.
All rights reserved. Specifications may change any time without
notification.
1.3
Standards
DAVE Embedded Systems SrL is certified to ISO 9001
standards.
1.4
Disclaimers
DAVE Embedded Systems does not assume any responsibility
about availability, supply and support regarding all the
products mentioned in this manual that are not strictly part of
the MAYA CPU module.
MAYA CPU Modules are not designed for use in life support
appliances, devices, or systems where malfunction of these
products can reasonably be expected to result in personal
injury. DAVE Embedded Systems customers who are using or
selling these products for use in such applications do so at their
own risk and agree to fully indemnify DAVE Embedded
Systems for any damage resulting from such improper use or
sale.
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Warranty
MAYA is warranted against defects in material and
workmanship for the warranty period from the date of
shipment. During the warranty period, DAVE Embedded
Systems will at its discretion decide to repair or replace
defective products. Within the warranty period, the repair of
products is free of charge as long as warranty conditions are
observed.
The warranty does not apply to defects resulting from improper
or inadequate maintenance or handling by the buyer,
unauthorized modification or misuse, operation outside of the
product’s specifications or improper installation or
maintenance.
DAVE Embedded Systems will not be responsible for any
defects or damages to other products not supplied by DAVE
Embedded Systems that are caused by a faulty MAYA module.
1.6
Technical Support
We are committed to making our product easy to use and will
help customers use our CPU modules in their systems.
Technical support is delivered through email to our valued
customers. Support requests can be sent to
[email protected].
Software upgrades are available for download in the restricted
download area of DAVE Embedded Systems web site:
http://www.dave.eu/download/reserved-area. An account is
required to access this area and is provided to customers who
purchase the development kit (please contact
[email protected] for account requests).
Please refer to our Web site at
http://www.dave.eu/dave-cpu-module-am387x-dm814x-maya.ht
ml for the latest product documentation, utilities, drivers,
Product Change Notifications, Board Support Packages,
Application Notes, mechanical drawings and additional tools
and software.
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Related documents
Document
Location
DAVE Embedded http://wiki.dave.eu/index.php/Main_Pa
Systems
ge
Developer's Wiki
MAYA Page on
http://wiki.dave.eu/index.php/Categor
DAVE Embedded y:Maya
Systems
Developer's Wiki
Integration guide
(on DAVE
Embedded
Systems
Developers Wiki)
http://wiki.dave.eu/index.php/Integrati
on_guide_%28Maya%29
Carrier board
design guidelines
http://wiki.dave.eu/index.php/Carrier_
board_design_guidelines_%28SOM
%29
TMS320DM814x
http://www.ti.com/litv/pdf/sprugz8d
DaVinci
Technical
Reference Manual
DM814x Overview http://processors.wiki.ti.com/index.ph
(on TI Embedded p/DM814x_Overview
Processors Wiki )
Tab. 1: Related documents
1.8
Conventions, Abbreviations, Acronyms
Abbreviation Definition
BTN
Button
GPI
General purpose input
GPIO
General purpose input and output
GPO
General purpose output
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Abbreviation Definition
NELK
NAON Embedded Linux Kit
PCB
Printed circuit board
RTC
Real time clock
SOM
System on module
PMIC
Power Management Integrated Circuit
HDVCIP
HD Video Image Coprocessing
HDVPSS
HD Video Processing Subsystems
Tab. 2: Abbreviations and acronyms used in this manual
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Revision History
Version
Date
Notes
0.9.0
October 2012
First Draft
0.9.1
January 2013
Completed chapters 2 and 3
0.9.2
March 2013
First official release
0.9.3
March 2013
Minor fixes
0.9.4
April 2013
Corrected module layout drawing
Minor fixes
1.0.0
April 2013
Released with NELK 4.0.0
Fixed J2.27, J2.29, J2.69, J2.101
default mount options
Minor fixes
1.0.1
May 2013
Added information on
EMAC_RMREFCLK signal
Minor fixes
1.0.2
January 2014
Updated pin J2.45 information
Minor fixes
1.0.3
August 2014
Added EMAC_RMREFCLK
termination resistors information
Minor fixes
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2
v.1.0.3
Introduction
MAYA is a ready-to-use CPU
module/SOM family, based
on Texas Instruments
Cortex-A8 high performance
application processor from
DM814x (“DaVinci”) and
AM387x (“Sitara”) models.
MAYA is specifically
designed for harsh
environments and tiny
spaces and is suitable for
Fig. 1: MAYA CPU module
high-end applications such
as medical instrumentation,
digital signage, security systems and home automation.
MAYA is the top product of DAVE Embedded Systems LITE
Line CPU modules and is built with SO-DIMM 204 pin form
factor. MAYA shares the same CPU with NAON.
Fig. 2: NAON and MAYA
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Product Highlights
● Top class CPU module family based on Texas Instruments
DM814x/AM387x processors models.
● ARM Cortex-A8 architecture @ up to 1 GHz
● HD Video Encoding/Decoding Capabilities (High-Definition
Video Image Coprocessing – HDVICP v2 engine)
● One HD Video input channel
● C674x DSP engine (available on DM8148)
● NEON Multimedia co-processor and PowerVR® SGX 530
Vector/3D Graphics Engine
● On-board flash (NOR and NAND) storage
● Small form factor
● Rich interfaces set including dual CAN, dual Ethernet, SATA
and native 3.3V I/O
● SO-DIMM 204 pin form factor
Fig. 3: MAYA plugged on MAYAEVB-Lite carrier board
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Block Diagram
ADDR/DATA/CTRL (8-bit data, 4-bit addr)
UART0
8 bit
Memory
Controller
UART3
UART5
32 bit
I2C1 (HDMI_I2C)
I2C3
Boot NAND
Flash
DDR2
SDRAM
C674x DSP
(DM814x only)
SPI0
SPI3
SGX 530 3D
Graphic
accelerator
USB0 OTG
204-pin SODIMM edge connector
USB1 OTG
SD/MMC1
VIN0 (up to 16 bit)
TI
DM814x
VOUT0 (up to 24 bit)
“DaVinci”
McASP1 (4-wire)
McASP2 (4-wire)
TV_OUT1
AM387x
CAN0
“Sitara”
CAN1
Ethernet 10/100
PHY
EMAC0 (RMII)
ARM Cortex-A8
Core @ 1 GHz
EMAC1 (RMII only) + MD
Voltage monitor
GPIOs
JTAG
EMU (trace)
HD Video
Coprocessor
HDVICP v2
WDT
I2C0
PMIC
RTC
Reset/control/bootstrap
Power supply (3.3V)
VBAT
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Feature Summary
Feature
Specifications
Options
CPU
“DaVinci” DM814x
“Sitara” AM387x
ARM v7 architecture
Up to 1 GHz
RAM
32-bit DDR2 SDRAM 400 @ MHz
Up to 512 MB
Storage
Flash NAND on Local bus
Bus
8-bit data, 4-bit address bus
Bootable
Tab. 3: CPU, Memories, Buses
Feature
Specifications
Options
Graphics
Controller
HD Video Processing Subsystem
(HDVPSS)
1x up to 24 bit HD Video Output port
Analog TV output
TFT/RGB support
2D/3D Engines NEON Multimedia SIMD coprocessor
PowerVR SGX 530 3D Accelerator
Coprocessors
Up to 750 MHz C674x VLIW DSP
HD Video Coprocessor HDVICP v2
Video capture
1x up to 16 bit HD Video Input port
USB
2x USB OTG, 480 Mbps (integrated PHY)
UARTs
3x UARTs
GPIO
Up to 128 lines, shared with other
functions (interrupts available)
Networks
1x Fast Ethernet with PHY
1x RMII 10/100 Mbps interface + MDIO
High-end Dual CAN controller
SD/MMC
Up to 2x MMC/SD/SDIO Serial interfaces
(up to 48 MHz)
Serial busses
2x I²C, 2x SPI
Audio
2x McASP channels (4-wires)
Timers
Up to 5 programmable general purpose
timers (PWM function available)
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Feature
Specifications
Options
RTC
On board (provided by TPS659113
PMIC), external battery powered
Debug
JTAG
EMU port
Tab. 4: Peripherals
Feature
Specifications
Options
Supply
Voltage
+3.3V
Active power
consumption
Please refer to Section 8.3 - Power
consumption
Dimensions
67,6 mm x 41,9 mm
Weight
<tbd>
MTBF
<tbd>
Operation
temperature
0..70 °C
-40..+85 °C
Shock
<tbd>
Vibration
<tbd>
Connectors
SO-DIMM 204 pins
Connectors
<tbd>
insertion/remo
val
Tab. 5: Electrical, Mechanical and Environmental Specifications
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v.1.0.3
Design overview
The heart of MAYA module is composed by the following
components:
● Texas Instruments DM814x/AM387x processor
● Power supply unit
● DDR2 memory bank
● NAND flash bank
● 204 pin SO-DIMM connector with interfaces signals
This chapter shortly describes the main MAYA components.
3.1
“Sitara” DM814x/AM387x CPU
DM814x DaVinci™ and AM387x Sitara™ are highly-integrated,
scalable and programmable CPU families from Texas
Instruments.
DaVinci™ digital media processor solutions are tailored for
digital audio, video, imaging, and vision applications.
Sitara™ ARM microprocessors (MPUs) are designed to
optimize performance and peripheral support for customers in
a variety of markets.
The architecture is designed to provide video, image, graphics
and processing power sufficient to support the following:
● Home and Industrial automation
● Test and measurement
● Digital Signage
● Medical instrumentation
● Remote monitoring
● Motion control
● Point-of-Sale
● Single Board Computers
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The following subsystems are part of the device:
● Microprocessor unit (MPU) subsystem based on the ARM®
Cortex™-A8 architecture:
 ARM Cortex-A8 RISC processor, with Neon™ Floating-Point
Unit, 32KB L1 Instruction Cache, 32KB L1 Data Cache and
512KB L2 Cache
 CoreSight Embedded Trace Module (ETM)
 ARM Cortex-A8 Interrupt Controller (AINTC)
 Embedded PLL Controller (PLL_ARM)
● PowerVR SGX 530 subsystem for vector/3D graphics
acceleration to support display and gaming effects
● The HDVICP2 is a Video Encoder/Decoder hardware
accelerator supporting a range of encode, decode, and
transcode operations for most major video codec standards.
The main video Codec standards supported in hardware are
MPEG1/2/4 ASP/SP, H.264 BL/MP/HP, VC-1 SP/MP/AP,
RV9/10, AVS-1.0, and ON2 VP6.2/VP7.
● The C674x DSP core is the high-performance floating-point
DSP generation in the TMS320C6000™ DSP platform and is
code-compatible with previous generation C64x Fixed-Point
and C67x Floating-Point DSP generation. The C674x
Floating-Point DSP processor uses 32KB of L1 program
memory with EDC and 32KB of L1 data memory. The DSP
has 256KB of L2 RAM with ECC, which can be defined as
SRAM, L2 cache, or a combination of both.
● The high definition video processing subsystem (HDVPSS)
includes video/graphics display and capture processing using
the latest TI developed algorithms, flexible compositing and
blending engine, and a full range of external video interfaces
in order to deliver high quality video contents to the end
devices.
The following table shows a comparison between the devices,
highlighting the differences:
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Processor DSP
v.1.0.3
3D
HDVICP HDVPSS Max clock
speed
DM8148
Yes
Yes
Yes
Yes
1 GHz
DM8147
Yes
n.a.
Yes
Yes
1 GHz
AM3874
n.a.
Yes
n.a.
Yes
1 GHz
AM3871
n.a.
n.a.
n.a.
n.a.
1 GHz
Tab. 6: DM814x/AM387x comparison
3.2
DDR2 memory bank
DDR2 SDRAM memory bank is composed by a 32-bit width
chip. The following table reports the SDRAM specifications:
CPU connection
SDRAM bus
Size min
64 MB
Size max
512 MB
Width
32 bit
Speed
400 MHz
Tab. 7: SDRAM specifications
3.3
NAND flash bank
On board main storage memory is a 8-bit wide NAND flash. By
default it is the boot memory so it is connected to GPMC_NCS0
chip select. Optionally it can be connected to GPMC_NCS7 in
case a different boot device is implemented.
CPU connection
GPMC bus
Page size
512 byte, 2 kbyte or 4 kbyte
Size min
32 MByte
Size max
2 GByte
Width
8 bit
Bootable
Yes (Default: yes)
Tab. 8: NAND flash specifications
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v.1.0.3
Memory Map
The total system memory is divided across various
processors/subsystems. Due to this “multiprocessor” nature,
Memory Mapping for MAYA Module is quite complex, since it
involves the Cortex-A8 core, the two Media Controllers
(Cortex-M3, that take care of the HDVPSS and HDVCIP
subsystems) and the DSP. NELK Memory Map is described in
detail on the dedicated page on the Developer's Wiki:
http://wiki.dave.eu/index.php/Memory_organization_%28Naon
%29
3.5
Power supply unit
MAYA embeds all the elements required for powering the unit,
therefore power sequencing is self-contained and simplified.
Nevertheless, power must be provided from carrier board, and
therefore users should be aware of the ranges power supply
can assume as well as all other parameters. For detailed
information, please refer to Section 5.1.
3.6
CPU module connectors
All interface signals MAYA provides are routed through a 204
pin SODIMM connector. The host board must mount the mating
connector and connect the desired peripheral interfaces
according to MAYA pinout specifications.
For mechanical information, please refer to Section 4
(Mechanical specifications). For pinout and peripherals
information, please refer to Sections 6 (Pinout table) and 7
(Peripheral interfaces).
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v.1.0.3
Mechanical specifications
This chapter describes the mechanical characteristics of the
MAYA module.
Mechanical drawings are available in DXF format from
the MAYA page on DAVE Embedded Systems website:
http://www.dave.eu/dave-cpu-module-am387x-dm814x-m
aya.html
4.1
Board Layout
The following figure shows the physical dimensions of the
MAYA module:
Fig. 4: Board layout - top view
● Board height: 41.9 mm
● Board width: 67.6 mm
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● Height of all components is < 4.3 mm.
● PCB thickness is 1.0 mm.
The following figure highlights the maximum components'
heights on MAYA module:
Fig. 5: Board layout - size view
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v.1.0.3
Connectors
The following figure shows the MAYA connector layout:
Fig. 6: Connector layout
The following table reports connectors specifications:
Model
Small Outline Dual In-line Memory Module
SO-DIMM 204 pin
Height
4,0 mm
Length
71,0 mm
Pitch
0.6 mm
Mating
connectors
TE Connectivity 2-2013022-1
DDR3 SO DIMM 204 position Right Angle
Surface Mount
4.0mm Height
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5.1
v.1.0.3
System Logic
Power
Implementing correct power-up sequence for DM814x/AM387x
processor is not a trivial task because several power rails are
involved. MAYA hides this complexity because it embeds most
of the circuitry required.
In typical applications AM387x/DM814x processor interfaces
directly to 3.3V-powered devices that are hosted on carrier
board. In order to be compliant with AM387x/DM814x
power-up requirements, these devices should be turned on at a
specific time during power-up sequence. To achieve this, MAYA
provides EN_BCK2_LS signal. When MAYA is powered, this
signal is low: this means that carrier board 3.3V-powered
devices must be powered off. During power-up sequence this
signal shall be raised by MAYA circuitry, indicating carrier
board 3.3V-powered devices have to be turned on. After this
rising edge, EN_BCK2_LS shall be kept high.
5.2
PMIC
This section will be completed in a future version of this
manual.
5.3
Reset
Five different signals are provided by MAYA SOM. Following
sections describes in more detail each one.
5.3.1
MRST (J2.33)
This pin is connected to HDRST signal (cold reset) of PMIC
TPS659113. When high, this signals keeps PMIC in off mode
and resets TPS659113 to default settings. MRST has a weak
internal pulldown.
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v.1.0.3
PORSTn (J2.39)
PORSTn is a bidirectional open-drain signal. It is connected to:
● PORn input (Power-on Reset) of DM8148 processor
● output of voltage monitor (see Section 5.4)
● NRESPWRON2 output of PMIC.
Internal pullup is 10kOhm.
5.3.3
RSTOUTn (J2.37)
This output signal is asserted by DM8148 processor until it
gets out of reset. It is usually used to reset external memories
and peripherals connected to processor. It is connected to:
● RSTOUT_WD_OUTn pad of DM8148 processor
● 1k pull down resistor
● peripherals and memories.
In case it is used to reset devices on carrier board, its driving
capability has to be taken into account.
5.3.4
CPU_RESETn (J2.41)
This input signal acts as External Warm Reset. It is connected
to processor's RESETn pad. Internal pullup is 2.7kOhm.
5.3.5
JTAG_TRSTn (J2.23)
This input signal acts as Emulation Warm Reset. It is connected
to processor's TRSTn pad. Internal pulldown is 4.7kOhm
5.4
Voltage monitor
MAYA SOM is equipped with a multiple-input voltage monitor
whose reset output is connected to PORSTn. Monitored voltage
rails include 3.3V provided by carrier board.
5.5
Boot options
Thanks to the versatility of internal BootROM,
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DM814x/AM387x processors provide a rich set of boot options
and different configurations selectable via BTMODE[15:0]
bootstrap pins. For a detailed explanation on the boot process
for DM814x/AM387x processors, please refer to the Technical
Reference Manual (available from TI website) at section ROM
Code Memory and Peripheral Booting. In order to fully
understand how boot work on MAYA platform, please refer to
Section 3.4 (Memory Map).
By default, MAYA provides the following configuration:
SYS_BOOT
pin
BTMODE[15]
BTMODE[14:13]
Default
Value
0
10
Function
Configurable
GPMC CS0 Wait enable
NO
GPMC CS0
Address/Data
multiplexing mode
NO
BTMODE[12]
1
GPMC CS0 bus width
NO
BTMODE[11]
0
RSTOUT_WD_OUT
Configuration
NO
BTMODE[10]
0
XIP (on GPMC) Boot
Options
NO
BTMODE[9:8]
01
Ethernet PHY Mode
Selection
NO
BTMODE[7:5]
000
Reserved
NO
BTMODE[4:0]
10111
Boot Mode Order
YES
Bootstrap pins BTMODE[4:0] are routed to main connectors in
order to allow to change bootstrap strategy in user's
application by optional external circuitry.
5.5.1
Default boot configuration
With the default configuration, the boot sequence is:
1. MMC
2. SPI
3. UART
4. EMAC
The internal BootROM tries each boot mode in sequence and
stops when it find a valid boot code. For example, assuming
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that:
1. default configuration is not changed,
2. no boot MMC card is connected to processor's MMC1
interface,
3. and there's a valid boot code programmed in SPI memory
the boot sequence performed by ARM core will be:
1. execute bootrom from internal ROM code memory
2. launch 1st stage bootloader
•
copied from on-board NOR flash memory connected to SPI0
port to on-chip SRAM by bootrom
•
executed from on-chip SRAM
3. launch 2nd stage bootloader
•
copied by 1st stage bootloader from NOR flash memory
connected to SPI0 port to SDRAM
•
executed from SDRAM
If no boot code is available in SPI NOR flash (for the bootrom
this means that the first sector read returns 0xFFFFFFFF) the
bootrom tries UART (please see also Section 5.7) and EMAC
peripheral booting.
5.5.2
Boot sequence customization
The following reference schematic shows a simple resistor
network that can be implemented on carrier board hosting
MAYA module. Through dip-switches, for each BTMODE[4:0]
pin it is possible to change default value that is set on module
itself. The available boot mode orders are reported in Table 4-8.
“BTMODE[4-0] Configuration Pins” in Section 4 “ROM Code
Memory and Peripheral Booting” of the DM814x/AM387x
Technical Reference Manual.
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Fig. 7: Boot sequence customization
5.6
Clock scheme
This section will be completed in a future version of this
manual.
5.7
Recovery
For different reason, starting from image corruption due power
loss during upgrade or unrecoverable bug while developing a
new U-Boot feature, the user will need, sooner or later, to
recover (bare-metal restore) the MAYA SOM without using the
bootloader itself. The following paragraphs introduce the
available options. For further information, please refer to DAVE
Embedded Systems Developers Wiki or contact the Technical
Support Team.
5.7.1
JTAG Recovery
JTAG recovery, though very useful (especially in development
or production environment), requires dedicated hardware and
software tools. MAYA provides the JTAG interface, which,
besides the debug purpose, can be used for programming and
recovery operations. For further information on how to use the
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JTAG interface, please contact the Technical Support Team.
5.7.2
UART Recovery
UART recovery does not requires any specialized hardware,
apart a PC and a DB9 serial cross cable. The boot sequence
must include the UART option and a way to enable it. Then a
simple procedure allow to load the 1st and 2nd stage bootloader
from the serial line. When the 2nd stage bootloader is running,
reprogramming the flash memory is straightforward.
The UART boot uses UART0 interface.
5.7.3
SD/MMC Recovery
MMC recovery is a valuable option that requires no special
hardware at all, apart a properly formatted MMC. The boot
sequence must include the SD/MMC option and a way to enable
it. When SD/MMC boot option is selected, bootrom looks for a
valid boot sector on SD/MMC1. Once the board is running after
booting from SD, reprogramming the flash memory is
straightforward.
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5.8
v.1.0.3
Multiplexing
DM814x/AM387x pins can have up to seven alternate function
modes. The I/O pins can be internally routed to/from one of
several peripheral modules within the device: this routing is
referred to as Pin Multiplexing. Pin Multiplexing allows
software to choose the subset of internal signals which will be
mapped to balls of the device for a given application. Pin
multiplexing selects which one of several peripheral pin
functions controls the pin's I/O buffer output data values.
Please note that pin mux configuration is a very critical
step. Wrong configuration may lead to system instability,
side effects or even damage the hardware permanently
Pin multiplexing configuration is quite complex in MAYA but a
tool from TI, the Pin Mux Utility, can help to perform this
operation. Software installation and generic usage
documentation is available on this page of the TI Embedded
Processors Wiki:
http://processors.wiki.ti.com/index.php/Pin_Mux_Utility_for_AR
M_MPU_Processors
5.9
RTC
The TPS659110 PMIC provides a real-time clock (RTC)
resource with
● Oscillator for 32.768-kHz crystal
● Date, time and calendar
● Alarm capability
● Backup power from external battery
Backup power is provided through the VBAT (J2.16) signal. If
not used, VBAT must be externally connected to GND.
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6
v.1.0.3
Pinout table
This chapter contains the pinout description of the MAYA
module. Pinout information is is listed in a table that reports
the pin mapping of the 204-pin SO-DIMM connector.
Each row in the pinout table contains the following
information:
Pin
Reference to the connector pin
Pin Name
Pin (signal) name on the MAYA connector
Internal
Connections
Connections to the MAYA components:
CPU.<x> : pin connected to CPU pad named <x>
CAN.<x> : pin connected to the CAN transceiver
PMIC.<x> : pin connected to the Power Manager IC
LAN.<x> : pin connected to the LAN PHY
SV.<x>: pin connected to voltage supervisor
Ball/pin #
Component ball/pin number connected to signal
Supply Group Power Supply Group
Type
Pin type: I = Input, O = Output, Z = High impedance,
S = Supply voltage, G = Ground, A = Analog signal
Voltage
I/O voltage
The Internal connection column reports the name of the
microprocessor signal, which in turn contains references to all
the peripheral functions that can be associated to that pin. For
example, the following pin name
CPU.VOUT[1]_B_CB_C[4]/EMAC[1]_MRXD[0]/VIN[1]A_D[1]/UA
RT4_RXD/GP3[1]
means that the pin can be used as:
● VOUT[1]_B_CB_C[4]: Video output data, port 1, B/CB/C color bit 4
● EMAC[1]_MRXD[0]: Ethernet MAC, port 1, [G]MII Receive Data,
bit 0
● VIN[1]A_D[1]: Video input channel 1, port A data input bit 1
● UART[4]_RXD: UART port 4, receive data input
● GP3[1]: General Purpose I/O port 3, channel 1
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The following table reports all the function names that can be
found on the Internal connection and the associated
description.
Function Description
name
6.1
VOUT[x]
Digital video output. “x” represents the port number (0 or
1).
VIN[x]A/B
Digital video input. “x” represents the capture number (0
or 1). Each capture has two ports (A and B)
EMAC[x]
Ethernet MAC. “x” represents the port number (0 or 1)
UART[x]
UART port. “x” represents the port number (0 to 5)
GPx[y]
General Purpose I/O port. “x” represents the port number
(0 to 3)
SPI[x]
SPI channel. “x” represents the channel number (0 to 3)
DCAN[x]
Controller Area Network module. “x” represents the
module number (0 to 1)
SD[x]
MMC/SD/SDIO interfaces. “x” represents the interface
number (0 to 2)
GPMC
General Purpose Memory Controller (local bus)
MD
Management Data I/O module
MCA[x]
Multi-Channel Audio Serial Port (McASP). “x” represents
the port number (0 to 5)
I2C[x]
I2C channel. “x” represents the channel number (0 to 3)
TIMx
General purpose timer. “x” represents the terminal
number (0 to 7)
CPU module mount options
Some pins can be configured for different functions through
mounting options. The rows into the table appear as the
following:
J2.27
TPS_PWRON
EMU1
PMIC.PWRON
CPU.EMU1
E4
AE11
Module mount option
The row content is split in two: the default pin configuration is
the upper one (eg TPS_PWRON); the optional pin configuration
is the lower one (eg EMU1).
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6.2
v.1.0.3
Carrier board mating connector J2
J2 SO-DIMM Connector
Pin
J2.1
J2.2
J2.3
J2.4
J2.5
J2.6
J2.7
J2.8
J2.9
J2.10
J2.11
J2.12
J2.13
J2.14
J2.15
J2.16
DGND
DGND
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
JTAG_TCK
DGND
JTAG_RTCK
VBAT
DGND
DGND
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
+3V3
CPU.TCLK
DGND
CPU.RTCK
PMIC.VBACKUP
Ball/
pin #
W7
AD4
D7
J2.17
J2.18
J2.19
J2.20
J2.21
J2.22
J2.23
J2.24
J2.25
J2.26
JTAG_TDI
TV_OUT1
JTAG_TDO
SD1_DAT0
JTAG_TMS
SD1_DAT1
JTAG_TRSTn
SD1_DAT2
DGND
SD1_DAT3
EMU1
TPS_PWRON
DGND
EMU0
TPS_PWRHOLD
CPU.TDI
CPU.TV_OUT0
CPU.TDO
CPU.SD1_DAT[0]
CPU.TMS
CPU.SD1_DAT[1]_SDIRQn
CPU.TRSTn
CPU.SD1_DAT[2]_SDRWn
DGND
CPU.SD1_DAT[3[
CPU.EMU1
PMIC.PWRON
DGND
CPU.EMU0
PMIC.PWRHOLD
Y7
AH24
AC5
P1
AA7
P5
AA4
P4
P6
AE11
E4
AG8
N1
J2.27
J2.28
J2.29
Pin Name
Internal Connections
August, 2014
Supply
Group
Type
G
G
S
S
S
S
S
S
S
S
S
S
I
G
O
S
Voltage
1.8V/3.3V
1.8V/3.3V
If not used, VBAT must be externally
connected to GND.
I
O
O
I/O
I
I/O
1.8V/3.3V
1.8V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
I/O
G
I/O
I/O
1.8V/3.3V
G
I/O
Note
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
Module mount option
Module mount option
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J2 SO-DIMM Connector
Pin
Pin Name
J2.30
J2.31
J2.32
J2.33
J2.34
SD1_CMD
PMIC_RESET
SD1_CLK
MRSTn
SD1_DAT4
J2.35
J2.36
DGND
SD1_DAT5
J2.37
J2.38
RSTOUTn
SD1_DAT6
J2.39
J2.40
PORSTn
SD1_DAT7
J2.41
J2.42
J2.43
J2.44
J2.45
CPU_RESETn
SD0_CMD
CPU_NMIn
SD0_CLK
EN_BCK2_LS
J2.46
J2.47
DGND
MEM_WP#
J2.48
J2.49
J2.50
J2.51
J2.52
J2.53
J2.54
J2.55
J2.56
VOUT0_B_CB_C2/GP2_22
SPI0_D1
VOUT0_B_CB_C3/GP2_23
SPI0_D0
VOUT0_B_CB_C4
DGND
VOUT0_B_CB_C5
SPI0_SCLK
VOUT0_B_CB_C6
Internal Connections
CPU.SD1_CMD/GP0[0]
PMIC.HDRST
CPU.SD1_CLK
SV.MR
CPU.SD0_DAT[0]/SD1_DAT[4]/SC1_DATA/G
P0[3]
DGND
CPU.SD0_DAT[1]_SDIRQn/SD1_DAT[5]/SC1
_CLK/GP0[4]
CPU.RSTOUTn_WD_OUTn
CPU.SD0_DAT[2]_SDRWn/SD1_DAT[6]/SC1
_RST/GP0[5]
CPU.PORn
CPU.SD0_DAT[3]/SD1_DAT[7]/SC1_VCCEN/
GP0[6]
CPU.RESETn
CPU.SD0_CMD/SD1_CMD/SC1_DET/GP0[2]
CPU.NMIn
CPU.SD0_CLK/SC1_C4/GP0[1]
PMIC.GPIO0
DGND
SV.RSTVDD
NAND.WP
CPU.VOUT[0]_B_CB_C[2]/EMU2/GP2[22]
CPU.SPI[0]_D[1]
CPU.VOUT[0]_B_CB_C[3]/GP2[23]
CPU.SPI[0]_D[0]
CPU.VOUT[0]_B_CB_C[4]
DGND
CPU.VOUT[0]_B_CB_C[5]
CPU.SPI[0]_SCLK
CPU.VOUT[0]_B_CB_C[6]
Ball/
pin #
P2
L6
P3
3
R7
Supply
Group
Type
Voltage
I/O
1.8V/3.3V
O
1.8V/3.3V
I/O
1.8V/3.3V
Y5
G
I/O
1.8V/3.3V
K6
Y3
O
I/O
1.8V/3.3V
1.8V/3.3V
F1
Y4
I
I/O
1.8V/3.3V
1.8V/3.3V
J5
N1
H7
Y6
L5
I
I/O
I
I/O
I
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1
19
AG7
AF3
AE15
AE3
AD11
AD15
AC7
AC10
G
August, 2014
Note
This pin is a 5V push-pull signal
connected to a voltage divider circuit
via 5K6 /10K resistor, thus providing
the 3V3 logical voltage output
(please refer to 6.3.1).
MEM_WP# for NAND Write Protect
during power down
I/O
I/O
I/O
I/O
O
G
O
I/O
O
I/O
1.8V/3.3V
I/O
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
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J2 SO-DIMM Connector
Pin
Pin Name
Internal Connections
J2.57
J2.58
J2.59
SPI0_SCS0n
VOUT0_B_CB_C7
SPI0_SCS1n/SD1_SDCD/S
ATA_ACT0_LED
VOUT0_B_CB_C8
VOUT0_CLK
VOUT0_B_CB_C9
VOUT0_HSYNC
DGND
VOUT0_VSYNC
VOUT0_G_Y_YC2/GP2_24
VOUT0_AVID/VOUT0_FLD
/GP2_21
VOUT0_G_Y_YC3/GP2_25
VOUT0_FLD
CPU.SPI[0]_SCS[0]n
CPU.VOUT[0]_B_CB_C[7]
CPU.SPI[0]_SCS[1]n/SD1_SDCD/SATA_ACT
0_LED/EDMA_EVT1/TIM4_IO/GP1[6]
CPU.VOUT[0]_B_CB_C[8]
CPU.VOUT[0]_CLK
CPU.VOUT[0]_B_CB_C[9]
CPU.VOUT[0]_HSYNC
DGND
CPU.VOUT[0]_VSYNC
CPU.VOUT[0]_G_Y_YC[2]/EMU3/GP2[24]
CPU.VOUT[0]_AVID/VOUT[0]_FLD/SPI[3]_S
CLK/TIM7_IO/GP2[21]
CPU.VOUT[0]_G_Y_YC[3]GP2[25]
CPU.VOUT[0]_FLD/CAM_PCLK/PATA_RESET
n/GPMC_A[12]/UART2_RTSn/GP2[02]
PMIC.PWRDN
CPU.VOUT[0]_G_Y_YC[4]
DGND
CPU.VOUT[0]_G_Y_YC[5]
CPU.VOUT[0]_R_CR[2]/EMU4/GP2[26]
CPU.VOUT[0]_G_Y_YC[6]
CPU.VOUT[0]_R_CR[3]/GP2[27]
CPU.VOUT[0]_G_Y_YC[7]
CPU.VOUT[0]_R_CR[4]
CPU.VOUT[0]_G_Y_YC[8]
CPU.VOUT[0]_R_CR[5]
CPU.VOUT[0]_G_Y_YC[9]
CPU.VOUT[0]_R_CR[6]
DGND
CPU.VOUT[0]_R_CR[7]
CPU.USB0_DP
CPU.VOUT[0]_R_CR[8]
CPU.USB0_DM
CPU.VOUT[0]_R_CR[9]
CPU.USB0_VBUSIN
J2.60
J2.61
J2.62
J2.63
J2.64
J2.65
J2.66
J2.67
J2.68
J2.69
J2.70
J2.71
J2.72
J2.73
J2.74
J2.75
J2.76
J2.77
J2.78
J2.79
J2.80
J2.81
J2.82
J2.83
J2.84
J2.85
J2.86
J2.87
J2.88
TPS_PWRDN
VOUT0_G_Y_YC4
DGND
VOUT0_G_Y_YC5
VOUT0_R_CR2/GP2_26
VOUT0_G_Y_YC6
VOUT0_R_CR3/GP2_27
VOUT0_G_Y_YC7
VOUT0_R_CR4
VOUT0_G_Y_YC8
VOUT0_R_CR5
VOUT0_G_Y_YC9
VOUT0_R_CR6
DGND
VOUT0_R_CR7
USB0_DP
VOUT0_R_CR8
USB0_DM
VOUT0_R_CR9
USB0_VBUS
Ball/
pin #
AD6
AB10
AE5
Supply
Group
Type
Voltage
I/O
I/O
I/O
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
AF15
AD12
AG15
AC11
AB13
AH7
AA10
O
O
O
O
G
O
I/O
I/O
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
AH15
AF18
I/O
I/O
1.8V/3.3V
1.8V/3.3V
Note
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
Module mount option
N2
AB8
AB12
AD9
AA8
AB9
AD14
AA9
AE14
AF8
AF14
AF6
AF12
AG11
AE8
AH11
AC13
AG12
August, 2014
O
G
O
I/O
O
I/O
O
O
O
O
O
O
G
O
A I/O
O
A I/O
O
AI
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
3.3V
1.8V/3.3V
3.3V
1.8V/3.3V
3.3V
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J2 SO-DIMM Connector
Pin
J2.89
J2.90
J2.91
J2.92
J2.93
J2.94
J2.95
J2.96
J2.97
J2.98
J2.99
J2.100
Pin Name
DGND
USB1_VBUS
USB0_DRVVBUS
USB1_DP
USB0_ID
USB1_DM
USB0_CE
DGND
USB1_DRVBUS
J2.102
UART0_RXD
USB1_ID
UART0_TXD
USB1_CE
DEVOSC_WAKE/TIM5_IO/
GP1_7
UART0_RTSn/DCAN1_RX
J2.103
J2.104
DGND
UART0_CTSn/DCAN1_TX
J2.105
GPMC_A11/CAM_FLD/CA
M_WEn
J2.106
UART3_RTSn
J2.107
EMAC1_RGMII_RXCTL
J2.108
UART3_RXD/SD1_POW
J2.109
UART5_TXD
J2.110
UART3_TXD/SD1_SDWP
J2.111
CAN0_TX
J2.101
Internal Connections
Ball/
pin #
DGND
CPU.USB1_VBUSIN
AG14
CPU.USB0_DRVVBUS/GP0[7]
AF11
CPU.USB1_DP
AG13
CPU.USB0_ID
AG10
CPU.USB1_DM
AH13
CPU.USB0_CE
AH10
DGND
CPU.AUD_CLKIN0/MCA[0]_AXR[7]/MCA[0]_ L5
AHCLKX/MCA[3]_AHCLKX/ATL_CLKOUT1/A
TL_CLKOUT0/VCX_VIC[0]/USB1_DRVVBUS
CPU.UART0_RXD
AH5
CPU.USB1_ID
AH12
CPU.UART0_TXD
AG5
CPU.USB1_CE
AH14
CPU.DEVOSC_WAKE/SPI[1]_SCS[1]n/TIM5_ W6
IO/GP1[7]
CPU.UART0_RTSn/UART4_TXD/DCAN1_RX/ AF5
SPI[1]_SCS[2]n/SD2_SDCD
DGND
CPU.UART0_CTSn/UART4_RXD/DCAN1_TX/ AE6
SPI[1]_SCS[3]n/SD0_SDCD
CPU.VOUT[1]_FLD/CAM_FLD/CAM_WEn/PA AB23
TA_INTRQ/GPMC_A[11]/UART2_CTSn/GP0[
28
CPU.UART0_RIN/UART3_RTSn/UART1_RXD/ AF4
GP1[5]
CPU.EMAC[0]_MRXD[3]/GPMC_A[27]/GPM J25
C_A[26]/GPMC_A[0]/UART5_RXD
CPU.UART0_DCDn/UART3_RXD/SPI[0]_SCS AH4
[3]n/I2C[2]_SCL/SD1_POW/GP1[2]
CPU.EMAC[0]_MRXD[4]/GPMC_A[1]/UART5 T23
_TXD
CPU.UART0_DSRn/UART3_TXD/SPI[0]_SCS AG4
[2]n/I2C[2]_SDA/SD1_SDWP/GP1[3]
CPU.DCAN0_TX/UART2_TXD/I2C[3]_SDA/G AH6
August, 2014
Supply
Group
Type
G
AI
I/O
A I/O
AI
A I/O
AO
G
I/O
Voltage
Note
3.3V
1.8V/3.3V
3.3V
3.3V
3.3V
3.3V
1.8V/3.3V
I
AI
O
AO
I/O
1.8V/3.3V
3.3V
1.8V/3.3V
3.3V
1.8V/3.3V
I/O
1.8V/3.3V
G
I/O
1.8V/3.3V
I/O
1.8V/3.3V
I/O
1.8V/3.3V
I/O
1.8V/3.3V
I/O
1.8V/3.3V
I/O
1.8V/3.3V
I/O
1.8V/3.3V
I/O
1.8V/3.3V
Module mount option
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v.1.0.3
J2 SO-DIMM Connector
Pin
Pin Name
J2.112
UART3_CTSn
J2.113
CAN0_RX
J2.114
J2.115
J2.116
J2.117
J2.118
J2.119
J2.120
J2.121
J2.122
J2.123
J2.124
DGND
VIN0A_D0/GP1_11
MCA1_ACLKX
VIN0A_D1/GP1_12
MCA1_AFSX
VIN0A_D2/GP2_7
MCA1_AXR0
DGND
MCA1_AXR1
VIN0A_D3/GP2_8
TIM2_IO/GP0_8
J2.125
J2.126
J2.127
J2.128
J2.129
J2.130
VIN0A_D4/GP2_9
MCA2_ACLKX/GP0_10
VIN0A_D5/GP2_10
MCA2_AFSX/GP0_11
VIN0A_D6/GP2_11
MCA2_AXR0/GP0_12
J2.131
J2.132
J2.133
J2.134
VIN0A_D7/GP2_12
DGND
VIN0A_D8_BD0/GP2_13
MCA2_AXR1/GP0_13
J2.135
J2.136
VIN0A_D9_BD1/GP2_14
MCA2_AHCLKX/GP0_9
J2.137
J2.138
VIN0A_D10_BD2/GP2_15
SPI3_SCS1n/GP3_14
Internal Connections
P1[0]
CPU.UART0_DTRn/UART3_CTSn/UART1_TX
D/GP1[4]
CPU.DCAN0_RX/UART2_RXD/I2C[3]_SCL/G
P1[1]
DGND
CPU.VIN[0]A_D[0]/GP1[11]
CPU.MCA[1]_ACLKX
CPU.VIN[0]A_D[1]/GP1[12]
CPU.MCA[1]_AFSX
CPU.VIN[0]A_D[2]/GP2[7]
CPU.MCA[1]_AXR[0]/SD0_DAT[4]/SC0_RST
DGND
CPU.MCA[1]_AXR[1]/SD0_DAT[5]/SC0_DET
CPU.VIN[0]A_D[3]/GP2[8]
CPU.AUD_CLKIN1/MCA[0]_AXR[8]/MCA[1]_
AHCLKX/MCA[4]_AHCLKX/ATL_CLKOUT2/E
DMA_EVT3/TIM2_IO/GP0[8]
CPU.VIN[0]A_D[4]/GP2[9]
CPU.MCA[2]_ACLKX/SC0_C4/GP0[10]
CPU.VIN[0]A_D[5]/GP2[10]
CPU.MCA[2]_AFSX/SC0_DATA/GP0[11]
CPU.VIN[0]A_D[6]/GP2[11]
CPU.MCA[2]_AXR[0]/SD0_DAT[6]/SC0_CLK
/UART5_RXD/GP0[12]
CPU.VIN[0]A_D[7]/GP2[12]
DGND
CPU.VIN[0]A_D[8]_BD[0]/GP2[13]
CPU.MCA[2]_AXR[1]/SD0_DAT[7]/SC0_VCC
EN/UART5_TXD/GP0[13]
CPU.VIN[0]A_D[9]_BD[1]/GP2[14]
CPU.UD_CLKIN2/MCA[0]_AXR[9]/MCA[2]_A
HCLKX/MCA[5]_AHCLKX/ATL_CLKOUT3/ED
MA_EVT2/TIM3_IO/GP0[9]
CPU.VIN[0]A_D[10]_BD[2]/GP2[15]
CPU.VOUT[1]_R_CR[4]/EMAC[1]_MTXD[3]/
VIN[1]A_D[15]/PATA_D[7]/SPI[3]_SCS[1]n/
Ball/
pin #
Supply
Group
Type
Voltage
AG2
I/O
1.8V/3.3V
AG6
I/O
1.8V/3.3V
AF9
U5
AB11
V3
AC9
V4
T6
AE12
R5
G
I/O
I/O
I/O
I/O
I/O
I/O
G
I/O
I/O
I/O
AH8
U6
AG16
AA5
AH16
N2
I/O
I/O
I/O
I/O
I/O
I/O
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
AA11
AB15
V6
I/O
G
I/O
I/O
1.8V/3.3V
AG9
H1
I/O
I/O
1.8V/3.3V
1.8V/3.3V
AH9
AG27
I/O
I/O
1.8V/3.3V
1.8V/3.3V
August, 2014
Note
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
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v.1.0.3
J2 SO-DIMM Connector
Pin
Pin Name
J2.139
J2.140
DGND
SPI3_SCLK/GP3_15
J2.141
J2.142
VIN0A_D11_BD3/CAM_W
En
SPI3_D1/GP3_16
J2.143
VIN0A_D12_BD4/GP2_17
J2.144
SPI3_D0/GP3_17
J2.145
VIN0A_D13_BD5/CAM_RE
SET
VIN0A_FLD/UART5_RXD
J2.146
J2.147
J2.148
J2.149
VIN0A_D14_BD6/CAM_ST
ROBE
VIN0A_DE/UART5_TXD
J2.150
J2.151
VIN0A_D15_BD7/CAM_SH
UTTER
DGND
VIN0A_FLD/CAM_D5
J2.152
J2.153
VIN[0]B_CLK/GP1_9
VIN0A_DE/CAM_D7
J2.154
CAM_D4
J2.155
J2.156
VIN0A_CLK/GP2_2
CAM_D6
J2.157
DGND
Internal Connections
GP3[14]
DGND
CPU.VOUT[1]_R_CR[5]/EMAC[1]_MTXD[4]/
VIN[1]A_D[16]/PATA_D[8]/SPI[3]_SCLK/GP3
[15]
CPU.VIN[0]A_D[11]_BD[3]/CAM_WEn/GP2[
16]
CPU.VOUT[1]_R_CR[6]/EMAC[1]_MTXD[5]/
VIN[1]A_D[17]/PATA_D[9]/SPI[3]_D[1]/GP3
[16]
CPU.VIN[0]A_D[12]_BD[4]/CLKOUT1/GP2[
17]
CPU.VOUT[1]_R_CR[7]/EMAC[1]_MTXD[6]/
VIN[1]A_D[18]/PATA_D[10]/SPI[3]_D[0]/GP
3[17]
CPU.VIN[0]A_D[13]_BD[5]/CAM_RESET/GP
2[18]
CPU.VIN[0]A_FLD/VIN[0]B_VSYNC/UART5_
RXD/I2C[2]_SCL/GP2[1]
CPU.VIN[0]A_D[14]_BD[6]/CAM_STROBE/G
P2[19]
CPU.VIN[0]A_DE/VIN[0]B_HSYNC/UART5_T
XD/I2C[2]_SDA/GP2[0]
CPU.VIN[0]A_D[15]_BD[7]/CAM_SHUTTER/
GP2[20]
DGND
CPU.VIN[0]A_FLD/CAM_D[5]/PATA_CS[0]n/
GP0[20]
CPU.VIN[0]B_CLK/CLKOUT0/GP1[9]
CPU.VIN[0]A_DE/CAM_D[7]/PATA_DIORn/G
P0[18]
CPU.VIN[0]B_FLD/CAM_D[4]/PATA_DIOWn/
GP0[21]
CPU.VIN[0]A_CLK/GP2[2]
CPU.VIN[0]B_DE/CAM_D[6]/PATA_CS[1]n/G
P0[19]
DGND
Ball/
pin #
Supply
Group
Type
Voltage
AC26
G
I/O
1.8V/3.3V
AH17
I/O
1.8V/3.3V
AA25
I/O
1.8V/3.3V
AG17
I/O
1.8V/3.3V
V22
I/O
1.8V/3.3V
AF17
I/O
1.8V/3.3V
AA20
I/O
1.8V/3.3V
AC12
I/O
1.8V/3.3V
AE21
I/O
1.8V/3.3V
AC14
I/O
1.8V/3.3V
AC22
G
I/O
1.8V/3.3V
AE17
AB17
I/O
I/O
1.8V/3.3V
1.8V/3.3V
AD17
I/O
1.8V/3.3V
AB20
AC15
I/O
I/O
1.8V/3.3V
1.8V/3.3V
-
G
August, 2014
Note
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Maya Hardware Manual
v.1.0.3
J2 SO-DIMM Connector
Pin
Pin Name
Internal Connections
J2.158
J2.159
CPU.GPMC_CS[2]n/GPMC_A[24]/GP1[25]
CPU.VIN[0]A_VSYNC/UART5_CTSn/GP2[4]
CPU.GPMC_D[0]/BTMODE[0]
CPU.VIN[0]A_HSYNC/UART5_RTSn/GP2[3]
J2.162
J2.163
J2.164
J2.165
J2.166
J2.167
J2.168
J2.169
GPMC_CS2n
VIN0A_VSYNC/UART5_CT
S
GPMC_D0
VIN0A_HSYNC/UART5_RT
S
GPMC_D1
GPMC_CS0n
GPMC_D2
HDMI_I2C_SCL
GPMC_D3
HDMI_I2C_SDA
DGND
I2C3_SCL
Ball/
pin #
M25
AD20
J2.170
J2.171
GPMC_D4
I2C3_SDA
J2.172
J2.173
GPMC_D5
EMAC1_RGMII_TXD1
J2.174
J2.175
J2.176
J2.177
GPMC_D6
DGND
GPMC_D7
EMAC1_RGMII_TXCTL
J2.178
J2.179
GPMC_WEn
EMAC1_RGMII_TXD0
J2.180
J2.181
GPMC_OEn_REn
EMAC1_RGMII_TXD2
J2.182
GPMC_A0
J2.183
EMAC1_RGMII_RXD0
J2.184
GPMC_A1/SD2_DAT3
CPU.GPMC_D[1]/BTMODE[1]
CPU.GPMC_CS[0]n/GP1[23]
CPU.GPMC_D[2]/BTMODE[2]
CPU.I2C[1]_SCL/HDMI_SCL
CPU.GPMC_D[3]/BTMODE[3]
CPU.I2C[1]_SDA/HDMI_SDA
DGND
CPU.VOUT[1]_B_CB_C[8]/EMAC[1]_MRXD[
4]/VIN[1]A_D[5]/I2C[3]_SCL/GP3[5]
CPU.GPMC_D[4]/BTMODE[4]
CPU.VOUT[1]_B_CB_C[9]/EMAC[1]_MRXD[
5]/VIN[1]A_D[6]/I2C[3]_SDA/GP3[6]
CPU.GPMC_D[5]/BTMODE[5]
CPU.EMAC[0]_MTXD[1]/GPMC_A[8]/UART4
_RXD
CPU.GPMC_D[6]/BTMODE[6]
DGND
CPU.GPMC_D[7]/BTMODE[7]
CPU.EMAC[0]_MTXD[2]/EMAC[1]_RMRXD[
0]/GPMC_A[9]/UART4_TXD
CPU.GPMC_WEn
CPU.EMAC[0]_MTXD[3]/EMAC[1]_RMRXD[
1]/GPMC_A[10]/UART4_CTSn
CPU.GPMC_OEn_REn
CPU.EMAC[0]_MTXD[4]/EMAC[1]_RMRXER
/GPMC_A[11]/UART4_RTSn
CPU.VOUT1_B_CB_C[2]/GPMC_A[0]/VIN[1]
A_D[7]/HDMI_CEC/SPI[2]_D[0]/GP3[30]
CPU.EMAC[0]_MTXD[6]/EMAC[1]_RMTXD[
0]/GPMC_A[13]/UART1_TXD
CPU.SD2_DAT[3]/GPMC_A[1]/GP2[5]
J2.160
J2.161
Supply
Group
Type
Voltage
I/O
I/O
1.8V/3.3V
1.8V/3.3V
U26
AC20
I/O
I/O
1.8V/3.3V
1.8V/3.3V
Y28
T28
V27
AF24
W27
AG24
AH26
I/O
I/O
I/O
I/O
I/O
I/O
G
I/O
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
V26
AA24
I/O
I/O
1.8V/3.3V
1.8V/3.3V
AA28
H25
I/O
I/O
1.8V/3.3V
1.8V/3.3V
U25
V25
H22
I/O
G
I/O
I/O
1.8V/3.3V
U28
H23
O
I/O
1.8V/3.3V
1.8V/3.3V
T27
G23
O
I/O
1.8V/3.3V
1.8V/3.3V
AF28
I/O
1.8V/3.3V
J22
I/O
1.8V/3.3V
J28
I/O
1.8V/3.3V
August, 2014
Note
1.8V/3.3V
1.8V/3.3V
1.8V/3.3V
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v.1.0.3
J2 SO-DIMM Connector
Pin
Pin Name
J2.185
EMAC1_RGMII_TXD3
J2.186
J2.187
DGND
EMAC1_RGMII_TXC
J2.188
GPMC_A2/SD2_DAT2
J2.189
EMAC1_RGMII_RXD2
J2.190
GPMC_A3/SD2_DAT1
J2.191
EMAC_REFCLK
J2.192
J2.193
J2.194
J2.195
J2.196
J2.197
J2.198
J2.199
J2.200
J2.201
J2.202
MDIO_MDIO
DGND
MDIO_MDCLK
ETH_TXETH_CTRD
ETH_TX+
ETH_CTTD
ETH_RXEMAC0_PHY_LED_SPEED
ETH_RX+
EMAC0_PHY_LED_LINK/A
CT
DGND
DGND
J2.203
J2.204
Internal Connections
CPU.EMAC[0]_MTXD[7]/EMAC[1]_RMTXD[
1]/GPMC_A[14]/UART1_CTSn
DGND
CPU.EMAC[0]_MTXD[5]/EMAC[1]_RMCRSD
V/GPMC_A[12]/UART1_RXD
CPU.SD2_DAT[2]_SDRWn/GPMC_A[2]/GP2[
6]
CPU.EMAC[0]_MTXEN/EMAC[1]_RMTXEN/G
PMC_A[15]/UART1_RTSn
CPU.SD2_DAT[1]_SDIRQn/GPMC_A[3]/GP1
[13]
CPU.EMAC_RMREFCLK/TIM2_IO/GP1[10]
Ball/
pin #
H24
Supply
Group
Type
Voltage
I/O
1.8V/3.3V
F27
G
I/O
1.8V/3.3V
K27
I/O
1.8V/3.3V
J23
I/O
1.8V/3.3V
M24
I/O
1.8V/3.3V
J27
I/O
1.8V/3.3V
LAN.MDIO
DGND
LAN.MDC
LAN.TXN
LAN.TXP
LAN.RXN
LAN.LED2/nINTSEL
LAN.RXP
LAN.LED1/REGOFF
16
17
28
29
30
2
31
3
DGND
DGND
-
August, 2014
Note
Available on request (module mount
option). Please refer to section 7.4.1
G
G
G
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Maya Hardware Manual
6.3
Additional notes
6.3.1
EN_BCK_LS
v.1.0.3
J2.97 pin is connected to PMIC GPIO0. This pin is a 5V push-pull signal connected to a
voltage divider circuit via 5K6 /10K resistor, thus providing the 3V3 logical voltage output as
depicted below:
Fig. 8: Simplified schematics of EN_BCK2_LS internal pin
configuration
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Maya Hardware Manual
7
v.1.0.3
Peripheral interfaces
MAYA modules implement a number of peripheral interfaces
through the SO-DIMM connector. The following notes apply to
those interfaces:
● Some interfaces/signals are available only with/without
certain configuration options of the MAYA module. Each
signal’s availability is noted in the “Notes” column on the
table of each interface.
The signals for each interface are described in the related
tables. The following notes summarize the column headers for
these tables:
● “Pin name” – The name of each microprocessor signal
● “Conn. Pin” – The pin number on the module connectors
● “Function” – Signal description
● “Notes” – This column summarizes configuration
requirements and recommendations for each signal.
7.1
Digital Video Output (DVO)
MAYA provides a Digital Video Output interfaces, VOUT0 (up to
24 bit), with support to YCbCr/RGB formats at 1080p@60.
7.1.1
VOUT0
The following table describes the interface signals:
Pin name
Conn.
Pin
Function
Notes
VOUT[0]_VSYNC
J2.65
Vertical Sync output
VOUT[0]_CLK
J2.61
Clock output
VOUT[0]_AVID
J2.67
Active video output
VOUT[0]_HSYNC
J2.63
Horizontal Sync
output
VOUT[0]_B_CB_C[2]
J2.48
VOUT[0]_B_CB_C[3]
J2.50
Video Output Data. These signals
represent the 8 MSBs of B/CB/C video
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Field ID output
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Maya Hardware Manual
Pin name
7.2
v.1.0.3
Conn.
Pin
VOUT[0]_B_CB_C[4]
J2.52
VOUT[0]_B_CB_C[5]
J2.54
VOUT[0]_B_CB_C[6]
J2.56
VOUT[0]_B_CB_C[7]
J2.58
VOUT[0]_B_CB_C[8]
J2.60
VOUT[0]_B_CB_C[9]
J2.62
VOUT[0]_G_Y_YC[2]
J2.66
VOUT[0]_G_Y_YC[3]
J2.68
VOUT[0]_G_Y_YC[4]
J2.70
VOUT[0]_G_Y_YC[5]
J2.72
VOUT[0]_G_Y_YC[6]
J2.74
VOUT[0]_G_Y_YC[7]
J2.76
VOUT[0]_G_Y_YC[8]
J2.78
VOUT[0]_G_Y_YC[9]
J2.80
VOUT[0]_R_CR[2]
J2.73
VOUT[0]_R_CR[3]
J2.75
VOUT[0]_R_CR[4]
J2.77
VOUT[0]_R_CR[5]
J2.79
VOUT[0]_R_CR[6]
J2.81
VOUT[0]_R_CR[7]
J2.83
VOUT[0]_R_CR[8]
J2.85
VOUT[0]_R_CR[9]
J2.87
Function
Notes
data. For RGB mode they are blue data
bits, for YUV444 mode they are Cb
(Chroma) data bits, for Y/C mode they
are multiplexed Cb/Cr (Chroma) data bits
and for BT.656 mode they are unused.
Video Output Data. These signals
represent the 8 MSBs of G/Y/YC video
data. For RGB mode they are green data
bits, for YUV444 mode they are Y data
bits, for Y/C mode they are Y (Luma) data
bits and for BT.656 mode they are
multiplexed Y/Cb/Cr (Luma and Chroma)
data bits.
Video Output Data. These signals
represent the 8 MSBs of R/CR video data.
For RGB mode they are red data bits, for
YUV444 mode they are Cr (Chroma) data
bits, for Y/C mode and BT.656 modes
they are unused.
Analog SDTV out
MAYA provides a standard definition Composite (NTSC/PAL) TV
out channel. The signal meets all requirements defined in
ITU-R BT 470.6.
The following table describes the interface signal:
August, 2014
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Maya Hardware Manual
Pin name
TV_OUT1
7.3
v.1.0.3
Conn.
Pin
J2.18
Function
Notes
Composite
Amplifier Output
Configured as
“Normal mode”
(internal amplifier
used). This pin drives
the 75-Ω TV
load.
Digital Video Input ports
The HD Video Processing Subsystem supports two
independently configurable external video input capture ports
(VIP) up to 165MHz. MAYA enables one video capture port
(VIN0), supporting:
● one scaler capable of both up and down scaling of one
non-multiplexed input stream
● one programmable color space conversion to convert
between 24-bit RGB data and YCbCr data.
● data storage in RGB, 422, and 420 formats, with chroma
down-sampling (422 to 420) for any non-multiplexed input
data. The chroma down-sampling for multiplexed streams is
done as memory to memory operations outside of HDVPSS on
an individual frame data.
The HDVPSS VIP instance 0 is configured as a 16-bit interface.
7.3.1
VIN0
The following table describes the interface signals:
Pin name
Conn.
Pin
Function
VIN[0]A_CLK
J2.155
Input clock for 8-bit,
16-bit, or 24-bit Port A
video capture.
VIN[0]A_FLD
J2.146
Discrete field
identification signal
for Port A RGB
capture mode or
YCbCr capture without
embedded syncs
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Notes
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Maya Hardware Manual
Pin name
v.1.0.3
Conn.
Pin
Function
Notes
(“BT.601” modes).
VIN[0]A_HSYNC
J2.161
Discrete horizontal
synchronization signal
for Port A RGB
capture mode or
YCbCr capture without
embedded syncs
(“BT.601” modes).
VIN[0]A_VSYNC
J2.159
Discrete vertical
synchronization signal
for Port A RGB
capture mode or
YCbCr capture without
embedded syncs
(“BT.601” modes).
VIN[0]A_DE
J2.148
Discrete data valid
signal for Port A RGB
capture mode or
YcbCr capture without
embedded syncs
("BT.601" modes).
VIN[0]A_D[0]
J2.115
VIN[0]A_D[1]
J2.117
VIN[0]A_D[2]
J2.119
VIN[0]A_D[3]
J2.123
VIN[0]A_D[4]
J2.125
VIN[0]A_D[5]
J2.127
VIN[0]A_D[6]
J2.129
VIN[0]A_D[7]
J2.131
VIN[0]A_D[8]_BD[0]
J2.133
VIN[0]A_D[9]_BD[1]
J2.135
VIN[0]A_D[10]_BD[2]
J2.137
VIN[0]A_D[11]_BD[3]
J2.141
VIN[0]A_D[12]_BD[4]
J2.143
VIN[0]A_D[13]_BD[5]
J2.145
VIN[0]A_D[14]_BD[6]
J2.147
VIN[0]A_D[15]_BD[7]
J2.149
Data inputs. For 16-bit capture, D[7:0]
are Cb/Cr and [15:8] are Y Port A inputs.
For 8-bit capture, D[7:0] are Port A YCbCr
data inputs and D[15:8] are Port B YCbCr
data inputs. For RGB capture, D[23:16]
are R, D[15:8] are G, and BD[7:0] are B
data inputs.
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7.4
v.1.0.3
Ethernet ports
The DM814x/AM387x 3PSW (Three Port Switch) Ethernet
Subsystem provides ethernet packet communication and can be
configured as an ethernet switch. It provides the gigabit media
independent interface (G/MII), reduced gigabit media
independent interface (RGMII), reduced media independent
interface (RMII), the management data input output (MDIO) for
physical layer device (PHY) management. MAYA provides two
Fast Ethernet ports, one with on-board PHY, and one RMII
only.
7.4.1
EMAC_RMREFCLK
EMAC_REFCLK signal is the reference clock for the internal
PHY (SMSC LAN8710) connected to EMAC[0] configured in
RMII mode. This signal is driven by the CPU and can be
optionally routed to J1.91 through a mount option. The
CPU.EMAC_RMREFCLK signal is internally split in two lines,
one connected to the internal PHY and the other routed to the
J1 connector; both lines are terminated with 22 Ω resistors. For
more flexibility on using both EMAC[0] and EMAC[1]
interfaces, this signal has been routed to the J1 connector
providing the following configuration options:
● generated internally (default configuration) and routed
externally for driving an external RMII PHY on the second
MAC (EMAC[1]) at 10/100 Mbit. In this case it is possible to
avoid the cost of an external crystal or oscillator.
● generated by an external PHY mounted on the carrier board
(connected to EMAC[1]) and routed internally to the internal
PHY and CPU. In some cases this configuration could be
preferred.
7.4.2
Ethernet 10/100
On-board Ethernet PHY provides interface signals required to
implement the 10/100 Ethernet port. It is connected to
processor EMAC0 controller through RMII interface.
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The following table describes the interface signals:
Pin name
7.4.3
Conn. Function
Pin
Notes
EMAC0_PHY_LED_LINK/A
CT
J2.202 Link activity LED
Indication.
This pin is driven
active when a valid
link is detected and
blinks when activity
is detected.
EMAC0_PHY_LED_SPEED
J2.200 Link Speed LED
Indication.
This pin is driven
active when the
operating speed is
100Mbps. It is
inactive when the
operating speed is
10Mbps or during
line isolation.
ETH_CTTD
J2.198 Tx Center Tap
ETH_CTRD
J2.196 Rx Center Tap
ETH_TX-
J2.195 Transmit Negative
Channel
ETH_TX+
J2.197 Transmit Positive
Channel
ETH_RX-
J2.199 Receive Negative
Channel
ETH_RX+
J2.201 Receive Positive
Channel
EMAC_RMREFCLK
J2.191 RMII Reference
Clock
Fast Ethernet EMAC1
MAYA provides a 10/100 Mbps Ethernet interface connected to
processor EMAC1 controller through RMII interface. When
required, an external PHY must be mounted on the carrier
board.
The following table describes the interface signals:
Pin name
EMAC_RMREFCLK
Conn. Function
Pin
Notes
J2.191 RMII Reference
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Pin name
v.1.0.3
Conn. Function
Pin
Notes
Clock
EMAC[1]_RMCRSDV
J2.187 RMII Carrier
Sense input
EMAC[1]_RMRXD[1]
J2.179 RMII Receive Data
J2.177 [1:0]
EMAC[1]_RMRXD[0]
EMAC[1]_RMRXER
J2.181 RMII Receive Data
Error input
EMAC[1]_RMTXD[1]
J2.185 RMII Transmit
J2.183 Data [1:0]
EMAC[1]_RMTXD[0]
EMAC[1]_RMTXEN
7.5
J2.189 RMII Transmit
Data Enable
output
CAN ports
MAYA provides two DCAN interfaces (DCAN0 and DCAN1) for
supporting distributed realtime control with a high level of
security. The DCAN interfaces implement the CAN protocol
version 2.0 part A, B and supports bit rates up to 1 Mbit/s.
7.5.1
DCAN0
When required, DCAN0 must be connected to an external PHY.
The following table describes the interface signals:
Pin name
7.5.2
Conn. Function
Pin
DCAN0_RX
J2.113
Receive data pin
DCAN0_TX
J2.111
Transmit data pin
Notes
DCAN1
When required, DCAN1 must be connected to an external PHY.
The following table describes the interface signals:
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Pin name
7.6
v.1.0.3
Conn. Function
Pin
DCAN1_RX
J2.102
Receive data pin
DCAN1_TX
J2.104
Transmit data pin
Notes
UARTs
Three UART ports are routed to MAYA connectors. UART0
provides full Modem Control Signals, while UART3 and UART5
are 4-wire interfaces. Each port can be programmed separately
and can operate in UART, IrDA or CIR modes.
7.6.1
UART0
The following table describes the interface signals:
Pin name
Conn. Function
Pin
Note
UART0_RXD
J2.98
Receive Data
Functions as IrDA
receive input in IrDA
modes and CIR
receive input in CIR
mode
UART0_TXD
J2.100
Transmit Data
Functions as CIR
transmit in CIR mode
UART0_RTSn
J2.102
Request To Send
Functions as transmit
data output in IrDA
modes
UART0_CTSn
J2.104
Clear To Send
Functions as SD
transceiver control
output in IrDA and
CIR modes
UART0_DTRn
J2.112
Data Terminal
Ready
This pin is
multiplexed with
UART3_CTSn signal
UART0_DSRn
J2.110
Data Set Ready
This pin is
multiplexed with
UART3_TXD signal
UART0_DCDn
J2.108
Data Carrier
Detect
This pin is
multiplexed with
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Pin name
v.1.0.3
Conn. Function
Pin
Note
UART3_RXD signal
UART0_RIN
7.6.2
J2.106
Ring indicator
This pin is
multiplexed with
UART3_RTSn signal
UART3
The following table describes the interface signals:
Pin name
7.6.3
Conn. Function
Pin
Notes
UART3_RXD
J2.108
Receive Data
Functions as IrDA
receive input in IrDA
modes and CIR
receive input in CIR
mode.
UART3_TXD
J2.110
Transmit Data
Functions as CIR
transmit in CIR
mode.
UART3_RTSn
J2.106
Request To Send
Functions as transmit
data output in IrDA
modes
UART3_CTSn
J2.112
Clear To Send
Functions as SD
transceiver control
output in IrDA and
CIR modes.
UART5
The following table describes the interface signals:
Pin name
UART5_RXD
Conn. Function
Pin
J2.146
Receive Data
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Notes
Also available as
alternative function
on pin J2.25 and
J2.130. Functions as
IrDA receive input in
IrDA modes and CIR
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Pin name
v.1.0.3
Conn. Function
Pin
Notes
receive input in CIR
mode.
7.7
UART5_TXD
J2.109
Transmit Data
Also available as
alternative function
on pin J2.134 and
J2.148. Functions as
CIR transmit in CIR
mode.
UART5_RTSn
J2.161
Request To Send
Functions as transmit
data output in IrDA
modes
UART5_CTSn
J2.159
Clear To Send
Functions as SD
transceiver control
output in IrDA and
CIR modes.
MMC/SD channels
Two standard MMC/SD/SDIO interfaces are available on MAYA
module. The processor includes 3 MMC/SD/SDIO Controllers
which are compliant with MMC V4.3, Secure Digital Part 1
Physical Layer Specification V2.00 and Secure Digital Input
Output (SDIO) V2.00 specifications. High capacity SD cards
(SDHC) are supported.
7.7.1
MMC/SD/SDIO0
MMC/SD1 can be configured as 1-bit, 4-bit or 8-bit mode.
The following table describes the interface signals:
Pin name
Conn. Function
Pin
SD0_CLK
J2.44
Clock output
SD0_CMD
J2.42
Command output
SD0_SDCD
J2.104
Card detect input
SD0_DAT[0]
J2.34
Data bit 0
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Notes
Functions as single
data bit for 1-bit SD
mode.
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Pin name
7.7.2
v.1.0.3
Conn. Function
Pin
Notes
SD0_DAT[1]
J2.36
Data bit 1
Functions as an IRQ
input for 1-bit SD
mode.
SD0_DAT[2]
J2.38
Data bit 2
Functions as a Read
Wait input for 1-bit
SD mode.
SD0_DAT[3]
J2.40
Data bit 3
SD0_DAT[4]
J2.120
Data bit 4
Multiplexed with
MCA1 interface
SD0_DAT[5]
J2.122
Data bit 5
Multiplexed with
MCA1 interface
SD0_DAT[6]
J2.130
Data bit 6
Multiplexed with
MCA2 interface
SD0_DAT[7]
J2.134
Data bit 7
Multiplexed with
MCA2 interface
MMC/SD/SDIO1
MMC/SD1 can be configured as 1-bit, 4-bit or 8-bit mode.
Please note that 8-bit mode can be used only when MMC/SD0
is not enabled.
The following table describes the interface signals:
Pin name
Conn. Function
Pin
Notes
SD1_CLK
J2.32
Clock output
SD1_CMD
J2.30
Command output Also available as
alternative function
on pin J2.42.
SD1_DAT[0]
J2.20
Data bit 0
Functions as single
data bit for 1-bit SD
mode.
SD1_DAT[1]
J2.22
Data bit 1
Functions as an IRQ
input for 1-bit SD
mode.
SD1_DAT[2]
J2.24
Data bit 2
Functions as a Read
Wait input for 1-bit
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Pin name
v.1.0.3
Conn. Function
Pin
Notes
SD mode.
7.8
SD1_DAT[3]
J2.26
Data bit 3
SD1_DAT[4]
J2.34
Data bit 4
SD1_DAT[5]
J2.36
Data bit 5
SD1_DAT[6]
J2.38
Data bit 6
SD1_DAT[7]
J2.40
Data bit 7
USB ports
MAYA provides two USB 2.0 On-The-Go (OTG) ports. The
processor features two USB modules where each USB module
is built around a USB OTG controller and PHY. Each module
supports:
● USB Device operations at High Speed (Up to 480 Mb/s) or
Full Speed (Up to 12 Mb/s).
● USB Host operations at High Speed (Up to 480 Mb/s), Full
Speed (Up to 12 Mb/s) and Low Speed (Up to 1.5Mb/s).
● USB 2.0 extensions for OTG Session Request Protocol (SRP).
● USB 2.0 extensions for OTG Host Request Protocol (HRP).
● All USB standard transfer types (control, bulk, interrupt, and
isochronous) as both a USB Host as well as a USB Device.
7.8.1
USB0
The following table describes the interface signals:
Pin name
Conn. Function
Pin
USB0_DP
J2.84
USB0_DM
J2.86
USB0_ID
J2.93
OTG identification
input.
USB0_CE
J2.95
USB0 charger
enable
Notes
Bidirectional data
differential signal
pair (plus/minus)
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When the USB0 PHY
is powered down,
this pin should be
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Pin name
v.1.0.3
Conn. Function
Pin
Notes
left unconnected
7.8.2
USB0_VBUSIN
J2.88
5-V VBUS
Senses the level of
comparator input. the USB VBUS.
Should connect
directly to the USB
VBUS voltage.
USB0_DRVVBUS
J2.91
Used by the USB0
Controller to
enable the
external VBUS
charge pump.
USB1
The following table describes the interface signals:
Pin name
7.9
Conn. Function
Pin
USB1_DP
J2.92
USB1_DM
J2.94
USB1_ID
J2.99
USB1_CE
J2.101
Notes
Bidirectional data
differential signal
pair (plus/minus)
OTG identification
input.
USB1 charger
enable
When the USB1 PHY
is powered down,
this pin should be
left unconnected
USB1_VBUSIN
J2.90
5-V VBUS
Senses the level of
comparator input. the USB VBUS.
Should connect
directly to the USB
VBUS voltage.
USB1_DRVVBUS
J2.97
Used by the USB1
Controller to
enable the
external VBUS
charge pump.
SPI buses
Two SPI channels are available on MAYA. Each port has a
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maximum supported frequency of 48 MHz and provides up to 4
chip selects. Communication parameters (frequency, polarity,
phase) are programmable.
7.9.1
SPI0
SPI0 provides 4 chip select signals. The following table
describes the interface signals:
Connector Pin
SPI[0]_SCLK
7.9.2
Pin
Function
name
J2.55
SPI[0]_SCS[3]
J2.108
SPI[0]_SCS[2]
J2.110
SPI[0]_SCS[1]
J2.59
SPI[0]_SCS[0]
J2.57
SPI[0]_D[1]
J2.49
SPI[0]_D[0]
J2.51
Notes
SPI clock
SPI chip selects
SPI Data I/O. Can be
configured as either
MISO or MOSI.
SPI3
SPI3 provides 1 chip select signal. The following table
describes the interface signals:
Connector Pin
7.10
Pin
Function
name
SPI[3]_SCLK
J2.140
SPI clock
SPI[3]_SCS[1]
J2.138
SPI chip select
SPI[3]_D[1]
J2.142
SPI[3]_D[0]
J2.144
SPI Data I/O. Can be
configured as either
MISO or MOSI.
Notes
Also available as
alternative
function on pin
J2.67.
I2C buses
Two I2C channels are available on MAYA to provide an
interface to other devices compliant with Philips
Semiconductors Inter-IC bus (I2C-bus™) specification version
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2.1. External components attached to this 2-wire serial bus can
transmit/receive 8-bit data to/from the device through the I2C
module. The I2C ports support standard and fast modes from
10 - 400 Kbps (no fail-safe I/O buffers).
A third I2C channel (I2C0) is used for the internal connection
between CPU and PMIC (please refer to Section 5.2).
7.10.1
I2C1
The following table describes the interface signals:
Connector Pin
7.10.2
Pin
Function
name
Notes
I2C[1]_SCL
J2.165
I2C2 Clock
The line is
internally
connected to
pull-up resistor
I2C[1]_SDA
J2.167
I2C2 Data I/O
The line is
internally
connected to
pull-up resistor
I2C3
The following table describes the interface signals:
Connector Pin
7.11
Pin
Function
name
Notes
I2C[3]_SCL
J2.169
I2C3 Clock
The line is
internally
connected to
pull-up resistor
I2C[3]_SDA
J2.171
I2C3 Data I/O
The line is
internally
connected to
pull-up resistor
Audio interfaces
The multichannel audio serial port (McASP) functions as a
general-purpose audio serial port optimized for the needs of
multichannel audio applications. The McASP is useful for
time-division multiplexed (TDM) stream, Inter-Integrated
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Sound (I2S) protocols, and inter-component digital audio
interface transmission (DIT). MAYA provides two McASP
interfaces with up to 2 serial data pins each.
7.11.1
McASP1
The following table describes the interface signals:
Connector Pin
7.11.2
Pin
Function
name
MCA[1]_ACLKX
J2.116
McASP1 Transmit Bit
Clock I/O
MCA[1]_AFSX
J2.118
McASP1 Transmit
Frame Sync I/O
MCA[1]_AXR[0]
J2.120
McASP1
Transmit/Receive
Data I/Os
MCA[1]_AXR[1]
J2.122
McASP1
Transmit/Receive
Data I/Os
Notes
McASP2
The following table describes the interface signals:
Connector Pin
7.12
Pin
Function
name
MCA[2]_ACLKX
J2.126
McASP2 Transmit Bit
Clock I/O
MCA[2]_AFSX
J2.128
McASP2 Transmit
Frame Sync I/O
MCA[2]_AXR[0]
J2.130
McASP2
Transmit/Receive
Data I/Os
MCA[2]_AXR[1]
J2.134
McASP2
Transmit/Receive
Data I/Os
Notes
GPIOs
The GPIO peripheral provides general-purpose pins that can be
configured as either inputs or outputs, for connections to
external devices. In addition, the GPIO peripheral can produce
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CPU interrupts in different interrupt generation modes. The
device contains four GPIO modules and each GPIO module is
made up of 32 identical channels.
The device GPIO peripheral supports up to 128 1.8-V/3.3-V
GPIO pins, GP0[0:31], GP1[0:31], GP2[0:31], and GP3[0:31].
Each channel must be properly configured, since GPIO signals
are multiplexed with other interfaces signals. For more
information on how to configure and use GPIOs, please refer to
http://processors.wiki.ti.com/index.php/TI811X_PSP_GPIO_Driv
er_User_Guide.
7.13
Local Bus
The general-purpose memory controller (GPMC) is an unified
memory controller dedicated to interfacing external memory
devices:
● Asynchronous SRAM-like memories and application-specific
integrated circuit (ASIC) devices
● Asynchronous, synchronous, and page mode (only available
in non-multiplexed mode) burst NOR flash devices
● NAND Flash (with BCH and Hamming Error Code Detection)
● Pseudo-SRAM devices
The GPMC includes flexible asynchronous protocol control to
interface to SRAM-like memories and custom logic (FPGA,
CPLD, ASICs, etc.).
MAYA provides a subset of the GPMC bus pins:
● 2 chip selects
● 4-bit wide address bus
● 8-bit wide data bus
The following table describes the interface signals:
Connector Pin
Pin
Function
name
GPMC_CS[2]n
J2.158
GPMC Chip Select #2
GPMC_CS[0]n
J2.163
GPMC Chip Select #0
GPMC_WEn
J2.178
GPMC Write Enable
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Connector Pin
v.1.0.3
Pin
Function
name
GPMC_OEn_REn
J2.180
GPMC_A[3]
J2.190
GPMC_A[2]
J2.188
GPMC_A[1]
J2.184
GPMC_A[0]
J2.182
GPMC_D[7]
J2.176
GPMC_D[6]
J2.174
GPMC_D[5]
J2.172
GPMC_D[4]
J2.170
GPMC_D[3]
J2.166
GPMC_D[2]
J2.164
GPMC_D[1]
J2.162
GPMC_D[0]
J2.160
Notes
GPMC Output Enable
GPMC Address bits
GPMC Demuxed data
I/Os
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8
8.1
v.1.0.3
Operational characteristics
Maximum ratings
This section will be completed in a future version of this
manual.
Parameter
Main power supply voltage
8.2
Min
Typ
3.1
3.3
Max
Unit
V
Recommended ratings
This section will be completed in a future version of this
manual.
Parameter
Main power supply voltage
8.3
Min
Typ
Max
Unit
-
3.3
-
V
Power consumption
Providing theoretical maximum power consumption value
would be useless for the majority of system designers building
their application upon MAYA module because, in most cases,
this would lead to an oversized power supply unit.
Several configurations have been tested in order to provide
figures that are measured on real-world use cases instead.
Please note that MAYA platform is so flexible that it is virtually
impossible to test for all possible configurations and
applications on the market. The use cases here presented
should cover most of real-world scenarios. However actual
customer application might require more power than values
reported here. Generally speaking, application specific
requirements have to be taken into consideration in order to
size power supply unit and to implement thermal management
properly.
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8.3.1
v.1.0.3
Set 1
Measurements have been performed on the following platform:
● NAON SOM (DM8148 model)
● Carrier board: NAONEVB-Lite
● System software: NELK 1.0.0
● Power monitor: INA226 (reference U20 of [[NAONEVB-Lite]]
schematics).
● ARM Cortex-A8 frequency: 600 MHz
● SDRAM size: 512 MByte
● SDRAM frequency: 400 MHz
● HDVICP2 frequency: 306 MHz
8.3.2
Use cases
Checkpoint
Input
Voltage
Shunt
Voltage
Current
Power
Consumpion
Linux prompt
(M3 unloaded)
3266 mV
8 mV
779 mA
2550 mW
Linux prompt
(M3 loaded)
3261 mV
10 mV
1040 mA
3400 mW
cpuBurnA8 (M3
Loaded)
3258 mV
12 mV
1235 mA
3900 mW
decode &
display H264
1080p60 on
HDMI
3258 mV
12 mV
1219 mA
3975 mW
decode &
display H264
1080p60 +
cpuBurnA8
3255 mV
14 mV
1352 mA
4450 mW
Additional notes and reference:
● M3 Unloaded means that the two Cortex-M3 firmware has
not yet been started
● For decode/display test the sample application included in
the TI EZSDK has been used
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● Cpuburn heavily uses Cortex-A8 and Neon to maximize
power consumption and heat spreading. See the Debian
package information (burnCortexA8.s) for further
information
● Please note that shunt voltage value is rounded
● Please note that, although the NAON module has been used
during these tests, usage of the MAYA module would lead to
comparable results.
8.4
Heat Dissipation
For more information on thermal management, please refer to
http://wiki.dave.eu/index.php/Thermal_management_%28Naon
%29.
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9
v.1.0.3
Application notes
Please refer to the following documents available on DAVE
Embedded Systems Developers Wiki:
Document
Location
Integration Guide
http://wiki.dave.eu/index.php/Inte
gration_guide_%28Maya%29
Carrier board design
guidelines
http://wiki.dave.eu/index.php/Carr
ier_board_design_guidelines_
%28SOM%29
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