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LPDDR4 Interface Electrical Validation
Measure the analog signal characteristics; trtf, Vmin/max, jitter,
eye size, crossover, strobe/clock alignment, etc.
I/O Training / Calibration
 LPDDR4 Interface adds several calibration / training schemes to
optimize the bus timing for high speed operation
– Write Training
– Unmatched DQS/DQ path in LPDDR4 SDRAM
– DQS2DQ training using command based FIFO WR/RD with user pattern
– Write Leveling
– Adjust Clock to DQS timing skew to de-skew flight time differences between
byte lanes
– Read Calibration
– Train DQ/DQS for Read Cycles by driving the contents of Mode Register in
the DQ and DMI I/O
– Ron
– Separate pull-down (or terminator) calibration using RZQ and pull-up
calibration to set VOH
– CA bus training
– Centers the CA eye to reference clock edge
– Vref training for CA-bus and DQ-Bus
– No external Vref, internal Vref requires training
Address Command Bus

CA bus in LPDDR4 is completely revamped
(LPDDR2/3: 10 CA + CS+ CK  LPDDR4: 2x(6 CA + CS + CK)

CA-bus is Single Data Rate and sampled on rising edge of clock signal

Commands are 2 Clock Cycles and timings are counted from/to the rising clock edge of
the second command part.

Read and Write Latencies are counted from the second clock edge of the CAS-2
command

CS is now Active High and indicated the beginning of the command

Some command pairs are tied and both must be issued in a consecutive manner.

CKE asynchronous for Power Down control
R1
CK
CA
CS
R2
R1
R2
Vcent
 DDR4/LPDDR4 bus does not include (externally accessible) VREF.
 Vcent_CAx is the Voltage at which the cumulative eye of the pin CAx
is widest
 Vcent_CA(pin_mid) is defined as the middle between the largest and
smallest Vcent_CA within the group.
 Vcent_CA(pin_mid) is the best available estimate for the internal
VREF (after training), that is accessible at the pins.
Mask-Based Timing and Voltage Definition
 All voltages referenced to Vcent
 All timing referenced to rising clock edge
 Mask is centered around Vcent and clock/strobe edge
Conditions must be met cumulatively per group over time
Read / Write Timing
Read
Write
Signal Access
Probing
Modelling
Probe Point
Interposer
Discrete
Soc
LPDDR4
PCB
Probe Point
Interposer
PoP
LPDDR4
Soc
PCB

System level modelling is performed to make sure that the system can handle
the introduction of the interposer in the channel path

In order to provide optimum performance special structures are designed into
the interposer to provide a linear response

2 port and 4 port S-parameter models that represent the probing system are
available for simulation purposes

Probing all signals simultaneous is not cost effective, only a few signals
probed at a time.
– Loaded Models represent the case when the probe connected
– Unloaded models represent the case when the probe is not connected
Simulation  Lab Measurement Results
Analysis and correlation
source waveforms
tr0 / csv file*
SPICE sw
Simulation Eye Diagram
Wfm file
70000 scope
DPOJET Eye Diagram
Lab Correlation with Tektronix shows the simulation results can be trusted
Peak to peak 0.8 V
Simulation
Measurement
Peak to peak 0.8 V
Eye
Height
Mean
CDNS Results
544 mV
Tek Results
515.26 mV
Probing
Interposer
Probe Point
Interposer
Discrete
Soc
LPDDR4
PCB
Probe Point
Interposer
PoP
LPDDR4
Soc
PCB
 An Interposer provides access to the signals for characterization and
Debug
 Due to the density of the packages only a subset of all the signals are
available for probing
 Custom probing solutions can be built if needed for specific
applications
Interposers Solutions
 Trade off between KoV, Signal Access and Signal Quality
Solder Down
Interposer with
Edge Style Probing
Socketed interposer
for PoP packages
Solder Down
interposer with
Probe Pads
Socketed interposer
with Probe Pads
De-embedding
Probe Point
Interposer
Soc
LPDDR4
PCB
 In order to remove the effects of the Interposer/Probe, De-embedding
must be considered.
 S-Parameters of the objects that need to be de-embedded are
required for de-embedding
 S-Parameters for the Interposer will be made available and can be
used to create De-embed filters.
 S-parameters can be extracted
– From the 3D models by simulation
– Measuring on a real sample using a VNA or TDR method on sampling scope
De-embed Filter
 Model the probing setup Use the S-Parameter Models to
generate Filters
 Supports different blocks in the signal path including
– Interposer
– Probe / tip
– RF Switch
Midbus probing
Before and After De-embedding
Probe Point
Soc
LPDDR4
PCB
Interposer Availability
Technology Package / Form Factor
DDR2
DDR3
DDR4
LPDDR
LPDDR2
LPDDR3
LPDDR4
GDDR5
Socketed – 60 Ball/ 84 Ball
Solder-down – 60 Ball/ 84 Ball
Socketed – 78 Ball/ 96 Ball
Solder-down – 78 Ball/ 96 Ball
Edge Probe – 78 Ball/ 96 Ball
DIMM Interposer for MSO
SO-DIMM Interposer for MSO
Socketed – 78 Ball/ 96 Ball
Edge Probe – 78 Ball/ 96 Ball
Edge Probe – 144 Ball
DIMM Interposer for MSO
Socketed – 60ball
Socketed – 136 ball/168 ball/216 ball/240 ball
Socketed – 216 ball
Solder-down – 178 ball
Socketed – 272 ball
Solder – down – 272 ball
Socketed – 170 ball
Solder – down – 170 ball
TriMode Probing

TriMode, with a single probe-DUT connection, allows:
– Traditional differential measurements: V+ to V– Independent single ended measurements on either input
–
–
V+ with respect to ground
V- with respect to ground
– Direct common mode measurements: ((V+) + (V-))/2 with respect to
ground

Many standards require both differential and single-ended voltage limit
measurements. Requires two separate probes – Until Now!
Before and After
Before TriMode Probing
After TriMode Probing
1 Probe for Differential
2 Probes for SE and Common Mode
or
1 Probe Soldered and Re-soldered 3 times
2 Probes for Common Mode
1 Probe and 1 setup for
Differential, SE and Common Mode
Signal Acquisition and Analysis
Triggering, ASM, DDRA and DPOJET
Oscilloscope Bandwidth Requirement
Memory Technology
Speed
Max slew rate
DDR
DDR2
DDR2
DDR3
DDR3
DDR3L
LPDDR3
DDR4
LPDDR4
all rates
to 400MT/s
to 800MT/s
to 1600MT/s
to 2400MT/s
to 1600MT/s
to 1600MT/s
to 3200MT/s
to 4267MT/s
5
5
5
10
12
12
8
18
18
Typical V swing
1.8
1.25
1.25
1
1
0.9
0.6
0.8
0.3
20-80 risetime (ps)
216
150
150
60
50
45
45
27
27
Equivalent Edge BW
1.9
2.7
2.7
6.7
8.0
8.9
8.9
15.0
15.0
Recommended Scope BW
(Max Performance)
Recommended Scope BW
(Typ Performance)
2.5
3.5
4.0
12.5
12.5
12.5
12.5
16
16
2.5
2.5
3.5
8.0
12.5
12.5
12.5
12.5
16




Highest Accuracy on Faster Slew rates
Slew Rates are about 80% of the Max Spec
DDR3L, DDR4 LPDDR3 and LPDDR4 is supported only on DSA/MSO/DPO70000C/D models only
LPDDR4 is a separate license
www.tektronix.com/ddr
Debug and Analysis Tools
 Tektronix Oscilloscopes come with several tools
that aid in debug of Memory Interfaces
–
–
–
–
–
–
DPOJET advanced Jitter analysis toolkit
PinPoint Triggering
Visual Trigger
Mask Testing
Advanced Search and Mark
DDRA
Pinpoint Triggering

Fastest way to solve sophisticated Memory signaling issues
– Superior real-time insight into the complex signaling
– DPX (FastAcq) and Pinpoint Triggering gives you “the power to see what others can’t”
– FastAcq shows any disparities on signals, like infrequent glitch’s
Visual Trigger

8 customizable zones to quality HW trigger setup

Option VET required

Areas may be resized or moved after creation

Four standard shapes supported (rectangle, triangle, hexagon, trapezoid)

Custom shapes may be built from templates up to 48 verticies

Areas are “keep in” or “keep out”

Apply to either trigA or trigB, whichever is last

Used to
–
–
–
–
Separate Read bursts from Write Bursts
Separate ranks
Look for pattern dependencies
Enable persistence eye diagrams
DQ Pattern Detection
Trigger with Persistence
Advanced Search and Mark



Scans entire acquisition for multiple occurrences of an event and marks each
occurrence
Extends across live data, stored as well as math waveforms.
Integrated with Trigger function and extends it
– Marks all events in the current acquisition that match the trigger setup
 Integrated with DDRA
– DDRA uses ASM to mark all the events of interest and the marked events are
used as gates for analysis by DDRA
DPOJET Analysis Overview
Jitter
Eye
Timing
Period
Link Analysis (SDLA)
Live Analog
Live Digital
Reference Memory
Waveform
Math
Results
Acquire
DPOJET works with
the following data
sources
- Analog
- Digital
- Math
- Reference
Transform
Data from a data
source can be post
processed to achieve
visibility at multiple
test points or after
math transformations
Measure / Analyze
Reporting
Measure
simultaneously across
multiple test points
and measurement
configurations
Plot and zoom on
worst case to provide
deeper levels of
insight
Get a test report with
measurement results,
pass fail limits, plots,
user comments and
instrument
configurations.
Supported Standards

Comprehensive coverage of multiple JEDEC memory standards in a single package

Support for all the JEDEC defined speed grades in each standard as well custom
settings
Memory Type
DDR
DDR2
DDR3
DDR3L
DDR4
LPDDR
LPDDR2
LPDDR3
GDDR5
JEDEC Specification
JESD79E
JESD79-2F
JESD79- 3F
JESD79-3-1
JESD79-4
JESD209A
JESD209-2E
JESD209-3
JESD212
Test Setup and Configuration

All the tests are logically grouped based on the input source requirement
–
–
–
–
READ
WRITE
CLOCK
ADDR/CMD

Quickly set up the test configuration by selecting a complete group or individual tests
for targeted analysis.

Flexible input source requirement, inputs are not hardwired to a particular Oscilloscope
channel.
Burst Detection


Read / Write bursts are automatically detected for
analysis purposes
Several different techniques are used for Read/Write
Burst Separation
– DQ/DQS phase alignment: DQ and DQS have different
phase relationship in Read and Write bursts
– CS, Latency + DQ/DQS Phase Alignment: CS is used
to quality the occurrence of a burst, followed by DQ/DS
phase relationship to distinguish between Read/Write
– Logic State + Burst latency: The command bus probed
using the digital channels on the MSO is used to
identify Read/Write commands on the command bus
are quality and distinguish Read and Write bursts

Options are provided to adjust the levels to improve
burst detection in systems with lower signal integrity
Read / Write separation
READ
WRITE
Reports

Analysis results are compiled into an
HTML report enabling easy report
management and distribution.

Report includes
–
–
–
–
–
Measurement results
Pass/Fail test results based on
specification values
Summary and detail plots
Oscilloscope screenshots
Measurement and Instrument
configuration summary

Report contents are user definable
content

Provision to append more results later