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Fine Pitch Interconnection
Tech. & Package Applications
JinYoung Kim, Sr. Director
Amkor Technology Korea
Technology Trend -- Thinner
Thickness decreased by almost 50% over 5 years
The thickness of AP processor decreased by 30%
Market Demands -- Finer
Why Cu Pillar ?
• Thinner + Finer
Limitation : Wire length & Loop height
thinner
Wire Bonding
Limitation : Bump aspect ration
finer
Solder Bump (C4)
Best Current Carrying Capacity
•
•
•
Low electrical resistance
High electro-migration performance
Cu Pillar > SnAg > SnPb eutectic > High Pb
Cathode
Die
e-
e-
Anode
Cathode
Substrate
Electrical
Resistivity
(uohm-cm)
Thermal
Conductiv
ity (W/mK)
Cu100
1.72
40
Sn100
12.4
73
Sn/3.5A
g
12.3
55
Sn/3.0A
g/0.5Cu
13.2
58
Sn/37Pb
14.5
50
90um UBM /
75um SRO
diameter
Cu substrate
finish
Anode
Design Improvement
• Cu pillar enables fine pitch peripheral design
Area Array Flip Chip
Finer Pitch
Fine Pitch Peripheral Flip Chip
The benefits of fine pitch Cu pillar
• Layer count reduction
Device Name
Solder Bump
Cu Pillar
Bump Pitch
180
110 / 55
BPO / Pad size
80 / 105
25 / 100 / CuP
Line/Space
25 / 25
19 / 20
PCB Thickness
392
281
PCB Layers
4 Layers (1-2-1)
2 Layers
Body size
12 x 12 mm
12 x 12 mm
4 layers
(180, 25/25)
2 layers
(55/110,
19/20)
Low-K Layer Stress
•
It is not easy for mass reflow to control the stress by thermal mismatch during
reflow processing. So it causes the low-k layer damage
Low-k layer damage
Simulated Max Tensile stress
of low k layer after chip
attach at die corner
Thermo-Compression Bonding
• Mass Reflow
• TCNCP (Thermo Compression Non-Conductive Paste)
TCNCP Process
HEAD
DIE
Cu pillar
NCP
PCB
Die
Cu pillar
PCB
Bump pad
Solder NCP
TCNCP Benefits
•
It is easy for TCNCP to control the thermal stress by holding tools for the
die and substrate. So it will not require many actions to compensate for
the thermal stress release like mass reflow.
low k Stress
Passivation
Structure
Lower
CTE PCB
Thin die
Low k damage
Concerned Zone
Potential risk Zone
Safe Zone
Other parameters
TCNCP
application
Cu Pillar at Mass Production
• Amkor Experience
Category
Fine Pitch
Passivation
Bumping
HVM(Prevail)
Sample Run
Silicon Nitride/ Oxy Nitride/ No PI
Pad
Die
Standard Pitch
Al
Cu, Al
Bump Pitch
> 45um in-line
40/80um staggered
150um array
~ 200um array
80~100um
>45um
30/60 staggered
Si node
28, 45, 65nm
32, 40, 45, 65nm
45~65nm
20nm~14nm
Structure(Pillar)
Cu + LF
(25um+15um)
Cu + LF
(25um+15um)
Cu + LF
(25um+15um)
Total height
(>35um)
NI layer
W/O Ni
W/O Ni
W/O Ni
W/O Ni
PI
W/O PI
W/O PI
W/O PI
PI
Seed
metal(UBM)
TiW/Cu
(1000A/2000A)
TiW/Cu
(1000A/2000A)
TiW/Cu
(1000A/2000A)
TiW /Cu, Ti/Cu
(1000A/2000A)
UBM size
Min. 25um
30~80um
30um
Min. 23um
Pillar Diameter
Min. 27um
32~86um
32um
Min. 25um
Section View
TCNCF (TC+ Non Conductive Film)
•
•
•
•
Pre-coated non-conductive film underfill material on wafer or substrate
Smaller keep out zone than MRCUF
Relatively simple process flow
Applicable for finer pitch and narrower gap
Quick Local Reflow (QLR)
• High UPH Thermo Compression Bonding
– Chip attach method that pre-molten solder
– Lower Low-K stress than Mass Reflow + CUF
– Higher throughput than TC+NCP
260~300 °C
Die
Flux on pad
 Flux jetting on substrate
 Die pick up to heater
(Head temp : 260~300’C)
 Alignment
260~300 °C
0.5~1.0 sec
Die
 Bump to head contact
 Hold 0.5~1.0 sec
260~300 °C
Die
 Head vacuum off
 Head up
QLR Benefits
• UPH improvement
– No need to heater cooling time (27%)
– Short bonding time (34%)
– Fast bond head down speed (15%)
• Low ELK Stress
Max. ELK Stress after C/A
fcCSP, 14mmx14mm
Comparison among MRCUF, TCNCP and QLR
UPH advantage
MRCUF
Bump count
TCNCP
QLR
8000
Fine pitch
availability
28nm
High
Middle
PCB layer
reduction
20nm
14/16nm
Si Node
Low
Thermal stress
reduction
* Single Chip to Substrate case
The Big Question
How to interconnect each components ?
What’s the best sequence (Process flow) ?
Source : google
Typical Structure of 2.5D
Micron Bump
• 40~45um pitch (most product)
• Cu/LF or Cu/LF with Ni barrier
• Bump height : 20~50um +/-10%
Interposer Front-side Pad
• Cu/Ni/Au
Interposer Backside Finish
• SiN inorganic passivation+ Cu RDL
+ Organic passivation
• SiN inorganic passivation + Organic
passivation (optional)
• Eutectic or Lead Free C4 bump
How to Interconnect ?
Cost Effectiveness & Fine pitch Capability





Logic + stacked memory


Logic + multiple single memory



Logic + small logic

Multiple small logic
All in use today by Amkor
Large
Small
interposer
interposer


Large logic

Single
Stacked
memory or
memory
small logic



High UPH
MR
MR
MR
MR
MR
Warpage
QLR
Warpage
QLR
QLR
QLR
TC-NCF
TC-NCF
TC-NCP
TC-NCF
TC-NCF
Warpage
TC-NCP
ELK Stress

Small FF
Small FF
Which is Optimal Process Flow ?
High yield & Robust Process
CoS (Chip on Substrate)
Interposer attach to
substrate then top die
attach to interposer
CoW (Chip on Wafer)
Top die attach to
interposer wafer ->
MEOL -> Dicing ->
Stacked die attach to
substrate
CoC (Chip on Chip)
Top die attach to finished
interposer then stacked
die attach to substrate
Use of finished interposer
assembly
Chip on Substrate Process Flow
Interposer
Carrier
Front side
bond &
Bump
TSV reveal
Logic
Sort
Back side
Carrier
bump
debond
U-bump
Thinning
Assembly 1
Interim
Test
Memory
(Option)
Stacked
memory
inspection
Assembly 2
Assembly 1
•
•
Interposer attach to Substrate
Logic attach to interposer
•
•
Memory attach to interposer
BGA ball attach
Assembly 2
Final Test
Chip on Wafer Process Flow
FS(pad) bump
CoW bond
Wafer mold
Mold grind
WSS bonding
TSV reveal
BS(C4) bump
WSS debond
Final assembly
Process Comparison
Chip on Substrate
Die
stacking
Interposer die attach to SUBSTRATE
first
Chip on Wafer
Top die attach to interposer WAFER first
Interposer Use of finished interposer
Use of full thickness interposer (before
MEOL)
Top die
attach
method
Mass reflow (preferred) and TC
bonding
Mass reflow
Leverages std. flip chip process
Top die attach to interposer WAFER first
Positivies Intermediate test and flexibility in
stacking
Negatives
- Warpage management required
Possible cost reduction when high yield &
throughput is possible
- Expensive BOM & high investment
- Requires warpage control for molded wafer
- Top die must be smaller than bottom die
Amkor 2.5D experience (CoS)
• 2.5D Interposer – Side by Side Stacking
─ Engaged with many top tier customers : several years of development
completed
─ Greater than 22K 2.5D parts built to date
─ Engineering reliability data completed for POR lock
─ Interposers from four different foundries
─ Logic on Interposer assembly
 Multiple logic die on single thinned interposer
─ Logic + Memory on Interposer assembly
 Single logic die + multiple memory stacks on single thinned interposer
Amkor 3D Experience
• 3D-Tier to Tier Stacking
– Engaged with many top tier customers : several years of development
completed
– Greater than 5K 3D parts built to date
– Engineering reliability data completed for POR lock
– Small package body focused (<20mm)
– TSV logic wafers from four different foundries
– Memory TSV wafers from one supplier
– Logic + Memory on substrate assembly
• Overmold and bare-die options available
• Lid options available
– Memory + Memory on substrate assembly
• Same size memory stack
Memory on Logic
8 die stack using DRAM Device
Silicon Photonics (CoW)
• Electric driver die + Photonic die
–
–
–
–
Electric driver die : 5x7mm (daughter)
Photonic die : 13x9mm (mother)
Bump pitch : 50um
Chip on Wafer + MRCUF
Summary
• Cu Pillar is core technology for the fine pitch interconnection
• Cu Pillar provides potential substrate cost reduction, improved
electrical & thermal performance, and electromigration resistance.
• TCNCP provides optimal solution for Low-K, thin packages
• TCNCF enables small form factor system integration
• QLR is a low-cost alternative to TCNCP
• Selection of interconnection methods and proper definition of
process flow is the key element of 2.5D and 3D system integration