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An Implementation of Spread Spectrum using an MCU with the Si5341/Si5345 timing devices
One of the most effective approaches to controlling EMI is to use spread spectrum clock generation.
Frequency spreading is done by modulating the frequency so that the peak energy is lowered and
distributed to other frequencies and their harmonics. Instead of a constant frequency the clock is
modulated across a smaller frequency that creates a frequency spectrum with sideband harmonics. By
intentionally spreading the narrowband clock across a broader band the peak spectral energy of both
the fundamental and harmonic frequencies can be reduced. The modulation frequency typically chosen
is 30-33 kHz, with 0.5% down-spread. This comes from the PCIe specification and is the typical
modulation profile which is broad enough to spread the energy around the carrier yet narrow enough to
avoid creating timing and tracking issues. Some of the Silicon Labs timing products have this
programmable capability built in, such as the Si5350/51. For products that do not have this capability it
is possible to use an MCU with the device if it has an external increment decrement pin feature for
adjusting the output frequency. GPIO pins on the MCU can be used to control incrementing and
decrementing the output frequency at a specific calculated time interval. An example of this is shown
using the Silicon Labs C8051F850MCU with the Si5341 or Si5345 device. These devices have external
frequency increment and decrement pins that are exposed on the pin out that can be toggled to
accomplish this task. Although other devices also may have the FINC and FDEC external pins the register
map is different and the example below will have different register settings. The same principles apply
and this methodology can be followed for other devices, but be aware that the register map may be
different.
P0.0
FINC
Si534x
MCU
P0.1
FDEC
Figure 1: Block Diagram Configuring the Si5341/45 with an MCU to implement Spread Spectrum
There are various calculations to consider to configure the system to have a modulation frequency of
30-33 kHz with 0.5% down-spread. The first thing to consider is the clocking speed of the MCU to know
how fast instructions can be set that will toggle the MCU GPIO pins. The C8051F850 MCU system clock
speed is set to 24.5MHz, which is 40.816 nS (4.1E-08) per SYSCLK cycle. The accuracy of the MCU system
clock is also important to consider. The accuracy of this MCU over voltage and temperature is 4.08%,
which should be good enough.
There is a limit on the speed at which the FINC and FDEC pins can be toggled. The frequency to toggle
the FINC/FDEC pin of the Si5340 cannot be much higher than 1 MHz. Therefore the MCU must toggle
the FINC or FDEC pin at a rate that causes the transitions to be somewhere below 1 MHz. The second
consideration is the minimum number of MCU clock ticks required to perform a uniform high to low
transition that can loop indefinitely. The calculations in Table 1 were used to find the edge transition
timing.
Table 1: MCU FINC/FDEC Transition Timing Optimization
SYSCLK ticks per
edge
Time SYSCLK tick (24.5MHz)
Accumulated Time Per Edge
Frequency
Time Per Cycle (2xEdge) (1/TimePerCycle)
5
4.1E-08
2.0408E-07
4.1E-07
2450000.00
6
4.1E-08
2.449E-07
4.9E-07
2041666.67
7
4.1E-08
2.8571E-07
5.7E-07
1750000.00
8
4.1E-08
3.2653E-07
6.5E-07
1531250.00
9
4.1E-08
3.6735E-07
7.3E-07
1361111.11
10
4.1E-08
4.0816E-07
8.2E-07
1225000.00
11
4.1E-08
4.4898E-07
9E-07
1113636.36
12
4.1E-08
4.898E-07
9.8E-07
1020833.33
13
4.1E-08
5.3061E-07
1.061E-06
942307.69
Figure 2: 5 SYSCLK ticks per Edge
The maximum possible frequency that the MCU can loop with an even repeatable cycle is 5 SYSCLK ticks
per edge (2.45 MHz). This is due to the limitation of the while loop that is controlling the pin toggle. The
while loop instruction takes 5 SYSCLK ticks.
P0.0 Set 2 cycles
Delay 3 cycles
P0.0 Clear 2 cycles
Delay 3 cycles
P0.1 Set 2 cycles
Delay 3 cycles
P0.1 Clear 2 cycles
While Loop 5 cycles
Figure 3: 13 SYSCLK ticks per Edge
To achieve a toggle frequency slightly under 1 MHz, 13 SYSCLK ticks per edge are used. This means 11
delay cycles are necessary per edge, since a SET and CLEAR instruction are both 2 cycles. From Table 2
the time to decrement by 15 cycles and then increment by 15 cycles (total of 30 cycles) will take 31.8 us,
which is a frequency of 31.4 kHz.
30 * 1.061E-6 = 31.836 E-6
1/31.836E-6 = 31.41kHz, which is right in the middle of the PCIe 3.0 Specification (30-33 kHz)
A total of 30 steps are required, 15 Cycles of FDEC and 15 cycles of FINC
Table 2: Calculations to determine the Optimal PCIe Frequency and Number of Steps required
MCU Half Cycles
Time Per Clock Time Per Half Cycle
Time Per Cycle
MCU Frequency Optimal PCIe Fq #Total Steps
5
4.08163E-08
2.04082E-07
4.08163E-07
2450000.00
31.41k
78
6
4.08163E-08
2.44898E-07
4.89796E-07
2041666.67
30.934k
66
7
4.08163E-08
2.85714E-07
5.71429E-07
1750000.00
31.25k
56
8
4.08163E-08
3.26531E-07
6.53061E-07
1531250.00
31.90k
48
9
4.08163E-08
3.67347E-07
7.34694E-07
1361111.11
30.93k
44
10
4.08163E-08
4.08163E-07
8.16327E-07
1225000.00
30.625k
40
11
4.08163E-08
4.4898E-07
8.97959E-07
1113636.36
30.934k
36
12
4.08163E-08
4.89796E-07
9.79592E-07
1020833.33
31.901k
32
13
4.08163E-08
5.30612E-07
1.06122E-06
942307.69
31.41k
30
14
4.08163E-08
5.71429E-07
1.14286E-06
875000.00
31.250k
28
Figure 4: Pin toggling showing FDEC (P0.0) and FINC (P0.1)
From the calculations above in Error! Reference source not found., using 13 cycles per transition, the
frequency controlling FINC and FDEC is set to under 1 MHz. With 15 steps down and 15 up the
modulation frequency is 31.4 kHz.
ClockBuilder Pro is a software tool to configure the Si534x/8x device settings to create frequency plans
and to configure the clock inputs and outputs. In ClockBuilder Pro a profile can be set up with 100 MHz
for the output frequency. Reviewing the design report text file N0_NUM at register 0x0302 is set to
0x02200000000 and N0_DEN is set to 0x80000000.
The following calculations show how these registers are set:
13600*DEN = 100
NUM *2
100MHz is the output frequency. The 13600 as the VCO Frequency in MHz. The Denominator is set to 1
and the numerator can be calculated. The resulting value for the numerator and denominator is then
left shifted.
NUM = 13600/200= 68 0x44, left shifted by 31 bits = 0x02200000000 (1.46029E11)
DEN = 1, left shifted by 31 bits = 0x80000000 (2147483648)
Note: 1.46029E11/2147483648=68.0000000000000000
The down-spread for the modulation can be set to be 0.45%, which is slightly below 0.5% per the PCIe
specification. Taking 0.45% of 100 MHz is equal to 450,000 Hz. So 450,000 Hz represents the total
frequency that must be divided by 15 to get to the bottom of the down-spread.
Dividing 450,000 Hz by 15 steps is equal to 30,000 Hz per step.
Going back to the original form, but putting in the numerator multiplied by the output frequency
(1.46029E11 * 100 = NUM * 100). The numerator is left shifted as from above (0x02200000000) and
then it is multiplied by 100 MHz, as seen below on the right hand side of the equation.
13600* DEN =1.46029E13
2
Next the NUM*100 is divided by 100 with the additional 30 kHz (which is one additional step)
1.46029E13 = 145985092536.239
100.03
This resulting value is equal to the numerator step change. This value is then subtracted from the
numerator value as shown below, and this is assigned as the step size used in N0_FSW field.
1.46029E11 – 145985092536 = 43,795,528 (Step Size= N0_FSW)
This final calculation shows the 0.45% drop. The frequency should range from 100MHz down to
99.55MHz.
1.46029E13/ (1.46029E11+ (43,795,528*15)) = 99.55MHz
In order to set up the part to enable the FINC/FDEC pins and to set the appropriate step size per
command, the following register settings must be inserted into the frequency plan. This was calculated
above. The other register settings are required to use the FINC/FDEC from pin control of the MCU GPIO.
The settings are shown below in Figure 5.
43,795,528
Figure 5: Register Settings to Implement FINC/FDEC with Pin Control
The frequency modulation is shown below in Figure 6 from an MCU toggling the FINC and FDEC pins,
showing the 0.45% down-spread from 100 MHz.
Figure 6: Screen Capture of the Output Frequency being stepped down and up using the MCU