1. No category

ICSO 2014
Tenerife
CRYOGENIC AND RADIATION-HARD ASIC
FOR INTERFACING LARGE FORMAT
NIR/SWIR DETECTOR ARRAYS
P.Gao, B.Dupont, B.Dierickx, E.Mueller,
G.Verbruggen, S.Gielis, R.Valvekens,
About us
•Image sensors and periphery ASICs
•Founded 2006
•Mechelen, Belgium
•17 p (10 designers)
Supplier of Custom designed
Beyond “State of the Art” CMOS Image sensors and ASIC for
Space, Scientific, Industrial and Medical applications
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Outline
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Motivation
Architecture and building block design
Design for Radiation hardness and Cryogenic
temperature
Test results
Conclusions & future work
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ASIC for LF NIR/SWIR detector array
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Outline
•
•
•
•
•
Motivation
Architecture and building block design
Design for Radiation hardness and Cryogenic
temperature
Test results
Conclusions & future work
11/2/2014
ASIC for LF NIR/SWIR detector array
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Why an ASIC ?
To operate an IR imagers
[Z.Zhao.SDA’05]
Analog domain
Signal conditioning
Analog to digital converter
Regulated power supply
Bias voltage/current references
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Digital domain
Digital control core
Memory & Clock
Data Communication
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The ASIC
This development aims at providing the community with
a IR imager accompany ASIC
• Tailored to imagers (especially IR sensor)
– Easy to control
– Simple to intergrade
• Taking in consideration multiple IR detector manufacturers
specificities
•Wide operating temperature range (77k – room T)
•Able to drive multi-sensor/array systems
•Radiation hard
– 1Mrad TID
– 60MeVcm2 /mg SEU
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Outline
•
•
•
•
•
Motivation
Architecture and building block design
Design for Radiation hardness and Cryogenic
temperature
Test results
Conclusions& future work
11/2/2014
ASIC for LF NIR/SWIR detector array
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Architecture
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Analog section
Bandgap
T sensor
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Supply
• LDO
– Programmable output
• 1,3…3.4V
– Stability: PM>60°
– Output current 0-100mA
• Bandgap
– 1.2V
– 77K-300K
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Conversion channel
• One ADC addressed 4 analog inputs in prototype ASIC
• CDS
– Bypassable
• Preamplifier (PA)
– Programmable gain from 0-30dB in 6dB step
– Offset cancellation (8-bit)
– Single to differential
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ADC
• 16-bit, 100kHz, fully differential SAR ADC
– Hybrid feedback DAC
– Low offset comparator auto zero
• A calibration scheme is implemented
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Digital section
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Specifications
Digital domain
Master clock
0 – 200 MHz
System level protocol
2 – 200 Mbit/s Space Wire
ROIC digital control
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ROIC monitoring and trigger inputs
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Scheduler time granularity
10M updates/s
Sequence nesting depth
8
ROIC programming channel
1 SPI
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Outline
•
•
•
•
•
Motivation
Architecture and building block design
Design for Radiation hardness and Cryogenic
temperature
Test results
Conclusions& future work
11/2/2014
ASIC for LF NIR/SWIR detector array
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Radiation hardness: digital
•Synthetized digital logic
–DARE lib (IMEC & ESA)
•0.18 um CMOS 1P6M
•Digital cell with TID, SEU, SEL tolerance
•Allows custom mixed-signal design
–Redundancy
•Hamming Codes
•Parity check
•Safe FSMs
–Watchdog Timers
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Radiation hardness: analog
DARE has a limited subset of analog component.
Caeleste developed its own radhard cells
•Analog and High Voltage logic standard cells
•Full custom tactical cells
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Analog & mixed mode
TID & TnID hardness
SEL hardness
SEU hardness without TR
<20% increased Cin and power
<50% area increase
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Normal
Caeleste
mixed mode
Caeleste RH
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Design for low temperature
•Synthetized digital logic:
– A derating of speed, power, etc. of the library
– SRAM
•Analog custom design:
– Active component modeling
– Component selection
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Cryogenic digital design
The DARE library has never been used at 77K before
•Faster but risk for set-up and hold time violation.
– Adapted models based on characterization at 218K
•SRAM has not been validated before
– Backup registers
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Cryogenic analog design
• MOSFET modeling
– Vth: increase
– Mobility: increase
– MOS switch: low Ron
PMOS: 0.75-0.97
NMOS: 0.68-0.91
Transistor Vt
• Passive components
– Highly doped non silicide poly Resistor for stability
– MIM capacitors
• Rely on ratios not absolutely values
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Outline
•
•
•
•
•
Motivation
Architecture and building blocks design
Design for Radiation hardness and Cryogenic
temperature
Test results
Conclusions
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Test setup
Unified design for:
RT board
CT board
+
Precision
DAC board
Digital Controller
RT board
ASIC
COB
Analog test
board
Base plate
+
CT board
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Bandgap and temperature sensor
Bandgap measuement
T-sensor measurement
1,35
1,0
0,9
T coefficient< 1mV/K
0,8
output voltage (V)
output valtage (V)
1,3
1,25
1,2
1,15
T coefficient: 3mV/K
0,7
0,6
0,5
0,4
0,3
0,2
1,1
0,1
1,05
0
50
100
150
200
250
300
350
0,0
70
120
Temperature (K)
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170
220
Temperature (K)
270
320
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Reference and Biases 10-bit
BIAS0 DNL
0,04
0,03
DNL(LSB)
0,02
0,01
0
-0,01 0
200
400
600
800
1000
600
800
1000
-0,02
-0,03
-0,04
Input code
BIAS0 INL
0,6
INL(LSB)
0,4
0,2
0
0
200
400
-0,2
-0,4
Input code
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R monitor
• On chip SC current source.
– R range 10k – 70k ohm
Measured output voltage with 2MHz clock
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16-bit SAR ADC INL DNL
•INL DNL problem :
–Root cause is a AC coupling in the
M5
layout: 2 fF cross-coupling
M4
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ADC INL DNL
• ADC INL DNL problem analysis
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ADC INL DNL
• ADC INL DNL @ 50KHz fs
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Measurement summary
Measurement result @ room T
Specs
Supply voltage
Total current consumption
Regulator PSRR
Regulator I out
Output impedance
LDO output
Analog rail to rail voltage
Reference DAC INL
Reference DAC DNL
ADC noise
ADC fs
ADC INL
ADC DNL
Monitor resistance range
Number of digital outputs/ inputs
Digital output clock speed
Serial interface speed
SpaceWire bit rate
ASIC start-up time
Temperature range
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@ cryogenic T
3.5-3.6V
53mA
60.5mA
> 40dB
> 40mA
< 1Ω
1.3-3.4 V
3.3 V
0.7LSB
0.06LSB
2.5LSB
1LSB
0.04LSB
2.1LSB
50, 100, 200KHz
78LSB (15LSB@50KHz)
76LSB (16LSB@50KHz)
10KΩ -70KΩ
32 / 8
0-10 MHz
50KHz-50MHz
0-200 Mbps
≤50us
77K-room T (Measured)
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Outline
•
•
•
•
•
Motivation
Architecture and building
block design
Design for Radiation hardness
and Cryogenic temperature
Test results
Conclusions& future work
11/2/2014
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Conclusions
•
Prototype accompany ASIC for (IR) detector arrays which
provide all functionalities has been demonstrated
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•
Full function has been proven from cryogenic (77K) to
room temperature
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All Caeleste custom designed cells
Digital cells in DARE Lib. Including SRAM
Highly flexible for ROICs
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ADC problem founded and will solve in next iteration
Highly programmable sequencer
Wide programmability and large dynamic ranges in analog
acquisition chain
Beyond IR imagers
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Next steps ?
•
Larger ASIC with multiple channels (32 to 64)
•
Faster ADCs is now developing at Caeleste (up to
12MS/s with reduced resolution)
•
Irradiation testing
•
More discussion with instrument builders and IR sensor
manufacturers for further enhancements
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Thank you!
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