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International Journal of Innovative Research in Advanced Engineering (IJIRAE)
Volume 1 Issue 10 (November 2014)
ISSN: 2349-2163
www.ijirae.com
Implementation of High Speed Vedic Multiplier
Akanksha Pawar
Anil Kumar Sahu
Dr. G. R. Sinha
ME research Scholar
SSGI (FET), Bhilai
Assistant Professor
SSGI (FET), Bhilai
Professor /ETE & Associate Director,
SSGI (FET),SSTC, Bhilai
Abstract: There are several multiplication algorithms, one - the Egyptian multiplication - came to us from antiquity and the same
is probably true of the Vedic algorithm. Another method - the lattice multiplication - has been brought to Europe in the early
1200s, and the fourth one, known as the Russian Peasant multiplication, was in all likelihood developed much later and
appeared in relatively modern times. A curious model of multiplication that was reputedly devised by a Chinese teacher has been
making rounds on the Internet is probably not older than the Internet itself. Except of the Vedic variant, none claims a divine
origin. The main objective of this paper is to design and implementation of a fast multiplier with vedic mathematics, which can
be used in any processor application. This paper deals with the study, design and implementation of Vedic multiplier starting
from 4×4 to 64×64 bit multiplier. In this paper work, also the study of Vedic multiplication has been explored. And architecture
of Vedic multiplier based on less number of gates and high speed specification is designed here. Synthesis Implementation of this
multiplier has been done on Xilinx XST and Smulation is done on ModelSim 6.5s Tool.
Key words: Adaptive filter, Prime and Binary field, VLSI.
I.
INTRODUCTION
Multiplication is basically a shift add operation. There are, however, many variations on how to do it. Vedic mathematics was
rediscovered in the early twentieth century from ancient Indian sculptures (Vedas).Ancient Indian system of mathematics was
derived from Vedic Sutras. The conventional mathematical algorithms can be simplified and even optimized by the use of Vedic
mathematics. The Vedic algorithms can be applied to arithmetic, trigonometry, plain and spherical geometry, calculus.
1.1 URDHVA TIRYAGBHYAM
The “Urdhva Tiryagbhyam‟ Sutra is a general multiplication formula applicable to all cases of multiplication. „Urdhva‟ and
Tiryagbhyam‟ words are derived from Sanskrit literature. „Urdhva‟ means “Vertically” and „Tiryagbhyam‟ means “crosswise”.
The LMS algorithm was devised by the multiplier is based on an algorithm Urdhva Tiryakbhyam (Vertical & Crosswise) of ancient
Indian Vedic Mathematics. Urdhva Tiryakbhyam Sutra is a general multiplication formula applicable to all cases of multiplication.
It literally means “Vertically and crosswise”. It is based on a novel concept through which the generation of all partial products can
be done with the concurrent addition of these partial products. The parallelism in generation of partial products and their summation
is obtained using Urdhava Triyakbhyam.
The designing of Vedic Multiplier is based on a novel Urdhava Triyakbhyam technique of digital multiplication which is quite
different from the conventional method of multiplication like add and shift. Where smaller blocks are used to design the bigger one.
The Vedic Multiplier is designed in Verilog HDL, as its give effective utilization of structural method of modelling. The individual
block is implemented using Verilog hardware description language. The functionality of each block is verified using simulation
software, ModelSim and ISE.
1.2 MULTIPLICATION OF TWO DECIMAL NUMBERS IN VEDIC TECHNIQUE- 325*738
The digits on the both sides of the line are multiplied and added with the carry from the previous step. This generates one of the bits
of the result and a carry. This carry is added in the next step and hence the process goes on. If more than one line are there in one
step, all the results are added to the previous carry. In each step, least significant bit acts as the result bit and all other bits act as
carry for the next step. Initially the carry is taken to be zero
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© 2014, IJIRAE- All Rights Reserved
Page -396
International Journal of Innovative Research in Advanced Engineering (IJIRAE)
Volume 1 Issue 10 (November 2014)
ISSN: 2349-2163
www.ijirae.com
1.3 NIKHILAM SUTRA
Nikhilam Sutra literally means “all from 9 and last from 10”. Although it is applicable to all cases of multiplication, it is more
efficient when the numbers involved are large. Since it finds out the compliment of the large number from its nearest base to
perform the multiplication operation on it, larger is the original number, lesser the complexity of the multiplication. We first
illustrate this Sutra by considering the multiplication of two decimal numbers (96 * 93) where the chosen base is 100 which is
nearest to and greater than both these two numbers
1.4 THE MULTIPLIER ARCHITECTURE
The multiplier architecture is based on this vedic sutra. The advantage of this algorithm is that partial products and their sums are
calculated in parallel. The main advantage of this multiplier as compared to other multipliers is its less number of gate based design.
The architecture can be explained with two 64 bit numbers i.e. the multiplier and multiplicand are 64 bit numbers. The multiplicand
and the multiplier are split into four 32 bit multiplier blocks. The four bit blocks are again divided into four 16 bit multiplier blocks
and the similar fashion is repeated upto two bit multiplications.
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© 2014, IJIRAE- All Rights Reserved
Page -397
International Journal of Innovative Research in Advanced Engineering (IJIRAE)
Volume 1 Issue 10 (November 2014)
ISSN: 2349-2163
www.ijirae.com
Fig 3.3 Proposed architecture of 64x64 bits Vedic Multiplier.
RESULT = (P127-P64) & (P63-P32) & (P31-P0)
Figure 3.9: 32X32 Bits proposed Vedic Multiplier.
RESULT = (P63-P32) & (P31-P16) & (P15-P0)
Fig 3.8 16x16 Bits decomposed Vedic Multiplier
RESULT = (P31- P16) & (P15- P8) & (P7- P0)
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© 2014, IJIRAE- All Rights Reserved
Page -398
International Journal of Innovative Research in Advanced Engineering (IJIRAE)
Volume 1 Issue 10 (November 2014)
ISSN: 2349-2163
www.ijirae.com
Fig 3.7 8X8 Bits decomposed Vedic Multiplier
RESULT = (P15- P8) & (P7-P4) & (P3-P0)
Fig 3.4 Proposed 4x4 Bit Vedic Multiplier
RESULT = (P7- P4) & (P3-P0)
2. SIMULATION RESULT
64×64 Bit Multiplier
32×32 Bit Multiplier
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© 2014, IJIRAE- All Rights Reserved
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International Journal of Innovative Research in Advanced Engineering (IJIRAE)
Volume 1 Issue 10 (November 2014)
ISSN: 2349-2163
www.ijirae.com
2.1 SYNTHESIS RESULT
64×64 Bit Vedic Multiplier
32×32 Bit Vedic Multiplier
HDL Synthesis Report 64 Bit Multiplier
•
=========================================================================
•
Advanced HDL Synthesis Report
•
Macro Statistics
•
# Registers
: 4096
•
Flip-Flops
: 4096
•
# Xors
: 1022
•
16-bit xor2
: 96
•
32-bit xor2
: 24
•
4-bit xor2
: 512
•
64-bit xor2
:6
•
8-bit xor2
: 384
•
=========================================================================
output. The difference between the reference signal and the actual output of the transversal filter is the error signal
3. CONCLUSION
The proposed Vedic multiplier architecture shows speed improvements over multiplier architecture presented in the 64x64 Vedic
multiplier along with other lower bit multipliers using Urdhva Tiryakbhyam‟ Sutra found to be better in terms of speed and
complexity in the gate level design architecture . This approach may be well suited for multiplication of numbers with more than 64
bit size.
4. REFERENCES
[1]. Implementation of Multiplier using Vedic Algorithm ;Poornima M, Shivaraj Kumar Patil, Shivukumar , Shridhar K P , Sanjay
H International Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-2, Issue-6,
May 2013.
[2].Design of High Speed Vedic Multiplier using Vedic Mathematics Techniques; G.Ganesh Kumar, V.Charishma;International
Journal of Innovative Technology and Exploring Engineering (IJITEE) ISSN: 2278-3075, Volume-2, Issue-6, May 2013
[3]. Purushottam D. Chidgupkar and Mangesh T. Karad, “The Implementation of Vedic
Algorithms in Digital Signal
Processing”, Global J. of Engng. Educ., Vol.8, No.2 © 2004 UICEE Published in Australia.
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© 2014, IJIRAE- All Rights Reserved
Page -400
International Journal of Innovative Research in Advanced Engineering (IJIRAE)
Volume 1 Issue 10 (November 2014)
ISSN: 2349-2163
www.ijirae.com
[4]. E. Abu-Shama, M. B. Maaz, M. A. Bayoumi, “A Fast and Low Power Multiplier Architecture”, The Center for Advanced
Computer Studies, The University of Southwestern Louisiana Lafayette, LA 70504.
[5]. Jenkins, W. Kenneth, Hull, Andrew W ,Strait, Jeffrey C., Schnaufer, Bernard A., Li, Xiaohui, Advanced Concepts in Adaptive
Signal Processing, Kluwer Academic Publishers, Boston, 1996.
[6]. Himanshu Thapliyal and Hamid R. Arabnia, “A Time-Area- Power Efficient Multiplier and Square Architecture Based On
Ancient Indian Vedic Mathematics”, Department of Computer Science, The University of Georgia, 415 Graduate Studies
Research Center Athens, Georgia 30602-7404, U.S.A.
First Author: Ms. Akanksha Pawar is currently pursuing M.E. in VLSI Design from Shri shankaracharya
group of institutions, Bhilai (India). She has completed her B.E. from Columbia Institute of engineering
and technology Raipur in Electronics and Telecommunication branch. Her area of interest is in the field
of Digital VLSI.
Second Author: Mr. Anil Kumar Sahu is working as assistant professor in shrishankaracharya group of
institutions, Bhilai (India). He is currently pursuing his Ph.D. from Swami Vivekananda technical
university Bhilai. He has completed his M.Tech in Microelectronics and VLSI Design from SGSIT, INDORE
in (2008). He has 5 years of academic experience and has 12 international journal and 12 national
Conference publications. Prof Sahu’s area of interest is in the field of Mixed signal design,VLSI testing ,a
front end VLSI Design.
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