P10.34
An ideal diode acts as a short circuit as long as current flows in the
forward direction. It acts as an open circuit provided that there is
reverse voltage across it. The volt-ampere characteristic is shown in
Figure 10.15 in the text. After solving a circuit with ideal diodes, we
must check to see that forward current flows in diodes assumed to be on,
and we must check to see that reverse voltage appears across all diodes
assumed to be off.
P10.35
The equivalent circuit for two ideal diodes in series pointing in opposite
directions is an open circuit because current cannot flow in the reverse
direction for either diode.
The equivalent circuit for two ideal diodes in parallel pointing in opposite
directions is a short circuit because one of the diodes is forward
conducting for either direction of current flow.
P10.36
10
= 3.70 mA.
2700
(a)
The diode is on, V = 0 and I =
(b)
The diode is off, I = 0 and V = 10 V.
(c)
The diode is on, V = 0 and I = 0.
(d)
The diode is on, I = 5 mA and V = 5 V.
335
P10.62
A clipper circuit removes or clips part of the input waveform. An
example circuit with waveforms is:
We have assumed a forward drop of 0.6V for the diode.
P10.63
Refer to Figure P10.63 in the book. When the source voltage is negative,
diode D3 is on and the output vo(t) is zero. For source voltages between 0
and 10 V, none of the diodes conducts and vo(t) = vs(t). Finally when the
source voltage exceeds 10 V, D1 is on and D2 is in the breakdown region so
the output voltage is 10 V. The waveform is:
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P10.74
(a)
A suitable circuit is:
We choose the resistors R1 and R2 to achieve the desired slope.
R2
1
Slope = =
3 R1 + R2
Thus, choose R1 = 2R2 . For example, R1 = 2 kΩ and R2 = 1 kΩ.
(b)
A suitable circuit is:
Other resistor values will work, but we must make sure that D2
remains forward biased for all values of vin , including vin = −10 V .
To achieve the desired slope (i.e., the slope is 0.5) for the transfer
characteristic, we must have R1 = R2 .
351
P12.3*
K = 21 KP (W / L) = 0.25 mA/V 2
(a) Saturation because we have vGS ≥ Vto and vDS ≥ vGS − Vto.
iD = K(vGS − Vto)2 = 2.25 mA
(b) Triode because we have vDS < vGS − Vto and vGS ≥ Vto.
iD = K[2(vGS − Vto)vDS − vDS2] = 2 mA
(c) Cutoff because we have vGS ≤ Vto. iD = 0.
P12.4*
iD
vGS = 4
3V
2V
vDS
P12.5
The device is in saturation for vDS ≥ vGS − Vto = 3 V. The device is in the
triode region for vDS ≤ 3 V. In the saturation region, we have
iD = K(vGS − Vto)2 = 0.1(vGS − 1)2 for vGS ≥ 1
In the pinchoff region, we have
iD = 0 for vGS ≤ 1
The plot of iD versus vGS in the saturation region is:
411
P12.6
(a) Saturation because we have vGS ≥ Vto and vDS ≥ vGS − Vto.
(b) Triode because we have vGS ≥ Vto and vDS ≤ vGS − Vto.
(c) Saturation because we have vGS ≥ Vto and vDS ≥ vGS − Vto.
(d) Cutoff because we have vGS ≤ Vto.
P12.7
With the gate connected to the drain, we havevDS = vGS so vDS ≥ vGS − Vto.
Then, if vGS is greater than the threshold voltage, the device is operating
in the saturation region. If vGS is less than the threshold voltage, the
device is operating in the cutoff region.
P12.8
For the NMOS enhancement transistors, we have Vto = +1 V. For the
PMOS enhancement transistors, we have Vto = −1 V.
(a) This NMOS transistor is operating in saturation because we have vGS
≥ Vto and vDS ≥ vGS − Vto. Thus, Ia = K(vGS − Vto)2 = 0.9 mA.
(b) This PMOS transistor is operating in saturation because we have vGS ≤
Vto and vDS = −4 ≤ vGS − Vto = −3 −(−1) = −2. Thus, Ib = K(vGS − Vto)2 = 0.4
mA.
(c) This PMOS transistor is operating in the triode region because we
have vGS ≤ Vto and vDS = −1 ≥ vGS − Vto = −5 −(−1) = −4. Thus,
Ic = K[2(vGS − Vto)vDS − vDS2] = 0.7 mA.
(d) This NMOS transistor is operating in the triode region because we
have vGS ≥ Vto and vDS = 1 ≤ vGS − Vto = 3 − 1 = 2. Thus,
Id = K[2(vGS − Vto)vDS − vDS2] = 0.3 mA.
P12.9
With vGS = vDS = 5 V, the transistor operates in the saturation region for
which we have iD = K(vGS − Vto)2. Solving for K and substituting values we
obtain K = 125 µA/V2. However we have K = (W/L)(KP/2). Solving for
W/L and substituting values we obtain W/L = 5. Thus for L = 2 µm, we
need W = 10 µm.
P12.10
To obtain the least drain current choose minimumW and maximum L (i.e.,
W1 = 0.25 µm and L1 = 2 µm). To obtain the greatest drain current choose
maximumW and minimum L (i.e., W2 = 2 µm and L2 = 0.25 µm). The ratio
between the greatest and least drain current is (W2/L2)/(W1/L1) = 64.
P12.11* In the saturation region, we have iD = K(vGS − Vto)2. Substituting values,
we obtain two equations:
412
With Vin = 0, the transistor operates in satruation and Ib = iD = K(vGS −
Vto)2 = 3.2 mA. With Vin = 5, the transistor operates in cutoff and Ib = iD =
0.
P12.14
Because vGD = 3 − 5 = −2 V is less than Vto, the transistor is operating in
saturation. Thus, we have iD = K(vGS − Vto)2. Substituting values gives
0.5 = 0.5(vGS − 1)2 which yields two roots: vGS = 2 and vGS = 0 V. However,
the second root is extraneous, so we have vGS = 2 = 3 − 0.0005R which
yields R = 2000 Ω.
P12.15* We have iD = K (v GS −Vto ) 2 . Substituting values and solving, we obtain
v GS = −2.5 and v GS = 1.5 V. However, if v GS = 1.5 , the PMOS transistor is
operating in cutoff. Thus, the correct answer is v GS = −2.5 V.
P12.16
Distortion occurs in FET amplifiers because of curvature and nonuniform
spacing of the characteristic curves.
P12.17* The load-line equation is VDD = RDiD + vDS, and the plots are:
Notice that the load line rotates around the point (VDD, 0) as the
resistance changes.
P12.18
The load-line equation is VDD = RDiD + vDS, and the plots are:
414
Notice that the load lines are parallel as long as RD is constant.
P12.19* For VGG = 0, the FET remains in cutoff so VDSmax = VDSQ =VDSmin = 20 V.
Thus, the output signal is zero, and the gain is zero. For amplification to
take place, the FET must be biased in the saturation or triode regions.
P12.20
(a) The 1.7 MΩ and 300 kΩ resistors act as a voltage divider that
establishes a dc voltage VGSQ = 3 V. Then if the capacitor is treated as a
short for the ac signal, we have vGS(t) = 3 + sin(2000πt)
(b), (c), and (d)
iD
vGS = 4 V
3V
2V
vDS
From the load line we find VDSQ = 16 V, VDSmax = 19 V, and VDSmin = 11 V.
P12.21* For vin = +1 V we have vGS = 4 V. For the FET to remain in saturation, we
415
Notice that the load lines are parallel as long as RD is constant.
P12.19* For VGG = 0, the FET remains in cutoff so VDSmax = VDSQ =VDSmin = 20 V.
Thus, the output signal is zero, and the gain is zero. For amplification to
take place, the FET must be biased in the saturation or triode regions.
P12.20
(a) The 1.7 MΩ and 300 kΩ resistors act as a voltage divider that
establishes a dc voltage VGSQ = 3 V. Then if the capacitor is treated as a
short for the ac signal, we have vGS(t) = 3 + sin(2000πt)
(b), (c), and (d)
iD
vGS = 4 V
3V
2V
vDS
From the load line we find VDSQ = 16 V, VDSmax = 19 V, and VDSmin = 11 V.
P12.21* For vin = +1 V we have vGS = 4 V. For the FET to remain in saturation, we
415
P12.29* We can write VDD = 20 = 2I DQ + 8 + 2 in which IDQ is in mA. Solving, we
obtain IDQ = 5 mA. Then, we find Rs = 2 / I DQ = 400 Ω. Next, we have
K = 21 KP (W / L) = 0.75 mA/V 2 . Assuming that the NMOS operates in
saturation, we have
I DQ = K (VGSQ −Vto ) 2
Substituting values and solving we find VGSQ = −1.582 V and VGSQ = 3.582
V. The correct root is VGSQ = 3.582 V. (As a check, we see that the
device does operate in saturation because we have VDSQ = 8 V, which is
greater than VGSQ −Vto . ) Then, we have VG = VGSQ + 2 = 5.582 V. However,
we also have
VG = VDD
R2
R1 + R2
Substituting values and solving, we obtain R1 = 2.583MΩ.
P12.30
First, we use Equation 12.11 to compute
VG = VDD
R2
R1 + R2
= 5V
As in Example 12.2, we need to solve:
V
 1

2
2
VGSQ
+ 
− 2Vto VGSQ + (Vto ) − G = 0
RS K
 RS K

Substituting values, we have
2
VGSQ
− 1.1489VGSQ − 3.2553 = 0
The roots are VGSQ = 2.4679 V and −1.319 V. The correct root is VGSQ =
2.4679 V which yields IDQ = K(VGSQ − Vto)2 = 0.5387 mA. Finally, we have
VDSQ = VDD − RDIDQ − RSIDQ = 9.936 V.
P12.31
Assuming that the MOSFET is in saturation, we have
VGSQ = 10 − IDQ
IDQ = K(VGSQ − Vto)2
419
where we have assumed that IDQ and K are in mA and mA/V2
respectively.
(a) Using the second equation to substitute in the first, substituting
values and rearranging, we have
VGSQ2 − 7VGSQ + 6 = 0
which yields VGSQ = 6 V. (The other root, VGSQ = 1 V, is extraneous.)
IDQ = 4 mA
VDSQ = 20 − 2IDQ = 12 V
(b) Similarly for the second set of values, we have
VGSQ2 − 3.5VGSQ − 1 = 0
VGSQ = 3.765 V
IDQ = 6.234 mA
VDSQ = 20 − 2IDQ = 7.53 V
P12.32
We can write VDD = RD I DQ +VDSQ + RS I DQ . Substituting values and solving
we obtain RS = 3 kΩ. Next we have K = 21 KP (W / L) = 0.2 mA/V 2 .
Assuming that the NMOS operates in saturation, we have
I DQ = K (VGSQ −Vto ) 2
Substituting values and solving we find VGSQ = −1.236 V and VGSQ = 3.236
V. The correct root is VGSQ = 3.236 V. (As a check we see that the
device does operate in saturation because we have VDSQ greater than
VGSQ −Vto . ) Then we have VG = VGSQ + Rs iD = 6.236 V. However we also have
R2
VG = VDD
R1 + R2
Substituting values and solving, we obtain R2 = 1.082 MΩ.
P12.33
We have VG = VGSQ = 10R2/(R1 + R2) = 2.5 V. Then we have IDQ = K(VGSQ −
Vto)2 = 0.5625 mA. VDSQ = VDD − RDIDQ = 4.375 V.
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