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Hardware Specifications, Memory Interface and Basic I/O Interface Microprocessor 8086/8088 Prof. Fayez F. M. El-Sousy Department of Electrical Engineering College of Engineering Salman bin Abdulaziz University Al-Kharj, Saudi Arabia Prof. Fayez F. M. El-Sousy Objectives of Hardware Specifications Microprocessor 8086/8088 Upon completion of this chapter, you will be able to: Describe function of each 8086 & 8088 pin. Understand the microprocessor's DC characteristics and indicate its fan-out to common logic families. Use the clock generator chip (8284A) to provide the clock for the microprocessor. Connect buffers and latches to the buses. Interpret the timing diagrams. Describe wait states and connect the circuitry required to cause various numbers of waits. Explain the difference between minimum and maximum Prof. Fayez F. M. El-Sousy mode operation. Hardware Specifications Microprocessor 8086/8088 Introduction In this chapter, the pin functions of both the 8086 and 8088 microprocessors are detailed and information is provided on the following hardware topics: clock generation, bus buffering, bus latching, timing, wait states, and minimum mode operation versus maximum mode operation. These simple microprocessors are explained as an introduction to the Intel microprocessor family. Prof. Fayez F. M. El-Sousy Hardware Specifications Microprocessor 8086/8088 Data bus Internally both are 16 bit data bus Externally 8088 has 8 bit bus AD0 to AD7 8086 has 16 bit bus AD0 to AD15 ALE: address latch enable is needed Address bus : 20 pins Needs a latch to latch the address Most widely used latch is 74LS373 Data bus width is the only major difference. Thus 8086 transfers 16-bit data more efficiently Prof. Fayez F. M. El-Sousy Hardware Specifications Microprocessor 8086/8088 Data bus 8086 Data Bus Prof. Fayez F. M. El-Sousy GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8086 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET Hardware Specifications Microprocessor 8086/8088 Data bus 8088 Data Bus Prof. Fayez F. M. El-Sousy GND A14 A13 A12 A11 A10 A9 A8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8088 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC A15 A16/S3 A17/S4 A18/S5 A19/S6 SS0 MN/MX RD HOLD HLDA WR IO/M DT/R DEN ALE INTA TEST READY RESET Hardware Specifications Microprocessor 8086/8088 Microprocessor 8086 BHE: Bus High Enable Used with ‘86 to distinguish between high and low byte Prof. Fayez F. M. El-Sousy GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8086 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET Hardware Specifications Microprocessor 8086/8088 Microprocessor 8086 NMI: Nonmaskable interrupt Edge triggered input signal from low to high Input to µp. Cause µp to jump into interrupt vector after finishing current instruction Can not be masked by software Prof. Fayez F. M. El-Sousy GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8086 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET Hardware Specifications Microprocessor 8086/8088 Microprocessor 8086 INTR: Interrupt Request Active high leveltriggered input Monitored by µp at the last clock cycle after each instruction. Prof. Fayez F. M. El-Sousy GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8086 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET Hardware Specifications Microprocessor 8086/8088 Microprocessor 8086 CLK: Clock µp require a very accurate clock for synchronizing Intel has designed 8284 clock generator CLK is an input and connected to 8284 clock generator Any irregularity cause the CPU to malfunction Prof. Fayez F. M. El-Sousy GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8086 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET Hardware Specifications Microprocessor 8086/8088 Microprocessor 8086 RESET: Reset •Terminate present activity of µp •Input to µp •Active high •Signal comes from 8284 Clock generator •After reset µp will contains the following Data: CPU Contents CS FFFFH DS 0000H SS 0000H ES 0000H IP 0000H FLAG CLEAR Prof. Fayez F. M. El-Sousy QUEUE EMPTY GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8086 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET Hardware Specifications Microprocessor 8086/8088 Microprocessor 8086 READY: READY •Input signal •Used to insert a wait state for slower memories and IO. •It inserts a wait state when it is low Prof. Fayez F. M. El-Sousy GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8086 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET Hardware Specifications Microprocessor 8086/8088 Microprocessor 8086 TEST •Input signal FROM 8087 Coprocessor Prof. Fayez F. M. El-Sousy GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8086 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET Hardware Specifications Microprocessor 8086/8088 Microprocessor 8086 Pin specifying the operation Mode • Low Maximum Mode • High Minimum Mode The function of pins 24 through 31 of 8088 and 8086 varies depending upon whether the µp is in max or min mode Prof. Fayez F. M. El-Sousy GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8086 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET Hardware Specifications Microprocessor 8086/8088 Microprocessor 8086: Min. Mode Versus Max. Mode Min Mode GND AD14 AD13 AD12 AD11 AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 NMI INTR CLK GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 8086 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 VCC AD15 A16/S3 A17/S4 A18/S5 A19/S6 BHE/S7 MN/MX RD HOLD HLDA WR M/IO DT/R DEN ALE INTA TEST READY RESET Logic 1 Max Mode Logic 0 RQ / GT0 RQ / GT1 LOCK S2 S1 S0 QS0 QS1 The function of pins 24 through 31 of 8088 and 8086 varies Prof. Fayez F. M. El-Sousy depending upon whether the µp is in max or min mode Hardware Specifications Microprocessor 8086/8088 Microprocessor 8086: Min. Mode Versus Max. Mode In Min Mode: Pins 24 – 31 are used as memory and I/O control signals The control signal are generated internally by 8088, 8086 Thus Min Mode is More cost efficient Pins 24 – 31 of 8088, 8086 are functioning similarly to 8085 Thus 8085 peripheral can be used with this mode. Prof. Fayez F. M. El-Sousy Hardware Specifications Microprocessor 8086/8088 In Min Mode: Pins 24 – 31 function are shown in the following table: Pin Function 24 INTA 25 ALE 26 DEN 27 DT/R 28 M/IO (8086) or IO/M (8088) 29 WR 30 HLDA 31 HOLD Prof. Fayez F. M. El-Sousy Hardware Specifications Microprocessor 8086/8088 In Min Mode: (24) INTA INTerrupt Acknowledge Active low output signal Inform interrupt controller that an interrupt has occurred And the vector number is available on the lower 8 lines of the data bus. (25) ALE – Address Latch Enable – Active high output signal Indicate that a valid address is available on the external address bus Prof. Fayez F. M. El-Sousy Hardware Specifications Microprocessor 8086/8088 In Min Mode: (26) DEN – Data Enable – Active low output signal Enable 74LS245, which allows isolation of the CPU from system Bus (27) DT/R – Data Transmit Receive – Active low output signal Used to control the Data Direction of data flow through 74LS245 tranceiver Prof. Fayez F. M. El-Sousy Hardware Specifications Microprocessor 8086/8088 In Min Mode: (26) DEN – Data Enable – Active low output signal Enable 74LS245, which allows isolation of the CPU from system Bus (28) IO/M (8088) or IO/M (8086) Memory or Input/output Indicate whether address bus is accessing memory or input / output device See the difference between 8088 and 8086 Prof. Fayez F. M. El-Sousy Hardware Specifications Microprocessor 8086/8088 In Min Mode: (29) WR Write Active low output signal Indicating that Data on the bus is being written to memory or I/O device (30) HLDA – Hold Acknowledge – Active high o/p signal used after HOLD. Indicate that CPU allows to the DMA to Use buses. Prof. Fayez F. M. El-Sousy Hardware Specifications Microprocessor 8086/8088 In Min Mode: (31) HOLD – Hold – Active high input from DMA controller Indicates that device requesting to control the local buses SSO – Status Line – For 88 only, an output signal that can be used along with the IO/M and DT/R to decode the status of the current bus cycle. Prof. Fayez F. M. El-Sousy Hardware Specifications Microprocessor 8086/8088 In Min Mode: SSO – Status Line – Prof. Fayez F. M. El-Sousy Hardware Specifications Microprocessor 8086/8088 In Min Mode: For the 8088/8086 in min mode some control signal must be generated using logic gate. In max mode these signal are provided by the 8288 88/86 in min mode provides 3 signals RD, WR, and IO/M or M/IO Using these 3 signal 4 important signal must be generated. Prof. Fayez F. M. El-Sousy Hardware Specifications Microprocessor 8086/8088 In Min Mode: These signals are shown in the following table: RD 0 1 0 1 0 Prof. Fayez F. M. El-Sousy WR 1 0 1 0 0 IO/M 0 0 1 1 X Signal MEMR MEMW IOR IOW Never Happened Hardware Specifications Microprocessor 8086/8088 In Max Mode: Some control signal are generated externally by the 8288 bus controller Some pins are used for new features available only for Max Mode Mostly used when CPU is used with Math Coprocessor IBM PC/XT and compatible use 8088, 8086 with 8087 coprocessor Prof. Fayez F. M. El-Sousy Hardware Specifications Microprocessor 8086/8088 In Max Mode: (24 and 25) QS0 and QS1 – Queue Status – Give information to the system about the Queue inside µp at any given time In IBM PC these pins are connected to 8087 to synchronize it with 8088 The following table describe their function Prof. Fayez F. M. El-Sousy Hardware Specifications Microprocessor 8086/8088 In Max Mode: (26, 27 and 28) So , S1 and S2 Status signal Connected to 8288 which will use them to produce all control signal such as those shown in table Prof. Fayez F. M. El-Sousy Hardware Specifications Microprocessor 8086/8088 In Max Mode: (29 ) LOCK Pin Active low o/p signal Used to prevent other processor or devices from gaining control on the buses Activated by LOCK prefix in the instruction of the assembly program (30 , 31 ) RQ / GT0 and RQ / GT1 request Grant Bidirectional Lines Allow other processors to gain control on the bus In IBM PC, RQ / GT0 is connected to high making it disabled Prof. Fayez F. M. El-Sousy and RQ / GT1 Is connected to 8087 Hardware Specifications Microprocessor 8086/8088 CLOCK GENERATOR (8284A): An 18-pin chip. Not only provide the clock and synchronization for the microprocessor, but also provides the READY signal for the insertion of WAIT states into the CPU bus cycle. Input Pins RES (Reset In): from power supplier X1 and X2 (Crystal In): the crystal frequency must be 3 times the desired frequency for the microprocessor. For IBM PC, 14.31818 MHz (max 24 MHz) RDY1 and AEN1: provide a Ready signal to the µP, which will insert a WAIT state to the CPU read/write cycle. Prof. Fayez F. M. El-Sousy RDY2 and AEN2: For multiprocessor systems. Hardware Specifications Microprocessor 8086/8088 CLOCK GENERATOR (8284A): Output Signals RESET: reset signal to the 8086/88 OSC (oscillator): provide to the expansion slot. CLK (clock): 1/3 of the OSC or EFI input, with a duty cycle of 33%. In IBM PC, OSC = 14.31818 MHz, so CLK = 4.772776 MHz PCLK: one-half of CLK (1/6 of crystal) with duty cycle of 50% and is TTL compatible. Provide to 8253 Timer to generate speaker tones READY: connect to READY input of CPU to insert Prof. Fayez F. M. El-Sousy WAIT state Hardware Specifications Microprocessor 8086/8088 CLOCK GENERATOR (8284A): The 8284 chips serves three purposes: Generates the main clock (CLK) for the processor (fc/3 with 33% duty cycle) and the clock for the peripheral devices (fc/5). Provides the Reset pulse according to the state of the RC circuit connected at the RES input. Provides the Ready signal to insert wait states whenever the processor is accessing slow memory or peripheral I/O ports. Prof. Fayez F. M. El-Sousy Hardware Specifications Microprocessor 8086/8088 CLOCK GENERATOR (8284A): This section describes the 8484A clock generator and the RESET signal. signal also introduces the READY signal for 8086/8088 With no clock generator, many circuits would be required to generate the clock (CLK). 8284A provides the following basic functions: clock generation; RESET & READY synch TTL-level peripheral clock signal Prof. Fayez F. M. El-Sousy Hardware Specifications Microprocessor 8086/8088 The pin-out of the 8284A clock generator Prof. Fayez F. M. El-Sousy Hardware Specifications Microprocessor 8086/8088 The pin-out of the 8284A clock generator CSYNC (clock synchronization) This active-high signal It is used to allow several 8284 chips to be connected together and synchronized. The IBM PC only uses one 8284; therefore, this pin is connected to low. Prof. Fayez F. M. El-Sousy Hardware Specifications Microprocessor 8086/8088 The pin-out of the 8284A clock generator PCLK (peripheral clock) This frequency is one-half of CLK (or one-sixth of the crystal) with a duty cycle of 50% and is TTL compatible. In the IBM PC this 2.386383 MHz is provided to the 8253 timer to be used to generate speaker tones, and other functions. Prof. Fayez F. M. El-Sousyfunctions Hardware Specifications Microprocessor 8086/8088 The pin-out of the 8284A clock generator RDY1 and AEN1 RDY1 is active high and AEN1 (address enable) is active low. They are used together to provide a ready signal to the microprocessor, which will insert a WAIT state to the CPU read/write cycle. In the IBM PC, RDY1 is connected to DMAWAIT and AEN1 is connected to RDY/WAIT. They allow the wait state to be inserted either by the CPU or by DMA. Prof. Fayez F. M. El-Sousy Hardware Specifications Microprocessor 8086/8088 The pin-out of the 8284A clock generator READY This signal is connected to READY of the CPU. In the IBM PC it is used to signal the 8088 to indicate if the CPU needs to insert a wait state due to the slowness of the devices that the CPU is trying to contact. Prof. Fayez F. M. El-Sousy Hardware Specifications Microprocessor 8086/8088 The pin-out of the 8284A clock generator RDY2 and AEN2 These function exactly like RDY1 and AEN1. These extra RDY and AEN signals are provided to allow for a multiprocessing system. It allows other general-purpose CPUs such as the 8088/8086 to gain control over the buses. In the IBM PC, RDY2 is connected to low, AEN2 is connected to high, which permanently disables this function since there is only one 8088/8086 microprocessor in the system. In cases of multiprocessor systems, these signals are used to coordinate access over the buses by different Prof. Fayez F. M. El-Sousy CPUs Hardware Specifications Microprocessor 8086/8088 The pin-out of the 8284A clock generator CLK (clock) This is an output clock frequency equal to one-third of the crystal oscillator, or EFI input frequency, with a duty cycle of 33%. This is connected to the clock input of the 8088/86 and all other devices that must be synchronized with the CPU. In the IBM PC it is connected to pin 19 of the 8088 microprocessor and other circuitry under the CLK88 label. This frequency, 4.772776 MHz (14.31818 divided by 3), is the processor frequency on which all of the timing calculations of the Prof. Fayez F. M. El-Sousy memory and I/O cycle are based. Hardware Specifications Microprocessor 8086/8088 The pin-out of the 8284A clock generator RESET This is an active-high signal that provides a RESET signal to the 8088/86 microprocessor. It is activated by the RES input signal discussed earlier. Prof. Fayez F. M. El-Sousy Hardware Specifications Microprocessor 8086/8088 The pin-out of the 8284A clock generator RES (reset in) This is an input active-low signal to generate RESET. In the IBM PC, it is connected to the power-good signal from the power supply. When the power switch in the IBM PC is turned on, assuming that the power supply is good, a low signal is provided to this pin and the 8284 in turn will activate the RESET pin, forcing the 8088/86 to reset; then the microprocessor takes over. This is called Prof. Fayez F. M. El-Sousy a cold boot. boot Hardware Specifications Microprocessor 8086/8088 The pin-out of the 8284A clock generator OSC (oscillator) This provides a clock frequency equal to the crystal oscillator and it is TTL compatible. Since the IBM crystal oscillator is 14.31818 MHz, OSC will provide this frequency to the expansion slot of the IBM PC. Prof. Fayez F. M. El-Sousy Hardware Specifications Microprocessor 8086/8088 The pin-out of the 8284A clock generator F/C (frequency/clock select) This pin provides an option for the way the clock is generated. If connected to low, the clock is generated by the 8284 with the help of a crystal oscillator. If it is connected to high, it expects to receive clocks at the EFI pin. Since the IBM PC uses a crystal, this pin is connected to Prof. Fayez F. M. El-Sousy low. Hardware Specifications Microprocessor 8086/8088 The pin-out of the 8284A clock generator EFI (external frequency in) External frequency is connected to this pin if F/C has been connected to high. In the IBM PC this is not connected since a crystal is used instead of an external frequency generator. In some cases (such as the Turbo PC), this pin is used to provide clock frequency in Prof. Fayez F. M. El-Sousy place of XI and X2. Hardware Specifications Microprocessor 8086/8088 The pin-out of the 8284A clock generator ASYNC This is called ready synchronization select. An active low is used for devices that are not able to adhere to the very strict RDY setup time requirement. In the IBM PC this is connected to low, making the timing design of the system easier with slower logic gates. Prof. Fayez F. M. El-Sousy Hardware Specifications Microprocessor 8086/8088 The pin-out of the 8284A clock generator X1 and X2 (crystal in) XI and X2 are the pins to which a crystal is attached. The crystal frequency must be 3 times the desired frequency for the microprocessor. The maximum crystal for the 8284A is 24 MHz and 30 MHz for the 8284A-1. The IBM PC is connected to a crystal of 14.31818 MHz. For some turbo compatibles, it is 24 Prof. Fayez F. M. El-Sousy MHz. Hardware Specifications Microprocessor 8086/8088 The internal block diagram of the 8284A clock generator Prof. Fayez F. M. El-Sousy Hardware Specifications Microprocessor 8086/8088 Operation of the Clock Section of the 8284A clock generator Crystal oscillator has two inputs: X1 and X2. if a crystal is attached to X1 and X2, the oscillator generates a square-wave signal at the same frequency as the crystal The square-wave is fed to an AND gate & an inverting buffer to provide an OSC output. The OSC signal is sometimes used as an EFI input to other 8284A circuits in a system. The following Figure shows how an 8284A is connected to Prof. Fayez F. M. El-Sousy the 8086/8088. Hardware Specifications Microprocessor 8086/8088 The clock generator (8284A) and the 8086 and 8088 microprocessors illustrating the connection for the clock and reset signals. A 15 MHz crystal provides the 5 MHz clock for the microprocessor Prof. Fayez F. M. El-Sousy Hardware Specifications Microprocessor 8086/8088 Operation of the Reset Section of the 8284A clock generator The reset section of 8284A consists of a Schmitt trigger buffer and a D-type flip-flop. the D-type flip-flop ensures timing requirements of 8086/8088 RESET input are met This circuit applies the RESET signal on the negative edge (1-to-0 transition) of each clock. 8086/8088 microprocessors sample RESET at the positive edge (0-to-1 transition) clocks. thus, this circuit meets 8086/8088 timing requirements Prof. Fayez F. M. El-Sousy Memory Interface Microprocessor 8086/8088 Two basic types: ROM: Read-only memory RAM: Read-Write memory Four commonly used memories: ROM Flash (EEPROM) Static RAM (SRAM) Dynamic RAM (DRAM) Prof. Fayez F. M. El-Sousy Memory Interface Microprocessor 8086/8088 The data pins are typically bi-directional in readwrite memories. The number of data pins is related to the size of the memory location. For example, an 8-bit wide (byte-wide) memory device has 8 data pins. Each memory device has at least one chip select (CS) or chip enable (CE) or select (S) pin that enables the memory device. This enables read and/or write operations. If more than one are present, then all must be 0 in order to perform a read or write. Prof. Fayez F. M. El-Sousy Memory Interface Microprocessor 8086/8088 SRAMs SRAMs used for caches have access times as low as 10ns. DRAMs SRAMs are limited in size (up to about 128Kb). DRAMs are available in much larger sizes, e.g., 64M X 1. DRAMs MUST be refreshed every 2 to 4 ms. Since they store their value on an integrated capacitor that loses charge over time. Prof. Fayez F. M. El-Sousy Memory Interface – Address Decoding Microprocessor 8086/8088 Address Decoding In order to attach a memory device to the microprocessor, it is necessary to decode the address sent from the microprocessor. Decoding makes the memory function at a unique section or partition of the memory map. Without an address decoder, only one memory device can be connected to a microprocessor, which would make it virtually useless. Prof. Fayez F. M. El-Sousy Memory Interface – Address Decoding Microprocessor 8086/8088 Address Decoding The processor can usually address a memory space that is much larger than the memory space covered by an individual memory chip. In order to splice a memory device into the address space of the processor, decoding is necessary. For example, the 8088 issues 20-bit addresses for a total of 1MB of memory address space. The BIOS on a 2716 EPROM has only 2KB of memory and 11 address pins. A decoder can be used to decode the additional 9 address pins and allow the EPROM to be placed in any 2KB section Prof. Fayez F. M. El-Sousy of the 1MB address space. Memory Interface – Address Decoding Microprocessor 8086/8088 Address Decoding- Why Decode Memory? The 8088 has 20 address connections and the 2716 EPROM has 11 connections. The 8088 sends out a 20-bit memory address whenever it reads or writes data. because the 2716 has only 11 address pins, there is a mismatch that must be corrected The decoder corrects the mismatch by decoding address pins that do not connect to the memory component. Prof. Fayez F. M. El-Sousy Memory Interface – Address Decoding Microprocessor 8086/8088 Simple NAND Gate Decoder When the 2K × 8 EPROM is used, address connections A10–A0 of 8088 are connected to address inputs A10–A0 of the EPROM. the remaining nine address pins (A19–A11) are connected to a NAND gate decoder The decoder selects the EPROM from one of the 2K-byte sections of the 1M-byte memory system in the 8088 microprocessor. In this circuit a NAND gate decodes the memory address, as seen in the following Figure. Prof. Fayez F. M. El-Sousy Memory Interface – Address Decoding Microprocessor 8086/8088 A simple NAND gate decoder that selects a 2716 EPROM for memory location FF800H–FFFFFH Prof. Fayez F. M. El-Sousy Memory Interface – Address Decoding Microprocessor 8086/8088 Simple NAND Gate Decoder for memory location FF800H–FFFFFH To determine the address range that a device is mapped into: Prof. Fayez F. M. El-Sousy Memory Interface – Address Decoding Microprocessor 8086/8088 Memory Locations: FF800H-FFFFFH A19 Common part makes the Prof. Fayez F. M. El-Sousy 9 selector bits A11 A10 A0 1111 1111 1000 0000 0000 = F0000H 1111 1111 1111 1111 1111 = F1FFFH Memory Interface – Address Decoding Microprocessor 8086/8088 Simple NAND Gate Decoder If the 20-bit binary address, decoded by the NAND gate, is written so that the leftmost 9 bits are 1s and the rightmost 11 bits are don’t cares (X), the actual address range of the EPROM can be determined. a don’t care is a logic 1 or a logic 0, whichever is appropriate Because of the excessive cost of the NAND gate decoder and inverters often required, this option requires an alternate be found. NAND gate decoders are not often used. Rather the 3to-8 Line Decoder (74LS138) is more common. Prof. Fayez F. M. El-Sousy Memory Interface – Address Decoding Microprocessor 8086/8088 The 3-to-8 Line Decoder (74LS138) The 74LS138 3-to-8 line decoder and function table. Prof. Fayez F. M. El-Sousy Memory Interface – Address Decoding Microprocessor 8086/8088 A circuit that uses eight 2764 EPROMs for a 64K × 8 section of memory in an 8088 Prof. Fayez F. M. El-Sousy microprocessor-based system. The addresses selected in this circuit are F0000H–FFFFFH. Memory Interface – Address Decoding Microprocessor 8086/8088 Module 0 1111 000X XXXX XXXX XXXX 1111 0000 0000 0000 0000 = F0000H to 1111 0001 1111 1111 1111 = F1FFFH Module 7 1111 111X XXXX XXXX XXXX 1111 1110 0000 0000 0000 = FE000H to 1111 1111 1111 1111 1111 = FFFFFH A circuit that uses eight 2764 EPROMs for a 64K × 8 section of memory in an 8088 Prof. Fayez F. M. El-Sousy microprocessor-based system. The addresses selected in this circuit are F0000H–FFFFFH. Memory Interface – Address Decoding Microprocessor 8086/8088 In this circuit, a three-input NAND gate is connected to address bits A19–A17. When all three address inputs are high, the output of this NAND gate goes low and enables input G2B of the 74LS138. Input G1 is connected directly to A16. In order to enable this decoder, the first four address connections (A19–A16) must all be high. Address inputs C, B, and A connect to microprocessor address pins A15–A13. These three address inputs determine which output pin goes low and which EPROM is selected whenever 8088 outputs a memory address within this range to the memory system. Prof. Fayez F. M. El-Sousy Memory Interface – Address Decoding Microprocessor 8086/8088 The 3-to-8 Line Decoder (74LS138) Example: A19………………………………. A0 1111 XXXX XXXX XXXX XXXX or 1111 0000 0000 0000 0000 = F0000H to 1111 1111 1111 1111 1111 = FFFFFH Prof. Fayez F. M. El-Sousy Memory Interface – Address Decoding Microprocessor 8086/8088 The 3-to-8 Line Decoder (74LS138) Example: CBA 1111 000X XXXX XXXX XXXX or 1111 0000 0000 0000 0000 = F0000H to 1111 0001 1111 1111 1111 = F1FFFH Prof. Fayez F. M. El-Sousy Memory Interface – Address Decoding Microprocessor 8086/8088 The 3-to-8 Line Decoder (74LS138) Example: CBA 1111 001X XXXX XXXX XXXX or 1111 0010 0000 0000 0000 = F2000H to 1111 0011 1111 1111 1111 = F3FFFH Prof. Fayez F. M. El-Sousy Memory Interface – Address Decoding Microprocessor 8086/8088 The 2-to-4 Binary Decoders Prof. Fayez F. M. El-Sousy Memory Interface – Address Decoding Microprocessor 8086/8088 The 2-to-4 Binary Decoders The binary inputs A and B determine which output line from D0 to D3 is "HIGH" at logic level "1" while the remaining outputs are held "LOW" at logic "0" so only one output can be active (HIGH) at any one time. Therefore, whichever output line is "HIGH" identifies the binary code present at the input, in other words it "decodes" the binary input and these types of binary decoders are commonly used as Address Decoders in microprocessor memory applications. Prof. Fayez F. M. El-Sousy Memory Interface – Address Decoding Microprocessor 8086/8088 The Dual 2-to-4 Line Decoder (74LS139) Prof. Fayez F. M. El-Sousy Memory Interface – I/O Interface Microprocessor 8086/8088 Programmable Peripheral Interface (PPI) 8255 The 82C55 is a popular interfacing component, that can interface any TTL-compatible I/O device to the microprocessor. It is used to interface to the keyboard and a parallel printer port in PCs (usually as part of an integrated chipset). Requires insertion of wait states if used with a microprocessor using higher that an 8 MHz clock. PPI has 24 pins for I/O that are programmable in groups of 12 pins and has three distinct modes of operation. In the PC, an 82C55 or its equivalent is decoded at I/O ports 60H-63H. Prof. Fayez F. M. El-Sousy Memory Interface – I/O Interface Microprocessor 8086/8088 Prof. Fayez F. M. El-Sousy Memory Interface – I/O Interface Microprocessor 8086/8088 Prof. Fayez F. M. El-Sousy Memory Interface – I/O Interface Microprocessor 8086/8088 Programmable Peripheral Interface (PPI) 8255 The 8255 Programmable Peripheral Interface (PPI) is a 40-pin DIP IC that provides 3 programmable I/O ports, A, B, and C. How are is it programmable? Configure each port as input or output Different modes of operation You must initialize the PPI via software commands Send a control byte to the device’s control register port Prof. Fayez F. M. El-Sousy Memory Interface – I/O Interface Microprocessor 8086/8088 Programmable Peripheral Interface (PPI) 8255 PA0 – PA7: Port A / All / input/output/bidirectional PB0 – PB7: Port B / All / input/output PC0 – PC7: Port C / All / input/output Can be split into two parts: Upper (PC7 – PC4) and Lower (PC3 – PC0). Each can be used for input or output. Any of PC0 – PC7 can be programmed. RD and WR: control signal input to 8255 IOR and IOW in peripheral I/O MEMR and MEMW in memory-mapped I/O Prof. Fayez F. M. El-Sousy Memory Interface – I/O Interface Microprocessor 8086/8088 Programmable Peripheral Interface (PPI) 8255 RESET: Active high input signal to 8255 Used to clear the internal control register When activated, all ports are initialized as input ports. Usually connect to the RESET output of the system bus or ground A0, A1, and CS CS selects the entire chip, A0 and A1 select the specified port Used to access port A, B, C, CS A1 A0 Select or control register 0 0 0 Port A 0 0 1 Port B 0 1 0 Port C Prof. Fayez F. M. El-Sousy 0 1 1 Control Reg. 1 x x Not Selected Memory Interface – I/O Interface Microprocessor 8086/8088 Programmable Peripheral Interface (PPI) 8255 Control Word D7 D6 D5 D4 D3 D2 D1 D0 Group B Port C Lower PC3-PC0 1 = input, 0 = output Port B 1 = input, 0 = output Mode Selection 0 = Mode0, 1 = Mode1 Group A Port C Upper PC7-PC4 1 = input, 0 = output Port A 1 = input, 0 = output Mode Selection 00 = Mode0, 01 = Mode1 1x = Mode 2 Prof. Fayez F. M. El-Sousy 1 = I / O Mode 0 = BSR Mode Memory Interface – I/O Interface Microprocessor 8086/8088 PPI 8255 Mode Selection Mode 0: simple I/O Any ports: A, B, CL, CU. No control of individual bits Mode 1: I/O (ports A and B) with handshaking (port C) Synchronizes communication between an intelligent device (printer) Mode 2: Bi-directional I/O with handshaking Port A: bidirectional I/O with handshaking through port C Port B: Simple I/O or in handshake mode 1 BSR Mode: Bit set/reset Prof. Fayez F. M. El-Sousy Only the individual bits on Port C can be programmed
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