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VLSI-SATA 2015 Program schedule
Tutorials – Thursday, Jan 8, 2015
From
To
08.30
09.30
09.30
11.30
11.30
11.45
11.45
13.15
13.00
14.00
14.00
15.30
15.30
15.45
15.45
16.30
Tutorial 1
Tutorial 2
Registration
Digital Signal Processing - A Modern Perspective - Prof.
Gene Frantz, Rice University, USA, Dr. C.P. Ravikumar,
Texas Instruments, Bengaluru and Aravindhan K.,
StarCom Information Technology Ltd., India
Validation and Verification of Automotive Embedded Systems Dr. Subramaniam Ganesan, Oakland University, Rochester, USA
Tea/coffee break
Digital Signal Processing - A Modern Perspective continued
Input-output pads – purpose and circuit design aspects - Lavanya
Nirikhi, Vani Deshpande and Hari Anand Ravi, Intel, Bengaluru
Lunch
Digital Signal Processing - A Modern Perspective –
continued.
Introduction to Accellera Transaction Level Modeling (TLM) 2.0 –
Aravinda Thimmapuram, Intel, Bengaluru
Tea/coffee break
Digital Signal Processing - A Modern Perspective continued
Introduction to Accellera Transaction Level Modeling (TLM) 2.0 Continued
Conference: Day 1, Friday, Jan 9, 2015
Plenary Session
From
To
Duration
Title
08.00
09.00
60
Registration
09.00
09.30
30
Inauguration (Lighting of the lamp, Invocation, Welcome address, scope of the conference, Chief guest address,
vote of thanks, introduction of keynote 1 and 2)
09.30
09.50
20
Inaugural Keynote: A “new” perspective of computer architecture by Gene Frantz, Rice University, Houston
09.50
10.30
40
Keynote 1: "Intelligent and Invisible - What is next for Technology" by Guru Ganesan, ARM, Bengaluru
10.30
11.00
30
Photo session and tea/coffee break
11.00
12.00
60
Keynote 2: Influence of Emerging Devices in Revitalizing Electronic Systems Design by Vijay Narayanan,
Pennsylvania State University
12.00
13.00
60
Panel Discussion: More of Moore and More than Moore – competing or complimenting? Panellists: TBD
13.00
14.00
60
Networking over lunch
Technical Tracks: Each paper is of 20 min duration (15 min presentation and 5 min Q&A).
From
To
System
Architecture
Technology
Application
Chair -
Chair -
Chair -
Chair -
14.00
14.20
Sys1.1: Cryptanalysis of
Hummingbird Algorithm with
Improved Security and
Throughput - Harikrishnan T
and C Babu, Amrita University
Arc1.1: Design of Low
Power and High Speed
Carry Select Adder
Using Brent Kung
Adder - Pallavi Saxena,
Kautilya Institute of
Technology
Tec1.1: Low power and High
performance MOSFET - Veera
Boopathy E, Raghul G and
Karthick K, VSB Engineering
College
App1.1: Software Power
Optimization in a
Microcontroller-based solution
for Filtering Noise from Audio
Recordings - Rajat Goyal and
Ravikumar C.P., Chitkara
University
14.20
14.40
Sys1.2: On-Chip Comparison
based Secure Output
Response Compactor for Scanbased Attack Resistance Sudeendra Kumar K, Kalpesh
Lodha, Sauvagya Sahoo and
Kamalakanta Mahapatra, NIT
Rourkela
Arc1.2: Design and
Implementation of Fast
Floating Point
Multiplier Unit Sunesh V and
Sathishkumar P, Amrita
University
Tec1.2: Design of an Efficient
CNTFET using Optimum
Number of CNT in Channel
Region for Logic Gate
Implementation - Rasmita
Sahoo, Subhendu Kumar
Sahoo and Krishna Chaitanya
Sankisa, BITS Hyderabad
App1.2: A Low Power Low
Frequency Oscillator for Driving
Electrolarynx - M
Madhushankara, Somashekhara
Bhat, Keerthana Prasad and
Vishnu Satya Chaitanya, Manipal
University
14.40
15.00
Sys1.3: Improvement in Error
Resilience for Compressed
VLSI Test Data using The
Hamming Code Based
Technique - Usha Mehta,
Nirma University
Arc1.3: Design of
Optimized Binary and
BCD Adders - A N
Nagamani, S Ashwin
and Agrawal Vinod
Kumar, PES University
Tec1.3: mFPGA Design based
on Hybrid CMOS-Memristor
Technology - Madankumar
Sampath, Pravin Mane and
Ramesha C.K., BITS Goa
App1.3: A Novel On-Chip SelfTesting Signature Register for
Low Cost Manufacturing Test Kalpesh Lodha, Sudeendra
Kumar and Kamalakanta
Mahapatra, NIT Rourkela
15.00
15.20
Networking over Tea/coffee
Chair -
Chair -
Chair -
Chair -
15.20
15.40
Sys1.4: Automatic synthesis of
inter-heterogeneousprocessor communication
implementation for
programmable system-on-chip
- Yuki Ando, Yukihito Ishida,
Shinya Honda, Hiroaki Takada
and Masato Edahiro, Nagoya
University, Japan
Arc1.4: Merged Switch
Allocation and Transversal
with Dual Layer Adaptive
Error Control for Networkon-Chip Switches - Havisha
Kalwad, Neeharika
Sompalli, Divya Songa,
Vinodhini M and Murty N S
(Amrita University)
Tec1.4: A 0.3V , 12nW,
47fJ/conv, Fully Digital
Capacitive Sensor Interface
in 0.18um CMOS - Ankit
Savaliya and Biswajit
Mishra, DAIICT
App1.4: Analytical Insight for
CFG Generation for
Superscalar Simulator Design
for RISC Architecture - Harsh
Arora, VIT Vellore
15.40
16.00
Sys1.5: HMFPCC: - HybridMode Floating Point
Conversion Co-processor Aneesh R, Vinayak Patil, Sobha
Pm and A David Selvakumar,
CDAC
Arc1.5: Reliable Router
Architecture with Elastic
Buffer for NoC Architecture
- Roshna Louis, M Vinodhini
and Murty N S (Amrita
University)
Tec1.5: A Quadratic
Approach for Routability
Driven Placement Design:
Initial Insight - Harsh Arora,
VIT Vellore
App1.5: Improved Single Image
and Video Dehazing Using
Morphological Operation Apurva Kumari, Sidharth
Sahdev and S.K Sahoo, BITS
Hyderabad
Banquet Session (Hotel Octave, Sarjapur Road)
18.30 to 19.30: Cultural Programme:
19.30 to 21.30: Banquet dinner
End of Day 1 program
Day 2, Saturday, Jan 10, 2015
Plenary Session
From
To
Duration
Title
08.00
09.00
60
Registration
09.00
10.00
60
Keynote 3: SuSi: Supercomputing on Silicon by Prof. Nandy, SERC, IISc, Bangalore
10.00
11.00
60
Keynote 4: TBD by Gopal Krishna, Maxim Integrated
11.00
11.30
30
Networking over Tea/coffee
Technical Tracks: Each paper is of 20 min duration (15 min presentation and 5 min Q&A).
From
To
System
Architecture
Technology
Application
Chair -
Chair -
Chair -
Chair -
11.30
11.50
Sys2.1: Implementation of
NB PHY Transceiver of IEEE
802.15.6 WBAN on FPGA Priya Mathew, Lismi
Augustine, Deepak
Kushwaha, A. D.
Selvakumar and V
Desalphine, CDAC
Arc2.1: Sub-1V ultra lowpower voltage reference Abbas C Mohammed,
Abhishek Shukla and Kavitha
R.K., NIT Tiruchirapalli
Tec2.1: New fault model analysis
for embedded SRAM cell for DSM
technologies using parasitic
extraction method - Parvathi
Muddapu, N Vasantha and K
Satya Prasad, SECTW Hyderabad
App2.1: Design and
Implementation of an LCD
Controller IP Core Using
SystemVerilog - Mithuna
Chandran, Libin T.T,
Krishnakumar Rao and Biju
C Oommen, CDAC
11.50
12.10
Sys2.2: A Study on Detailed
Placement for FPGAs Sudipta Paul, Rana Das and
Pritha Banerjee, Indian
Statistical Institute
Arc2.2: An 8-b 250Msample/s Power Optimized
Pipelined ADC in 0.18-um
CMOS - Manas Kumar Hati
and Tarun K. Bhattachayya,
IIT Kharagpur
Tec2.2: Stability Investigation for
1R-2W and 2R-2W Register File
SRAM Bit Cell using FinFET in
Subthreshold Region - Sreyas
Mohan, Kirti Pande and N S
Murty, Amrita University
App2.2: A Real Time
Watermarking of
Grayscale Images without
altering it’s Content Sakthivel Sm and Dr. Ravi
Sankar A, VIT Chennai
12.10
12.30
12.30
13.30
Sys2.3: Performance
Analysis of Various
scheduling algorithms using
FPGA Platforms - Liyaqat
Nazir and Roohie Naaz Mir,
NIT Srinagar
Arc2.3: A PFD and Charge
Pump Switching Circuit to
Optimize the Output Phase
Noise of the PLL in 0.13-μm
CMOS - Manas Kumar Hati
and Tarun K. Bhattacharyya,
IIT Kharagpur
Tec2.3: A Novel Delay & Quantum
Cost Efficient Reversible
Realization of 2i x j Random
Access Memory - Alak Majumder,
Prasoon Lata Singh, Nikhil Mishra
- Abir Jyoti Mondal and Barnali
Chowdhury, NIT Arunachala
Pradesh
App2.3: Design of Any
Codeword Length Parallel
Long BCH Encoders with
the help of An Efficient CUtility - Sagar Koorapati
and Surya Prakash, Ineda
Systems
Networking over lunch
Chair -
Chair -
Chair -
Chair -
13.30
13.50
Sys2.4: FPGA Prototyping of
Energy Dispersal and
Improved Error Efficiency
Techniques for DVBSatellite Standard - Rakesh
Palisetty, Vibhooti Kumar
Sinha, Saugata Mallick and
Kailash Chandra Ray, IIT
Patna
Arc2.4: Design Space Exploration
of RISC Architectures using
Retargetability - Harsh Arora, VIT
Vellore
Tec2.4: Quantum Cost
Realization of New Reversible
Gates with Transformation
Based Synthesis Technique Jayashree Hv, Dr. V.K.
Agrawal and Shishir Bhardwaj
– PES University
App2.4: Design And
Implementation of Test
Harness for Device drivers
in SOC on Mobile
Platforms - Harsh Arora,
VIT Vellore
13.50
14.10
Sys2.5: A Proposal for
Source Separation of
Ground Borne Vibration
Signals and Its FPGA
Implementation - Geethu
RS, Krishna Kumar M and
Sudhish N George, Amrita
University
Arc2.5: An Efficient Method for
Testing of L1 Cache Module in
Tiled CMPs Architecture at Low
Cost - Mousumi Saha, Subhra and
Biplab Sikdar Sikdar, NIT
Durgapur
Tec2.5: Design and Analysis
of a 2.4 GHz Fully Integrated
1.8V Power Amplifier in
TSMC 180nm CMOS RF
Process for Wireless
Communication - Santsoh
Patil and Rajendra Kanphade,
SSGMCE Shegaon
App2.5: Power Efficient
Implementation of BitParallel Unrolled CORDIC
Structures for FPGA
Platforms - Burhan
Khurshid and Roohie Naaz
Mir, NIT Srinagar
14.10
14.30
Sys2.6: Area and Frequency
optimized 1024 point Radix2 FFT Processor on FPGA Vinay Kumar Maddala,
CDAC
Arc2.6: Optimization of row
decoder for 128x128 6T SRAMs Vipul Bhatnagar, Chandni Attri
and Sujata Pandey, Amity
University
Tec2.6: Design of Ultra Low
Power Flash ADC using TMCC
& Bit Referenced Encoder in
180nm Technology - Aditi
Kar, Alak Majumder, Abir J
Mondal and Nikhil Mishra,
TIT Agartala
App2.6: FPGA
Implementation of an
Advanced Encoding and
Decoding Architecture of
Polar Codes - Mamatha
Oommen and Ravishankar
S, Amrita University
14.30
14.50
Sys2.7: Intermediate
Representation for
Heterogeneous Multi-Core:
a Survey - Meena Belwal
and Sudarshan TSB, Amrita
University
Arc2.7: High Performance VLSI
Architecture for 2-D DWT Using
Lifting Scheme - Mithun R and
Ganapathi Hegde, Amrita
University
Tec2.7: Functional testing
technique for microprocessor
interface board - Kurada
Rayudu, RCI-DRDO
App2.7: Architecture for
ASIC based, batteryless
multisource energy
harvesting system - L Vijay,
K.K Greeshma and N.S
Murty, Amrita University
14.50
15.10
Networking over Tea/coffee
15.10
15.30
Valedictory Function