ENGCONF26 Driving Technology Solutions A Cost Effective Approach for the Development of a Laminate VCO Platform in both GaAs and SiGe Process Technologies Ronan Brady, Shane Collins, Eoin Carey, Pierce Nagle, and Robert O’Leary M/A-COM Technology Solutions, 4 Eastgate Road, Little Island Cork, Ireland Abstract Over the last few decades GaAs based technologies have been the most cost effective solution for high power and high frequency applications in the RF industry. However, recently, GaAs has seen its presence challenged by Si based solutions, in particular by BiCMOS SiGe which now offers RF functionality at much lower cost. However, while SiGe based solutions offer lower TMC than those on GaAs, their maskset costs create a large barrier to entry into this technology. These costs soar when multiple design runs are considered. As a result the time to amortize the initial engineering and production masksets costs, incurred to develop a product, lengthens significantly. This paper details a general layout approach that facilitates the fabrication of an entire platform of VCOs via alterations to a single mask layer only. Therefore, for a given technology, successive production masksets can be generated by replacing just one mask layer from an existing maskset. Engineering masksets can also be compiled in a similar fashion. This approach offers considerable time and money savings for both GaAs, and to an even greater extent, SiGe based approaches and will enhance the feasibility of all future VCO design opportunities I. INTRODUCTION Foundry masksets are a significant expense during the development of any semiconductor based IC. This is especially true for Silicon based technologies. These technologies are typically mature and well established processes fabricated on larger semiconductor wafers. Hence they can provide both lower unit TMC and increased capacity for enhanced design complexity. While MPW services can lessen the maskset cost burden from an engineering design perspective, the production maskset cost can have a significant bearing on whether a design opportunity even passes the opportunity assessment stage of a product’s development cycle. The Laminate VCO consists of a varactor tuning flipchip IC and a negative resistance HBT flipchip IC, in GaAs and/or SiGe technology, mounted on a laminate resonator [1]. To date it has been experimentally shown that this concept offers a low cost “best in-class” phase noise VCO [2]. It also facilitates a mix & match of technologies, giving the customer a choice to trade-off between performance and cost. While the laminate approach also offers a certain degree of frequency customization using off-chip SMT components, this approach does have its limitations. In general, for a given pair of varactor and HBT flipchips, frequency adjustment is limited to +/-10%. Moreover other key VCO parameters, including phase noise and bandwidth, cannot be tuned without alterations to the flipchips. This has critical consequences for the manufacture of their associated production masksets: For any moderate change in VCO specification an entirely new production maskset would be required. In the context of replacing the existing platform of full MMIC VCOs with laminate VCOs using GaAs, it is estimated that a total of 16 masksets would be required at a total cost of $400k. This cost would rise to almost $2m for an exclusively SiGe based approach. This paper details a layout approach that facilitates the fabrication of an entire platform of VCOs via alterations to a single metal mask layer only. Therefore, for a given technology, successive production masksets can be generated by replacing just one mask layer from an existing maskset. Engineering masksets can also be compiled in a similar fashion. This approach offers considerable time and money savings for both GaAs and, to an even greater extent, SiGe based approaches and will enhance the feasibility of all future VCO design opportunities. COMPANY CONFIDENTIAL 1 ENGCONF26 Driving Technology Solutions II. VCO OPERATION There is a wide range of literature and academic textbooks [3] dedicated to both the theoretical and practical aspects of VCO design. The majority of this material is beyond the scope of this paper. However a brief synopsis of the VCO operation, specific to the architecture adopted by M/A-COM Tech, is essential before discussing the Metal Mask Approach. Fig. 1: M/A-COM Tech’s balanced VCO topology indicating the 2Fo tap-off point at the F0 virtual ground. Under normal large-signal operating conditions the two identical Clapp Oscillators shown in Fig. 1 operate 180° out of phase at the fundamental frequency (F0). This push-pull mode of operation at F0 leads to a virtual ground at the centre of the resonator transmission path (2L) connecting the base terminals of the back-to-back HBTs. At the same time nonlinear harmonics of the fundamental will also exist at this point, the most dominant of these being the second harmonic (2F0). As a consequence of the balanced topology the virtual node is also mirrored at the centre point between the pair of emitter capacitors C2. This node provides both a convenient tap-off point for 2F0 and good rejection of the fundamental, F0 [3]. This fundamental can be extracted (via a buffer) from a non-virtual ground node along the resonator or, alternatively, it may be coupled-off using an adjacent transmission line alongside the 2L resonator track. The VCO frequency is determined by the resonance frequency of the oscillator’s resonant loop which is essentially a series LC circuit of transmission line resonator inductances “2L” and capacitors C1\C2\C3. The capacitance C3 typically comprises of both constant and variable capacitors which are configured to obtain the desired oscillation frequency and bandwidth, while the gain of the negative resistance circuits are controlled specifically by C1 and C2. III. SIGE/GAAS LAMINATE VCO The Laminate VCO concept, first proposed in [4], is a low cost solution for the Point-to-Point market. It involves fabricating only the components that are most critical to VCO performance on semiconductor flipchip technology, and realising the remaining components using a combination of SMTs and/or metal interconnect on an underlying COMPANY CONFIDENTIAL 2 ENGCONF26 Driving Technology Solutions multi-layer laminate. The assembly diagram of a typical Laminate VCO is illustrated in Fig. 2. It includes a varactor flipchip containing all the required variable capacitor diodes for the VCO, a HBT flipchip containing the negative resistance core, high Q inductive resonator tracks on top metal laminate and finally a number of 0201 SMTs to complete the required VCO circuitry. The idea here was that with reduced semiconductor area and higher Q resonator tracks on laminate this design concept has the potential to improve both VCO phase noise performance and reduce the VCO’s TMC. The results from the first prototype of this design, namely a GaAs/GaAs Laminate constituting a GaAs Varactor and GaAs HBT Core, were presented in [2]. It exhibited “best-in-class” phase noise performance beating all purely MMIC based approaches on the same GaAs technology. More recent results from a SiGe/GaAs, constituting a SiGe core and GaAs Varactor, has demonstrated comparable phase noise performance to the GaAs/GaAs Laminate VCO but with further TMC reductions. As a result the SiGe/GaAs Laminate VCO was the chosen technology for the product development of this component. RF/2 Port Varactor Die VCO Core Die Vtune Port Inductive Transmission Lines RF Port Fig. 2: MACOM’s Laminate VCO Concept IV. METAL MASK APPROACH GAAS Compiling today’s customer requirements with MACOM’s existing family of MMICs VCO, the specifications cover frequency ranges from 5-15GHz and bandwidths from 500-1400MHz. As argued earlier, the engineering and production maskset costs for the development of an entire new platform of Laminate VCOs would be substantial. In fact, despite the laminate VCO’s enhanced flexibility which allows moderate frequency adjustments via laminate and/or SMT alterations, the entire platform would still require several unique masksets on both GaAs (+$25K/ea) and SiGe(+$120K/ea) technology to meet all the platform specifications. This presented a huge barrier and an improved approach was sought in terms of metal mask adjustability. The key idea was to layout both flipchips in such a way that they could each be reconfigured to operate to any VCO specification by changes to one mask layer only in their maskset. Successive engineering/production masksets can then be derived by replacing just this one mask layer in this maskset thereby providing considerable savings during any future VCOs product development. To realize this approach, the key VCO components that were critical to VCO performance, had to be determined. Then the required range and resolution of these components values had to be established from simulation and/or review of historical data. Finally the process technologies layer stack was carefully studied to determine the most appropriate layer to which Metal Mask Adjustability would be applied. The following two subsections discuss how the metal mask approach has been applied to the GaAs Varactor flipchip on GCS D1 and to the SiGe HBT core on IBM’s 5PAE processes. COMPANY CONFIDENTIAL 3 ENGCONF26 Driving Technology Solutions A. Metal Mask Approach on GaAs The typical layout for the varactor flipchip die on GCS’s 2µm D1 includes 3 pairs of back-2-back varactor diodes and a MIM capacitor (termed virtual node capacitor) tied to ground via adjacent Cu pillar bumps. As discussed earlier both are critical elements of the VCO’s operation as they constitute capacitors C3 and CNODE respectively in earlier simplified circuit diagram of Fig. 1. The varactors are used to set the frequency/bandwidth characteristics of the VCO, while the MIM node capacitor which creates optimum impedance at 2fo at the virtual node to enhance the overall balanced operation of the VCO circuit. (a) (b) (c) Fig. 3: ADS Momentum 3D & Layout plots of GaAs components employing metal mask approach: (a) A 5pF MiM Capacitor on GaAs, (b) A 5pF sized capacitor with 40% M2 (Blue) overlap reduction on M1(Green)=> 3pF. (c) An 18 finger varactor with 10 anode/cathode fingers disconnected/isolated => 8 finger varactor. The chosen adjustable layer on the GCS process was top metal M2. It acts as both the interconnection layer between circuit components and as the top electrode of the MiM capacitors. In the case of the virtual node MiM cap the footprint of the largest required capacitance value was first laid out. Variability in this capacitance was then achieved by peeling back the M2 overlap on the underlying M1 as illustrated in Fig. 3a and Fig. 3b. In terms of the varactors, just like the MiM capacitor, the largest required periphery was also laid out first i.e. 18 fingers of 150um x 10um (27000um2). The varactor periphery can then be adjusted by connecting in/out cathode/anode finger pairs to the common M2 flange at either end of the component as shown in Fig. 3c. This gives the design engineer a generous adjustment resolution of 1 finger or 1500um2 varactor periphery. The remaining components on the GaAs varactor flipchip include RF choke inductors and ESD structures. These are considered to be not critical to VCO operation and, hence, are left fixed. B. Metal Mask Approach on IBM’s SiGe The metal mask adjustable layout for the SiGe process contains a number of key VCO circuit components. These include the HBT biasing resistors which allow the design engineer to trade off VCO phase noise performance with power consumption as per Lesson’s equation [3]. They also include the capacitors C1, C2 & C3 as illustrated earlier in Fig.1. In the case of the input capacitor C3 the maximum required capacitance was determined to be 10.8pF from simulation. Just as in the case of the GaAs process, adjustments to a single metal layer can provide any value of capacitance up to 10.8pF. Capacitors C1 and C2 have been implemented in a similar fashion. A similar approach has been adopted for the resistors. In the case of the emitter resistor, the design engineer can select resistance values ranging from 4Ω to 36Ω with a 1Ω resolution. The pair of base bias resistors have also been implemented in a similar fashion providing adjustable resistances ranging from 30-300Ω with a 5Ohm resolution. V. CONCLUSION This paper has shown how all key VCO characteristics including frequency, bandwidth, phase noise, power and current consumption can be varied with just a single mask layer change. It highlighted that despite imposing certain layouts constraints on the GaAs/SiGe flipchip the design engineer still has the complete design flexibility to fabricate any circuit component values required to design/target an entire platform of laminate VCOs. The expected release COMPANY CONFIDENTIAL 4 ENGCONF26 Driving Technology Solutions dates for both SiGe and GaAs masksets that implement the proposed metal mask adjustability approach is September. ACKNOWLEDGEMENT The authors wish to acknowledge the assistance and support of the M/A-COM Engineering Conference Committee. REFERENCES [1] Shane Collins, Ronan Brady, Eoin Carey, and Pierce Nagle, "GaAs and SiGe Options Point-2-Point Laminate VCOs," 2013 Engineering Conference. [2] Shane Collins, Ronan Brady, Eoin Carey, and Pierce Nagle, "Laminate VCOs for Point-2-Point Applications," 2012 Engineering Conference. [3] A. Grebennikov, “RF and Microwave Transistor Oscillator Design” John Wiley & Sons, 2007. [4] Ronan Brady, Shane Collins, Eoin Carey, and Pierce Nagle, "High Frequency Laminate VCOs: A Feasibility Study," 2011 Engineering Conference. [5] R. E. Collin, Foundations for Microwave Engineering, New York: McGraw-Hill, 1966. COMPANY CONFIDENTIAL 5
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