9th International Workshop on Interconnection Network Architectures: On-Chip, Multi-Chip (INA-OCMC 2015) http://mpsoc.unife.it/~inaocmc/ Associated with the 10th HiPEAC Conference on High Performance and Embedded Architecture and Compilers 19-21 January 2015, Amsterdam, The Netherlands http://www.hipeac.net/2015/amsterdam/ Scalable interconnect architectures form the fabric that unifies future complex computing platforms. The interconnect architecture should be as high performance as the compute nodes, thus enabling the expected exponential growth in system concurrency. The number of nodes either on-chip or off-chip that need to communicate in modern embedded and HPC systems is constantly increasing. This trend poses significant challenges to the interconnection network designers that tackle a multidimensional problem involving hardware and software components such as network interfaces, switches, and communication library APIs. The INA-OCMC workshop focuses on the presentation of novel interconnect architectures, optical and electrical, for embedded MPSoCs/CMPs, Cloud/Datacenter, microservers and HPC systems. To emphasize both the fundamental impact of silicon photonic technologies on future system and interconnection network architectures and, conversely, the driving forces of practical and economically viable system-level design, requirements and constraints on the underlying technologies, this year the INAOCMC and SiPhotonics Workshops will be held in a federated fashion. We plan to organize joint keynote presentations and a panel discussion with experts from both fields on topics of interest to both communities. This way, we intend to foster the exchange of ideas and increase collaboration between these highly complementary workshops. The paper submission and review processes will, however, still be run independently by each workshop. We invite contributions of previously unpublished results on all aspects of emerging interconnect architectures, including but not limited to:  Multi-Chip interconnection networks, cluster interconnects  Networks-on-Chip  Communication architectures for 2,5 D and 3D stacked systems  Asynchronous interconnect designs  Interaction with memory hierarchy  Switch, buffering, and routing architectures  Flow control and congestion management in switching fabrics  Architectures for QoS support  Virtualization, SDN, OpenFlow, NFV  Impact of the interconnect on application performance  Topology exploration  Reconfigurable/Programmable interconnect components  Reliability, availability, fault tolerance  Programming models for communication-centric systems Submission and dates Submitted papers must represent original, previously unpublished, research that is not currently under review for any other workshop, conference or journal. All manuscripts will be reviewed by an international Program Committee and will be judged on correctness, originality, technical strength, significance, quality of presentation, and interest and relevance to the workshop attendees. The submission and review process will be handled electronically via EasyChair: https://www.easychair.org/conferences/?conf=inaocmc2015. Papers must be in PDF format and should include title, authors and affiliations as well as the e-mail address of the contact author. Papers must be formatted in accordance to the double-column CPS format. For formatting templates and information please visit http://www.computer.org/portal/web/cscps/submission. Submissions must be limited to 4 pages, including figures and references. Papers deviating significantly from the paper size and formatting rules may be rejected without review. Submission deadline: November 28th, 2014 Author Notification: December 14th, 2014 Camera-ready paper due: December 27th, 2014 Publication The proceedings of the workshop will be published by Conference Publishing Services (CPS). Conference proceedings will be submitted for indexing and inclusion in Xplore and CSDL. Registration Authors of accepted papers are expected to register for and present their papers at the workshop. Registration will be handled via the HiPEAC Conference. Workshop Organizers General Chair:  Sören Sonntag (Intel, Germany) Program Chairs:  Mitch Gusat (IBM Research Zurich, Switzerland)  Luca Ramini (University of Ferrara, Italy) Steering Committee:  José Duato (Technical University of Valencia, Spain)  Manolis Katevenis (FORTH, Greece)  Davide Bertozzi (University of Ferrara, Italy)  Cyriel Minkenberg (IBM Research Zurich, Switzerland) Publication Chair:  Bogdan Prisacari (IBM Research Zurich, Switzerland) Web Chair:  Marco Balboni (University of Ferrara, Italy)