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ECE 560 (VLSI in Signal Processing and Communications) (Spring 2015) Instructor: Naresh R. Shanbhag Consultation TAs: Pourya Assem, Sai Zhang, Graders: Mingu Kang, Yingyan Lin Credit: 4 hours Prerequisite: ECE 310 required, ECE 313, ECE482/ECE425 recommended. Students should be familiar with programming in MATLAB. HDL (VHDL/Verilog) programming experience is desirable. Textbook: Draft text by Naresh Shanbhag, and assigned technical papers. Time and Place: 12:30 ‐1.50, TuTh, 3015 ECE General Description: This course focuses on the design of communication and signal processing systems using nanoscale integrated circuits. The course provides a bridge from algorithms, through VLSI architectures, to integrated circuits. These include: 1. Introduction: motivation, communication system design: components in a communications link, source coding, channel coding, VLSI architectures, integrated circuit parameters (delay, power, area, reliability), communications‐inspired system design: algorithmic noise‐tolerance, role of estimation and detection techniques, relationship between arithmetic unit architectures, nanoscale artifacts, and architectural error statistics. 2. Signal Representation and Arithmetic units: signal representations (signed, unsigned, redundant, stochastic, Galois field), and arithmetic unit architectures (adders, multipliers). 3. Algorithm Transforms: retiming, pipelining, parallel processing, unfolding and folding. 4. Architectures for Signal Processing kernels: equalizers, adaptive filters, finite‐precision effects. 5. Architectures for Detection kernels: the detection problem, MAP and ML rules, BCJR and Viterbi algorithms and architectures. 6. Algebraic decoders: basics of error‐control coding, BCH and Reed‐Solomon decoder architectures. 7. Probabilistic decoders: turbo and LDPC decoders. 8. Communications‐inspired SOC design The course will begin with a review background material including communication system modeling, adaptive filtering, integrated circuits and arithmetic unit architectures. Next, algorithm/architectural transformations such as will be introduced and employed to trade‐off power, speed and area of arbitrary DSP data‐flow graphs. The remainder of the course will focus on understanding the algorithmic issues and the application of algorithm transforms to the computational kernels of three major blocks in a generic media communications system (see Figure below): a) source codec (video/image/data encoding and decoding), b) channel codec (error‐control decoders), and c) modulation‐demodulation. A key component of the course will be a semester long design project that will take the students from system design to architecture phase covering the source, channel and waveform processing blocks. Homeworks and the design project will involve MATLAB/C, and HDL programming. Grading: The course grade will be based upon: (1) homework assignments (25%), (2) one mid‐
term exams (25%), (3) final project and presentation (50%). Homework submission will be graded in a heavily quantized scale: 0% (way off), 50% (half‐way there), and 100% (correct or close). Instructor Office Hours: TH: 2:00pm‐3:00pm, 414 CSL Contact Prof. Shanbhag at [email protected], if consultation at a different time is needed. TA Contact: Pourya Assem ([email protected]), Sai Zhang ([email protected]) Course Web‐Page: http://courses.ece.uiuc.edu/ece560 Topical Outline 1. Introduction a. Motivation for the course – applications, role of standards, market sectors. b. Examples of communication ICs. c. Communication system design – role of various blocks in a communication link ‐ source coding, channel coding, modulation, demodulation. d. Communication SOC design – design methodology, integrated circuit parameters (delay, power, area, reliability). e. Communications‐inspired system design: introduction to algorithmic noise‐
tolerance. f. Examples of communication‐inspired ICs. 2. Signal Representation and Arithmetic units: a. Signal representations (signed, unsigned, redundant, stochastic, Galois field) + arithmetic unit architectures (adders, multipliers). b. Energy and delay in ICs – superthreshold operation c. Sub/near threshold voltage operation – MEOP, reliability issues in ICs 3. Algorithm Transforms: a. Retiming b. Pipelining c. parallel processing d. unfolding and folding e. case study 4. VLSI Architectures for Signal Processing kernels: a. Multi‐rate filtering in the TX and RX, fixed‐coefficient filters – direct, lattice, DA, strength reduced, decorrelated b. adaptive filters c. finite‐precision effects 5. VLSI Architectures for Detection kernels: a. Slicer b. MAP/BCJR architectures c. Viterbi architectures d. OC‐192 case study 6. Algebraic Channel Decoders: a. basics of error‐control coding, block (Hamming) codes, simple decoders (sequential, majority voting) b. BCH encoder, decoder algorithms and architectures c. Reed‐Solomon encoder, decoder algorithms and architectures 7. Probabilistic Channel Decoders: a. Turbo decoders b. LDPC decoders 8. Algorithmic noise‐tolerance: error statistics in nanoscale VLSI architectures, use of estimation and detection techniques for statistical error compensation.