Nanoelectromechanical Switches (NEM Relays & NEMFETs) Dimitrios Tsamados Adrian Ionescu EPFL Kerem Akarvardar H.-S. Philip Wong Stanford Elad Alon Tsu-Jae King Liu UC Berkeley Outline Part I: NEM Relays • Motivation • Device operation • Logic gate configurations • State-of-the-art • Scaling and performance • Issues • Conclusion Part II: NEMFETs 2 Motivation Motivation Two key properties unavailable in CMOS Infinite subthreshold slope Zero Leakage Ultra-low VDD without degrading Ion Zero static energy Ultra-low dynamic energy Ultra-low energy operation beyond the capability of CMOS 3 Motivation Extra Motivation • Hysteresis • Stiction SRAM and NV Memory • Low temperature process 3-D integration and hybrid NEMS/CMOS Choi et al. IEDM 2007 (UC Berkeley) Chakraborty et al. IEEE Trans. Circ. Syst. 2007 (Case Western Reserve U.) • High temperature operation • High radiation hardness Niche applications • Cheap substrates Reduced cost 4 air gap S G D insulating substrate OFF-state S G ON-state D 1 2 3 0 Drain Current limit stop cantilever beam Normalized Position Operation of the NEM Relay Conventional Device Structure & Operation VGS infinite slope zero leakage VGS Pull-in Pull-out voltage, Vpo voltage, Vpi = VDD,min 5 Operation of theand NEM Relay Logic Implementation Interconnection S D S G MOSFET VDD VDD D G NEM RELAY laterallyactuated cantilever VDD in out "p-type" laterallyactuated cantilever "n-type" CMOS CNEM Lee et al. SPIE 2005 (Simon Fraser U. – Canada) GND top view • CMOS schematics can be used in CNEM logic circuits • No conductivity difference between the n-type and p-type relays • Simple layout enabling to small area 6 Operation of the NEM Relay Energy-Reversible (ER) CNEM Logic Gates out = VDD GND VDD GND VDD GND cantilever insulator VDD in in = VDD in = GND Laterally-actuated ER CNEM Inverter out = GND Elastic potential energy, which is stored due to beam bending, is reversibly used for switching Akarvardar et al. DRC 2008 out = in Top View ER principle: Yang et al. MME 2003 Delft University – The Netherlands 7 1 energyreversible A B VDD ER ER Relays: NAND • Reduced VDD & dynamic energy Gate (unless hysteresis is prevented) • Experimentally demonstrated in RF switches (VDD = 5 V instead of Vpi = 38 V) GND 0 0 Vpo Vpi VGS (energy-reversible) (conventional) floating electrode VDD,min Conventional VDD Normalized Position Operation of the NEM Logic Relay Gates Energy-Reversible CNEM Pakula et al. (Delft U.) IEEE Sensors 2005 • Any logic function can be realized out = AB 8 State-of-the-Art The smallest 2-terminal switch ever reported: Jang et al. APL 92, 2008 (KAIST & Samsung – Korea) Vpo = 8 V Vpi = 13 V 300 nm • 15 nm gap • 35 nm beam thickness • TiN beam, sacrificial poly-Si, wet etch + critical point dry • Several hundred cycles endurance (insulator failure) zero leakage infinite slope 9 State-of-the-Art Self-assembled "CNT wafers" on pre-patterned substrates Hayamizu et al. Nature Nanotech 3 2008 (AIST – Japan) >1250 relays Parallel, scalable, and reproducible relay fabrication with > 95% structural yield ~5000 SWNTs 10 Constant-Field Scaling Scaled parameters Resulting variation Parameter Scaling Factor Gap, thickness, length, width 1/K Supply voltage 1/K Spring constant 1/K Resonance frequency K Footprint area 1/K2 Pull-in voltage 1/K Pull-in delay 1/K Pull-in energy 1/K3 Electrostatic force 1/K2 Elastic force 1/K2 van der Waals forces K • Scaling => smaller and faster relay that dissipates less energy • vdW Forces tend to become dominant at nanoscale 11 0 0 1 nm Performance = 250 nm nm L =L200 – 300 = Wsilicon h = 10 nm g0 = 10nm 4 nm D S G • 1 ns switching delay • 1.5 V supply voltage • 80 aJ switching energy • 0.03 μm2 lateral inverter area => competitive with CMOS • Zero leakage Akarvardar et al. IEDM 2007 scaling Fvdw ↑ delay ↓ ~ 1 ns stiffer beams to compensate for Fvdw increased VDD ~ 1 V Negligible Fvdw => 1 ns @ VDD 150 mV 12 NEM relays vs. Low-Power CMOS Lg = 45 nm LSTP CMOS (ITRS): High VT (0.53 V) => Very low leakage (30 pA/μm) Zero leakage advantage of the NEM relay would only be apparent in logic circuits with relatively high device count and low activity CV/I = 1 ns @ VDD = 425 mV NEM relays should achieve nanosecond-range intrinsic delay @ VDD << 425 mV => Decrease the vdw forces substantially • How? => And/or operate close to the stiction limit Akarvardar et al. submitted to • Increased sensitivity to device param. IEDM 2008 13 Issues 1. Contact reliability • hot switching • high current density • high impact velocity 2. Sticking: limits the voltage scaling 3. Packaging: hermetic sealing is required 4. Tunneling: determines the minimum gap 5. Long settling time & tip bouncing: tend to increase the switching delay 6. Brownian motion: leads to switching errors 14 Conclusion NEM logic can become an alternative ultra-low power logic technology if: • Contacts can be reliably implemented at nanoscale • Nanosecond range delays can be achieved at a few 100 mV Detailed roadmapping and intensive engineering development are recommended 15 Nano-Electro-Mechanical FETs Hybrid M/NEMS Pure M/NEM devices: Hybrid M/NEM devices: - micro/nano movable parts - passive device operation - micro/nano movable parts - solid state semiconductor device involved in operation Ex: suspended-gate FETs Ex: suspended nano-beams Drain Gate Source 17 M/NEM-FET: device architectures In-plane Move body Move gate Out-of-plane Major advantages: new functionality and low power 18 M/NEM-FET abrupt switch movable gate tgap = 220nm Drain A A’ SuspendedGate Experiment: Out-of-plane movable gate 10-6 (A) D 10-8 Pull-in 10-9 A 10-10 Gate up: • high Vt • in-series Cgap -11 10-12 20μm 3 k t gapo VPullin Pull-out 10 Source Gate down • low Vt • Cox 10-7 Drain current, I • Resonant-Gate FET (Nathanson, 1966) • Suspended-Gate MOSFET (EPFL: A.M. Ionescu, ISQED 2001, IEDM 2005, 2006) • Nano-electro-mechanical FET (UC Berkeley, T.J. King, IEDM 2005) • Modeling of SG-FET (Stanford & EPFL: Akarvardar: IEEE TED 2008, Tsamados: SSE 2008) 0 2 4 6 8 10 12 14 Gate voltage, VG(V) Applications: power management, low power logic, memory 19 NEMS simulation & modeling Electrostatic NEMS: mechanical & electrostatic analysis Source: G. Li et al, Urbana-Champaign. 20 NEM-FET: scaling & simulation • Multi-physics simulation for hybrid NEM device design • Coupled FEA: 2D ANSYS-DESSIS for suspended-gate FET Simulation: 90nm NEM-FET Suspended Gate S D 21 NEM-FET power management switch NEM-FET vs. MOSFET power management switch: • dynamic VT • Ioff, Isubthreshold : 102 -104 • sleep area ~ MOSFET Replaced by NEM-FET 22 Hysteresis: 1T MEM-FET memory -6 10 1.E-06 Drain Source ID (A) Gate 1 -7 10 1.E-07 Mechanical pull-in -8 10 1.E-08 Mechanical pull-out -9 10 1.E-09 0 -10 10 1.E-10 0 5 10 15 20 VG (V) • Electro-mechanical hysteresis: [ Vpull-in – Vpull-out ] • SG-MOSFET capacitor-less memory feasible • Hysteresis control! Scaling? Reliability? 23 Size & Voltage operation scaling (1) • nanogap scaling (Samsung) tbeam= 20nm tgap = 20nm NEM clamp switch with TiN beam memory cell array structure for high density non-volatile memory application M.-S. Kim et al., ISDRS 2007 24 Size & Voltage operation scaling (2) VD=1.2V SG-FET compliant to ITRS 90nm node: tox=2nm, L=65nm, channel doping Nch=3×1018cm−3, μ0=278cm2/Vs , airgap g0=5nm, W=400nm, h=10nm, Young modulus, E=170GPa. 25 NEM-FET inverter • significant power savings (1-2 decades reduction) of inverter peak current • no leakage power compared with nanometer scaled CMOS inverter. 26 Movable/vibrating gate transistor Laterally (in-plane) vibrating gate • lateral MOS transistor, detection in drain current • +4.3dB experimental gain demonstrated compared to capacitive detection using same structure LETI-CEA • e-beam defines gaps (~47nm gap resol.). • L=10mm, W=165nm, d=120nm C. Durand et al., IEEE EDL 2008. 27 Double Gate switchable/vibrating body FET Laterally (in-plane) movable body: first demonstration of +30dB signal improvement fres=2.4MHz, Q=6’000, Rm=200Ohm EPFL D. Grogg, A.M. Ionescu, DRC 2008. 28 Double Gate switchable/vibrating body FET Experiment D. Grogg, A.M. Ionescu, ESSDERC 2008, Confidential 29 Conclusion • NEM-FET: true hybrid mechanical-solid-state switch with near-zero point subthreshold swing • attractive for low-Ioff power management switches, capacitor-less memory (D-RAM, S-RAM and NVM with appropriate storage layers) and new analog/RF functionality (in the resonant-gate configuration). • fabrication: compatibility of surface micromachining with CMOS processing. • Voltage scaling below 1-2V: nanogap technology • Size: ~as scalable as MOSFET (anchors needed) • NEMFET does not use mechanical contacts in the path of current flow: long-term reliability comparable to that of capacitive RF MEMS switches (>109 cycles), being limited by oxide charging. 30 MEMS/NEMS application roadmap More transistors than MEMS devices Number of Transistors, NT increasing power consumption 109 108 Ultra-low-power NEM-based Embedded NVM NEM-FET Power Gating and Embedded D/SRAM 107 106 CPU’s OMM 32x32 105 104 Optical Switches & Aligners 102 101 More MEMS devices than transistors Digital Micromirror Device (DMD) Adaptive Optics ADXL RF MEMS 103 Integrated Actuator Systems NT/NM=1 Early MEMS (sensing applications) Ultra-low-power NEM Relay Logic 100 100 101 102 103 104 105 106 107 108 109 Number of Mechanical Components, NM M/NEMS Integration Levels Enabled Applications 31 MEMS/NEMS application roadmap • NEMS Beyond CMOS = low power nano-switch More than Moore = new functionality • Key role of NEMS for power savings and new functionality: future hybrid NEMS-CMOS • Future role of true hybrid NEM-FET devices: abrupt switch, memory, resonator, sensing • Challenges for hybrid NEM-FET: additional process control of nanoscale air-gap, thickness and uniformity of suspended structures, control and uniformity of mechanical properties fabrication: top-down & bottom-up (Si, CNTs) wafer-level packaging and reliability thermal drift 32 Acknowledgments EPFL: FP7 IST projects MIMOSA, MINAMI and NANO-RF Stanford: DARPA, FCRP C2S2, NSF Roger T. Howe, David Elata, J Provine, Roozbeh Parsa, Kyeongran Yoo, Soogine Chong UC Berkeley: DARPA, FCRP C2S2 Hei Kam 33
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