Data Converters
EECT 7327
Interpolating and Folding ADC
Interpolation
–1–
Professor Y. Chiu
Fall 2014
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Interpolation
…
Vi
VR1
Vo1
Vo2
VR3
Vo3
V R1
…
VR2
Vo1
VR2
Vo2
Vo3
VR3
Uniformly spaced zero-crossings in flash ADCs
Ref: R. van de Grift, I. W. J. M. Rutten, and M. van der Veen, "An 8-bit video ADC
incorporating folding and interpolation techniques," IEEE Journal of Solid-State
Circuits, vol. 22, pp. 944-953, issue 6, 1987.
–2–
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Resistive Interpolation
…
Vi
VR1
Vo1
Vo1
Vo2
Vo3
Vo2
VR3
Vo3
…
V R1
VR2
VR3
•
Intermediate zero-crossings are recovered by interpolation.
•
DNL is improved by voltage interpolation.
•
Requires overlapped linear regions b/t adjacent preamps.
–3–
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Interpolation Nonlinearity (I)
A
VA
VB/4+VA*3/4
A
VA/2+VB/2
B
VB*3/4+VA/4
B
VB
•
Nonlinear TF of preamps cause errors in the interpolated zero-crossings.
•
Interpolation nonlinearity directly translates into DNL and INL.
•
Impedance mismatch due to interpolation also causes dynamic errors.
–4–
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Interpolation Nonlinearity (II)
R
VA
A
• Interpolation factor of 4
R/4
• Latch input bandwidth
equalized
VB/4+VA*3/4
VA/2+VB/2
• Critical if input SHA is
not used
R/4
VB*3/4+VA/4
• Nonlinear interpolation
errors remain
R
B
VB
Ref: R. J. van de Plassche and P. Baltus, "An 8-bit 100-MHz full-Nyquist analog-todigital converter," IEEE Journal of Solid-State Circuits, vol. 23, pp. 1334-1344,
issue 6, 1988.
–5–
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Interpolation Nonlinearity (III)
A
VA
VB/4+VA*3/4
VA/2+VB/2
VB*3/4+VA/4
B
• Resistive mesh network
improves impedance
matching at latch input.
• 2X interpolation avoids
the interpolation error.
VB
Ref: P. Vorenkamp and R. Roovers, "A 12-b, 60-MSample/s cascaded folding and
interpolating ADC," IEEE Journal of Solid-State Circuits, vol. 32, pp. 1876-1886,
issue 12, 1997.
–6–
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Capacitive Interpolation
K. Kusumoto,
JSSC, Dec. 1993
–7–
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Current Interpolation
Less accurate then voltage interpolation due to mismatch of current mirrors
Ref: M. Steyaert, R. Roovers, and J. Craninckx, "100 MHz 8 bit CMOS interpolating
A/D converter," in Proceedings of IEEE Custom Integrated Circuits Conference,
1993, pp. 28.1.1-28.1.4.
–8–
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Features of Interpolation
• Reduces the total number of preamps by the interpolation factor.
• Total number of latches stay the same.
• Reduces the total input capacitance (larger input BW).
• More area- and power-efficient than straight flash ADC.
• Voltage interpolation improves DNL.
• Loading of interpolation network decreases the preamp gain/BW.
• Subject to preamp nonlinearities.
–9–
Data Converters
EECT 7327
Interpolating and Folding ADC
Folding
– 10 –
Professor Y. Chiu
Fall 2014
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Inefficiency of Flash ADC
VFS
Vi
Strobe
2N-1
Encoder
…
…
…
…
fs
Do
Do
0
2N-1
comparators
Vi
VFS
Only comparators in the vicinity of Vin are active at a time → low efficiency.
– 11 –
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Segmented Quantization
VFS
N
2 -1
Analog pre-processing
…
divides Vin into 2M
uniformly-spaced
Do
0
segments.
1
2
3
4
5
6
7
8
Vi
Segment indicator (M bits)
– 12 –
Fine quantization
(N-M) bits
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Signal Folding
VFS
N
2 -1
…
• Analog pre-processing
→ folding amplifier
• Folding factor (F) is
equal to the number of
folded segments.
Do
0
1
2
3
4
5
6
7
Fine quantization
N-log2(F) bits
8
Vi
Segment indicator (log2(F) bits)
– 13 –
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Folding ADC Architecture
VR
Vi
F=8
Fine ADC
5 bits
Coarse
ADC
LSB’s
Digital Logic
Reference Ladder
MSB’s
Dout
8 bits
3 bits
•
The fine ADC performs amplitude quantization on the folded signal.
•
The coarse ADC differentiates which segment Vin resides in.
– 14 –
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Folding Amplifier
RL
RL
V o+
Vo-
VR1
IS
M5 M6
M3 M4
M1 M2
VR2
IS
F=3
IS
VR3
Vi
Vo
ISRL
Vi
0
-ISRL
VR/6
5VR/6
VR/2
– 15 –
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Folding Amplifier
RL
RL
V o+
Vo-
VR1
IS
M5 M6
M3 M4
M1 M2
VR2
IS
F=3
IS
VR3
Zero-crossings
are still precise!
Vi
Vo
ISRL
Vi
0
-ISRL
VR/6
5VR/6
VR/2
– 16 –
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Zero-Crossing Detection
Vo
0
Vi
F = 3, P = 4
•
Only detect zero-crossings instead of fine amplitude quantization
→ insensitive to folder nonlinearities.
•
P parallel folding amplifiers are required.
– 17 –
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Offset Parallel Folding
Reference Ladder
VR
Vi
F = 3, P = 4
Folder 1
V1
c
0
Vi
Folder 2
V2
c
0
Vi
Folder 3
V3
c
0
Vi
Folder 4
V4
c
0
Vi
•
Total # of zero-crossings = Total # of preamps = P*F
•
Parallel folding saves the # of comparators, but not the # of preamps
→ still large Cin.
– 18 –
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Signal Folding
Pros
• Folding reduces the comparator number by the folding factor F,
while the number of preamps remains the same.
Cons
• Multiple differential pairs in the folder increases the output loading.
• “Frequency multiplication” at the folder output.
– 19 –
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Frequency Multiplication
CT vs. DT
fmax
– 20 –
π  fin

1 2
sin ( )
F
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Folding + Interpolation
Vi
c
…
Vi
…
…
Cross-connect
P & N sides at
the endpoints
– 21 –
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
“Rounding” Problem
Vo
0
Vi
F=3
Vi
F=9
2√2(Vgs-Vth)
Vo
0
2√2(Vgs-Vth)
•
Large F results in signal “rounding”, causing gain and swing loss.
•
Max. folding factor is limited by Vov of folder and supply voltage.
– 22 –
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Folding vs. Interpolation
Folding
• Folding works better with non-overlapped active regions between
adjacent folders.
• Large Vov (for high speed) of folders and low supply voltage limit
the max. achievable F.
Interpolation
• Works better with closely spaced overlapped active region between
adjacent folding signals.
Observation
• Small F and large P (parallel folders) will help both folding and
interpolation, but introduces large Cin – approaching flash…
• What else can we do?
– 23 –
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Cascaded Folding
Vo
0
F=3
Vi
F=9
c
Vi
Vo
0
•
Ideal: A large folding factor F can be developed successively.
•
Small F in the 1st-stage folder → large Vov, less capacitive loading, and
less frequency multiplication effect.
– 24 –
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Cascaded Folder Architecture (II)
Vo+
V o-
F=?
…
…
…
…
Vi
…
…
•
Simple differential pair-based folding amplifiers
•
Only works with odd P, compatible with low supply voltage.
– 25 –
Data Converters
EECT 7327
Interpolating and Folding ADC
Cascaded Folder Architecture (I)
F=?
•
Gilbert four-quadrant multiplier based folding amplifier
•
Only works with even P, requires a lot of headroom
– 26 –
Professor Y. Chiu
Fall 2014
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Mechanical Model of Cascaded Folding
Bult (JSSC’97)
– 27 –
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Distributed Preamplification
Comparators
c
Interpolation and Averaging
…
c
Interpolation and 2nd-stage Folding
…
c
1st-stage Folding and Averaging
…
c
Input and Reference Ladder
Large signal gain developed gradually along the signal path
→ from “soft” to “hard” decision
– 28 –
Gain
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Useful Formulas
Assuming a two-stage cascaded folding & interpolating ADC,
F1 = 1st-stage folding factor, F2 = 2nd-stage folding factor,
P = # of offset parallel folders, I = total interpolation factor,
then,
Total # of decision level = P*F1*I
ADC Resolution = Log2(P*F1*I)
Total # of fine comp = P*I/F2
Total # of coarse comp = P*F1 or P+F1?
where, usually P = F2 holds.
– 29 –
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Circular Thermometer Code
D C B A
VFS
F=4
Vi
A
B
C
D
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
overflow
underflow
•
Very tight coarse comparator offset requirement (<1/2 LSB)
•
Aperture delay b/t coarse and fine worsens the problem.
– 30 –
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Coarse-Fine Sync (Bit Alignment)
D C B A
VFS
Vi
A
B
C
D
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
A
OF
5
4
3
Margin
2
UF
1
•
“Coarse” fold indicator with offset thresholds combined with the output of
fine comparator A precisely determines which fold Vin resides in.
•
Large tolerance on coarse comparator offset and aperture delay errors
– 31 –
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Useful Formulas
Assuming a two-stage cascaded folding & interpolating ADC,
F1 = 1st-stage folding factor, F2 = 2nd-stage folding factor,
P = # of offset parallel folders (P>F2), I = total interpolation factor, then
total # of decision level = P*F1*I,
ADC Resolution = Log2(P*F1*I),
total # of preamps in 1st folder = P*F1,
total # of preamps in 2nd folder = P,
total # of fine comparators = P*I/F2,
total # of coarse comparators = F1*F2, F1+F2, or F1+P?
– 32 –
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Cascaded Offset Bit Alignment (I)
D C B A
VFS
Vi
A
B
C
D
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
0
A
OF
5
4
3
Margin
2
UF
1
•
F1 coarse comparators at input and P coarse comparators at 1st-stage
folder outputs resolve F1*P (>F1*F2) folds.
•
One fine comparator output is utilized to perform offset bit alignment.
– 33 –
Data Converters
EECT 7327
Interpolating and Folding ADC
Professor Y. Chiu
Fall 2014
Cascaded Offset Bit Alignment (II)
Bit
Alignment
LSB’s
Digital Logic
2nd-stage Folders (F2)
P
Cmp’s
Fine Comparators
1st-stage Folders (P*F1)
Vi
F1
Cmp’s
Reference Ladder
VR
Dout
MSB’s
Two-step offset bit alignment – large offset tolerance on F1 coarse
comparators and medium tolerance on P comparators.
– 34 –
Data Converters
EECT 7327
Interpolating and Folding ADC
References
1. R. J. van De Plassche et al., JSSC, vol. 14, pp. 938, issue 6, 1979.
2. R. E. J. van De Grift et al., JSSC, vol. 19, pp. 374-378, issue 3, 1984.
3. R. E. J. van De Grift et al., JSSC, vol. 22, pp. 944-953, issue 6, 1987.
4. R. J. van de Plassche et al., JSSC, vol. 23, pp. 1334-1344, issue 6, 1988.
5. J. van Valburg et al., JSSC, vol. 27, pp. 1662-1666, issue 12, 1992.
6. B. Nauta et al., JSSC, vol. 30, pp. 1302-1308, issue 12, 1995.
7. A. G. W. Venes et al., JSSC, vol. 31, pp. 1846-1853, issue 12, 1996.
8. M. P. Flynn et al., JSSC, vol. 31, pp. 1248-1257, issue 9, 1996.
9. P. Vorenkamp et al., JSSC, vol. 32, pp. 1876-1886, issue 12, 1997.
10. K. Bult et al., JSSC, vol. 32, pp. 1887-1895, issue 12, 1997.
11. M. P. Flynn et al., JSSC, vol. 33, pp. 1932-1938, issue 12, 1998.
12. M.-J. Choe et al., VLSI, 1999, pp. 81-82.
13. R. C. Taft et al., JSSC, vol. 39, pp. 2107, issue 12, 2004.
– 35 –
Professor Y. Chiu
Fall 2014