What is shift register?
A shift register is a digital memory circuit found in
calculators, computers, and data-processing systems. Bits
(binary digits) enter the shift register at one end and
emerge from the other end. The two ends are called left
and right. Flip flops, also known as bistable gates, store
and process the data.
Applications of shift registers






Computer and Data Communications
Serial and Parallel Communications
Multi-bit number storage
Sequencing
Basic arithmetic such as scaling (a serial shift to the left
or right will change the value of a binary number a power
of 2)
Logical operations
Parallel versus Serial

Serial communications: provides a binary
number as a sequence of binary digits, one
after another, through one data line.

Parallel communications: provides a binary
number as binary digits through multiple data
lines at the same time.
Shift Registers

Shift Registers are devices that store and move data
bits in serial (to the left or the right),

..or in parallel,

..or a combination of serial and parallel.

Ideally, in shift registers, the binary digit transfers
(shifts) from the output of one flip-flop to the input
of the next individual Flip-Flop at every clock edge.

Once the binary digits are shifted in, the individual
Flip-Flops will each retain a bit, and the whole
configuration will retain a binary number.
Construction of shift regiters

Shift registers are constructed from flip-flops due to their
characteristics:



Edge-triggered devices
Output state retention
Each Flip-Flop in a shift register can retain one binary digit.

For instance, if a 5-bit binary number needs to be stored and
shifted, 5 flip-flops are required.

Each binary digit transfer operation requires a clock edge.

Asynchronous inputs are useful in resetting the whole
configuration.
Example of shift register
construction

Shift registers are comprised of D Flip-Flops that
share a common clock input.
D Q
D Q
D Q
Q
Q
Q
Possible combinations of Data Transfer
Methods

SISO: Serial In, Serial Out

SIPO: Serial In, Parallel Out

PISO: Parallel In, Serial Out

PIPO: Parallel In, Parallel Out
SISO Flip-Flop Shift Register

a Serial In Serial Out shift register has a single
input and a single output
Input
D Q
D Q
D Q
Q
Q
Q
Output
SIPO Flip-Flop Shift Register

a Serial In Parallel Out shift register has a single input
and access to all outputs
Output
Input
Output
Output
D Q
D Q
D Q
Q
Q
Q
PISO Flip-Flop Shift Register

a Parallel In Serial Out shift register requires
additional gates, and the parallel input must revert to
logic low.
Input
Input
Input
Output
D Q
Q
D Q
D Q
Q
Q
PIPO Flip-Flop Shift Register

a Parallel In Parallel Out register has the simplest
configuration. It represents a memory device.
Input
Input
Input
D Q
D Q
D Q
Q
Q
Q
Output
Output
Output
Universal Shift Registers

Universal Shift Registers can be configured to
operate in a variety of modes. For instance, they
can be configured to have either Serial or Parallel
Input/Output.
JK Shift Registers
J-K Shift registers are seldom used, as two inputs (J,K)
are required to load the first flip-flop (note all others
receive only set or reset inputs).
Input
J
Q
J
Q
J
Q
Input
K
Q
K
Q
K
Q
Output
Introduction: Counters

Counters are circuits that cycle through a specified
number of states.

Two types of counters:
 synchronous (parallel) counters
 asynchronous (ripple) counters

Ripple counters allow some flip-flop outputs to be
used as a source of clock for other flip-flops.

Synchronous counters apply the same clock to all
flip-flops.
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Asynchronous (Ripple) Counters
 Asynchronous counters: the flip-flops do not change
states at exactly the same time as they do not have a
common clock pulse.
 Also known as ripple counters, as the input clock
pulse “ripples” through the counter – cumulative
delay is a drawback.
 n flip-flops  a MOD (modulus) 2n counter. (Note: A
MOD-x counter cycles through x states.)
 Output of the last flip-flop (MSB) divides the input
clock frequency by the MOD number of the counter,
hence a counter is also a frequency divider.
16
Asynchronous (Ripple) Counters

Example: 2-bit ripple binary counter.

Output of one flip-flop is connected to the clock input
of the next more-significant flip-flop.
HIGH
Q0
J
C
K
CLK
FF0
CLK
1
2
3
Q0
Q1
J
C
K
FF1
4
Q0
Timing diagram
Q0 0
1
0
1
0
Q1 0
0
1
1
0
00  01  10  11  00 ...
17
Asynchronous (Ripple) Counters

Example: 3-bit ripple binary counter.
HIGH
Q0
J
CLK
C
K
C
K
Q0
FF0
CLK
1
2
3
Q1
J
C
K
Q1
FF2
FF1
4
5
Q2
J
6
7
8
Q0
0
1
0
1
0
1
0
1
0
Q1
0
0
1
1
0
0
1
1
0
Q2
0
0
0
0
1
1
1
1
0
Recycles back to 0
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Asynchronous (Ripple) Counters
 Propagation delays in an asynchronous (rippleclocked) binary counter.
 If the accumulated delay is greater than the clock
pulse, some counter states may be misrepresented!
CLK
1
2
3
4
Q0
Q1
Q2
tPLH
(CLK to Q0)
tPHL (CLK to Q0)
tPLH (Q0 to Q1)
tPHL (CLK to Q0)
tPHL (Q0 to Q1)
tPLH (Q1 to Q2)
19
Asynchronous (Ripple) Counters

Example: 4-bit ripple binary counter (negative-edge
triggered).
HIGH
Q0
J
CLK
Q1
J
C
K
J
C
K
FF0
C
K
FF1
FF2
Q2
J
C
K
FF3
CLK
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15 16
Q0
Q1
Q2
Q3
20
Q3
Asyn. Counters with MOD no. < 2
n

States may be skipped resulting in a truncated
sequence.

Technique: force counter to recycle before going
through all of the states in the binary sequence.

Example: Given the following circuit, determine the
counting sequence (and hence the modulus no.)
C
All J, K
inputs
are 1
(HIGH).
Q
J
B
CLK
K
Q
CLR
Q
J
CLK
K
Q
CLR
A
Q
J
CLK
K
Q
CLR
B
C
21
Asyn. Counters with MOD no. < 2

n
Example (cont’d):
C
All J, K
inputs
are 1
(HIGH).
Clock
A
B
C
NAND 1
Output 0
Q
B
J
Q
CLK
K
Q
CLR
J
CLK
K
Q
CLR
A
Q
J
CLK
K
Q
CLR
B
C
1
2
3
4
5
6
7
8
9
10 11 12
MOD-6 counter
produced by
clearing (a MOD-8
binary counter)
when count of six
(110) occurs.
22
Asyn. Counters with MOD no. < 2
n
 Example (cont’d): Counting sequence of circuit (in
CBA order).
1
Temporary
state
2
3
4
5
6
7
Clock
A 0
1
0 1
0
1
0 1
B 0
0
1 1
0
0
0 0
C 0
NAND 1
Output 0
0
0 0
1
1
0 0
111
8
9
10 11 12
000
001
110
010
101
Counter is a MOD-6
counter.
011
100
Asynchronous
23
Asyn. Counters with MOD no. < 2
n

Exercise: How to construct an asynchronous MOD-5
counter? MOD-7 counter? MOD-12 counter?

Question: The following is a MOD-? counter?
F
Q
J
Q
K
CLR
E
Q
J
Q
K
CLR
C
D
E
F
D
Q
J
Q
K
CLR
C
Q
J
Q
K
CLR
B
Q
J
Q
K
CLR
A
Q
J
Q
K
CLR
All J = K = 1.
24
Asyn. Counters with MOD no. < 2
n
 Decade counters (or BCD counters) are counters
with 10 states (modulus-10) in their sequence.
They are commonly used in daily life (e.g.: utility
meters, odometers, etc.).
 Design an asynchronous decade counter.
(A.C)'
HIGH
J
CLK
Q
D
J
Q
C
J
Q
B
J
Q
C
C
C
C
K
CLR
K
CLR
K
CLR
K
CLR
A
25
Asyn. Counters with MOD no. < 2

n
Asynchronous decade/BCD counter (cont’d).
HIGH
J
CLK
Q
D
J
C
K
C
J
C
K
CLR
Clock
Q
2
J
C
K
CLR
1
B
Q
4
5
A
(A.C)'
C
K
CLR
3
Q
CLR
6
7
8
9
10
D 0
1
0
1
0
1
0
1
0
1
0
C 0
0
1
1
0
0
1
1
0
0
0
B 0
0
0
0
1
1
1
1
0
0
0
A 0
0
0
0
0
0
0
0
1
1
0
NAND
output
26
11
Asynchronous Down Counters
 So far we are dealing with up counters. Down
counters, on the other hand, count downward from
a maximum value to zero, and repeat.
 Example: A 3-bit binary (MOD-23) down counter.
1
J
CLK
Q
Q0
J
Q
Q1
C
K Q'
C
Q'
K
J
Q
Q2
C
K Q'
3-bit binary
up counter
1
J
CLK
Q
C
Q'
K
Q0
J
Q
C
K Q'
Q1
J
Q
C
K Q'
Q2
3-bit binary
down counter
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