2015 - Poet Technologies
POET Technologies Enabling the Future of Semiconductors Corporate Presentation February 2015 Safe Harbor The following presentation, other than statements of historical fact, may include certain “forward-looking statements” within the meaning of the United States Private Litigation Reform Act of 1995 and applicable Canadian securities laws. These forward looking statements are made under the “Safe Harbor” provisions of the aforesaid act and laws. All statements regarding future plans and objectives are forward-looking statements. Words such as “expect”, “anticipate”, “estimate”, “future plans”, “may”, “will”, ”should”, “intend”, “believe”, “opportunities”, and other similar expressions are forward-looking statements. Forward-looking statements are subject to risks, uncertainties, assumptions and are not guarantees of future results, but rather reflect current views with respect to future events. Important factors that could cause actual results to differ materially from those expressed or implied in the forward looking statements include risks and factors disclosed under the heading “Risk Factors” in the public documents filed from time to time with the System for Electronic Document Analysis and Retrieval (“SEDAR”). Readers should not place undue reliance on any forward-looking statements. We disclaim any obligation to update or revise any forward looking statements, except as required by law to reflect any change in expectations, events, conditions or circumstances on which any of the forward looking statements are based, or that may affect the likelihood that actual results will differ from those set forth in the forward-looking statements. The Milestone schedule contained in this presentation was prepared in good faith; however, the Company does not warrant that it will achieve any results projected in this presentation. This presentation contains "forward-looking information" (within the meaning of applicable Canadian securities laws) and "forward -looking statements" (within the meaning of the U.S. Private Securities Litigation Reform Act of 1995). Such statements include all aspects of the milestones scheduled to be performed after the date of this presentation. Such forward-looking information or statements are based on a number of risks, uncertainties and assumptions which may cause actual results or other expectations to differ materially from those anticipated and which may prove to be incorrect. Assumptions have been made regarding, among other things, plans for and completion of projects by the Company’s third party relationships, availability of capital, and the necessity to incur capital and other expenditures. Actual results could differ materially due to a number of factors, including, without limitation, operational risks in the completion of the Company’s anticipated projects, delays or changes in plans with respect to the development of the Company’s anticipated projects by the Company’s third party relationships, risks affecting the Company’s ability to execute projects, the ability to attract and retain key personnel, and the inability to raise additional capital. Although the Company believes that the expectations reflected in the forward-looking information or statements are reasonable, you should not place undue reliance on forward-looking statements because the Company can provide no assurance that such expectations will prove to be correct. Forward- looking information and statements contained in this presentation are as of the date of this presentation and the Company assumes no obligation to update or revise this forward-looking information and statements except as required by law. © 2015 POET Technologies Inc. – Confidential Corporate Presentation February 2015 2 POET - Planar Opto-Electronic Technology Revolutionary III-V (gallium arsenide–GaAs) semiconductor process technology used to build electrical, optical and electro-optical integrated circuits (ICs) § Up to 10x application performance gains over silicon § Up to 90% application power savings over silicon § Enables complementary logic in GaAs – never before realized in the industry § Enables innovation with fully integrated analog, mixed signal, digital and optical components on a single die § Easy industry adoption § Actively in discussion with the industry © 2015 POET Technologies Inc. – Confidential Corporate Presentation February 2015 3 Technology IP and Corporate Overview § Dr. Geoff Taylor has dedicated many years towards development of gallium arsenide semiconductor technology § Granted 34 patents, 7 additional patents pending and significant process expertise § Publicly listed: § TSX Venture Exchange (Canada) – “PTK” § OTC QX (US) – “POETF” § Fully SEC Compliant (20-F) § Company locations: § Lab facilities - Storrs, Connecticut § Head office - Toronto, Canada § Industry relations office - San Jose, California © 2015 POET Technologies Inc. – Confidential Corporate Presentation February 2015 4 Application Examples Processors and SoCs = = A4 in POET = § A4 45-nm chip fabricated with POET process could match the performance of A8 fabricated in 20-nm A8 in 20-nm Analog and Digital Integration § One chip solution for RF-to-bits and bits-to-RF § One chip IoT solution with analog and RF front-end plus microcontroller and energy harvester Optical § Enabling processor designs at > 10GHz and 50+% Applications power saving - Data Centers § Memory structures for NVRAM, SRAM and DRAM § 100G Ethernet switch with integrated Optics Servers Optical Components 40G CFP Optical Transceiver § Lowering BOM part count in optical transceivers and lowering manufacturing costs § VCSELs, 2D VCSEL arrays with integrated drivers § High speed tunable lasers with integrated drivers © 2015 POET Technologies Inc. – Confidential Corporate Presentation February 2015 5 The Industry Problem Silicon node migration is hitting physical barriers: § Silicon clock frequency is flattening out § Power is flattening out with silicon § Performance is flattening with silicon § Chip tapeout “Non Recurring Engineering” (NRE) costs are escalating geometrically with node § Investment costs to keep up with performance demands are increasingly high § Only a few fab vendors can keep up Source: Herb Sutter, “The Free Lunch Is Over: A Fundamental Turn Toward Concurrency in Software” , Dr. Dobb’s Journal, 30(3), March 2005 (graph updated in 2009) © 2015 POET Technologies Inc. – Confidential Corporate Presentation February 2015 6 POET’s Solution GaAs transistors perform over 5x better than Si based transistors at the same node § Projected to be 3-4 node jump in technology § GaAs material make excellent photonic devices and better analog circuits Integrate novel and disruptive capabilities to semiconductors § First GaAs process technology to support integrated HFETs and HBTs (complementary logic) - New GaAs p and n HFET devices - New GaAs p and n HBT devices § Supports concurrent fabrication of fully integrated electrical and optical circuit components - New GaAs Optical Thyristor device POET has been designed to function in existing silicon computing environment § Migrate into devices, starting with CMOS, opto-electronic interfaces, memory and sensors © 2015 POET Technologies Inc. – Confidential Corporate Presentation February 2015 7 End Use Markets Integrated Circuit (IC) Market - 2015 Forecast Semiconductor Design Total Available Market over $300 billions Military $< 3 © 2015 POET Technologies Inc. – Confidential Corporate Presentation February 2015 8 Easy Industry Adoption Fabless Design TCAD Foundry Outsourced Assembly & Testing OEMs Design § Enabling industry standard Synopsys design tool flow Manufacturing and Testing § Supports existing manufacturing and testing infrastructure § Supports existing silicon CMOS fabrication procedures lowering Capex Performance and Integration § 50 to 90% solution power savings lowers Opex § Integration lowers manufacturing costs © 2015 POET Technologies Inc. – Confidential Corporate Presentation February 2015 9 Monetization of Technology Non Recurring Engineering Fees (NRE) § Direct Foundry § Foundry Design Kits § Exclusive Rights by Markets Royalties on POET enabled device shipments Revenue and industry partnerships expected in 2015 © 2015 POET Technologies Inc. – Confidential Corporate Presentation February 2015 10 Achieved Technical Milestones Milestone! Date! Technical Achievement! Definitions! Q2-11! Integrated Pulsed Laser" General purpose laser for on-chip use." Q2-11! p and n channel Complementary Heterostructure Field Effect Transistor Validation1" High performance, power efficient transistors. World’s first complementary GaAs HFETs." Q4-12! Continuous Wave Vertical Cavity Surface Emitting Laser Demonstration" High density laser design for surface-emitting applications (e.g. chip-to-chip in stacked-die array)." Q1-13! n-channel and p-channel Complementary Heterostructure Field Effect Transistor Radio Frequency Validation1 Demonstrating radio frequency and microwave performance of revolutionary complementary HFETs." Q1-14! 3/4 Terminal Switching Laser Demonstration" High quality pulsed laser type for critical signal propagation (e.g. clocks, optical line signaling)." Q2-13! Complementary Heterostructure Field Effect Transistorbased Inverter/Oscillator Demonstration" Complementary HFET-based ring oscillator (standard circuit configuration used to demonstrate process performance)." Q1-14! Optical Thyristor-based Infrared Detector Array Fabrication and Validation1" An array of optical thyristors configured as infrared detectors." Q3-14! Demonstration of 100 nm or below PET n- and pchannel device" Demonstration of p and n type HFETs and BJTs at sub-100 nm feature size." Performance optimization phase on-going." Q1-14! POET TDK (Technical Design Kit) Documentation" Full POET platform TDK documentation release." Note 1: Milestones noted above were accomplished with a 3rd party fab partner, an international defense services company that is a global leader in military electronic systems design, development, manufacturing and integration. The 3rd party partner has world-class GaAs research facilities and has numerous PhD researchers. POET’s partnership has successfully reproduced the POET technology as published, by producing and testing the critical electrical elements of POET Platform sub-process steps for transistors. © 2015 POET Technologies Inc. – Confidential Corporate Presentation February 2015 11 Technical Roadmap Milestone Timeframe* Q1-‐15 Technical Milestone PET Founda+on PDK (Process Design Kit) targe+ng 40nm (V 1.0) COMPLETED 3rd Party Foundry 40/100nm transfer Defini4ons Design rules and parameters library models for PET process. Devices include complementary HFET and HBT transistor and a thyristor with both op+cal and electrical opera+on. Bring up cri+cal layers manufacturing capability in external foundry. Accelerates comple+on of development and op+miza+on learning cycles on 100 and 40nm structures. Also enables more complex test structures. Q1-‐15 Electrical 100nm ring oscillator Demonstra+on vehicle for high speed performance and power at 100nm process node. Reference standard to compare to Silicon CMOS. Q1-‐15 50 GHz VCSEL 50 GHz DWDM (dense wavelength division mul+plexing) ver+cal cavity laser device Milestone Timeframe* 2015 Capability Development! Roadmap Definitions! PET PDK v2.0 Adds mixed signal and I/O capability Adds high frequency low noise devices for analog and 2.5V HEMTs for electrical I/O to the PET PDK. Update PDK with new devices and calibra+on. Op+cal On-‐Chip Signal Distribu+on Components Develop and successful demonstra+on of individual components necessary to build WDM op+cal distribu+on and conversion from E-‐O and O-‐E. SRAM Structure Develop and successful demonstra+on of 2T thyristor-‐based bit cell, read and write amps. Goal of layout density greater than equivalent CMOS bit cell at same node. Demonstra+on Digital Cell Library Create basic set of digital cells suitable for trial SoC block post layout performance evalua+on. * Note: Please see Milestone Disclaimer © 2015 POET Technologies Inc. – Confidential Corporate Presentation February 2015 12 Management Team Peter Copetti Exec. Co-Chairman & Interim CEO Ajit Manocha Exec. Co-Chairman Dr. Geoffrey Taylor Chief Scientist § Chief architect and strategist of POET transformation § Leading POET’s resurgence and monetization activities § Capital markets expertise § Most recently CEO of GlobalFoundries (second largest semiconductor foundry in the world with multi-billions $US revenues) § 35 years of semiconductor industry experience with deep knowledge of the technology and operations § Technology and IP generation pioneer and world renowned expert in GaAs and inventor of the POET platform § POET technology development for over 20 years Daniel DeSimone § 30+ years of semiconductor development and fabrication experience § Responsible for process IP product development Stephane Gagnon § 20+ years of semiconductor and telecom management experience § Responsible for overall operations and business development Chief Technology Officer Chief Operating Officer © 2015 POET Technologies Inc. – Confidential Corporate Presentation February 2015 13 POET – Ready at the Right Time POET will provide much needed performance and power correction to the semiconductor industry § POET offers a III-V process with up to 10x performance gains § POET low voltage operation enables up to a 90% application power savings POET enables new innovations § Integration of analog, digital and optical devices on the same chip will lead to new innovative products and device consolidation never before possible POET enables system cost savings § Device consolidation will lower manufacturing costs at the module and system level § POET will enable an order of magnitude lower system OPEX due to power savings © 2015 POET Technologies Inc. – Confidential Corporate Presentation February 2015 14
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