1. art and entertainment
2. visual art and design
3. design

VI LASCAS
AND
XXI IBERCHIP
WORKSHOP
Montevideo, Uruguay
24 - 27 February 2015
GOLD SPONSORS
CONFERENCE SPONSORS
ORGANIZERS
1
LASCAS & IBERCHIP PROGRAM
LASCAS & IBERCHIP PROGRAM
Day I - Tuesday, 24th February 2015
Day II - Wednesday, 25th February 2015
11:00 - 12:00
LASCAS & IBERCHIP Registration
8:30 - 9:00
LASCAS & IBERCHIP Registration
12:00 - 13:30
Tutorial I - Session I
9:00 - 10:40
Opening Ceremony
Keynote I
13:30 - 14:30
14:30 - 16:00
16:00 - 16:30
16:30 - 18:00
Carlos Galup Montoro and
Marcio Cherem Schneider
Subthreshold CMOS design
Roberto S. Murphy
Characterization of
Semiconductor Devices in
the High-Frequency Regime
Franco Maloberti
Data Converters: the road from hundred of MS/s to many GS/s
10:40 - 11:00
Coffee Break
11:00 - 12:40
Session I-A LASCAS
12:40 - 14:00
Lunch
14:00 - 15:10
Panel
15:10 - 16:30
Session II-A LASCAS
16:30 - 17:20
Coffee break
LASCAS Poster Session I – IBERCHIP Poster Session I
17:20 - 19:00
Session III-A LASCAS
Time for Lunch
Tutorial I - Session II
Carlos Galup Montoro and
Marcio Cherem Schneider
Subthreshold CMOS design
Tutorial II - Session II
Roberto S. Murphy
Characterization of
Semiconductor Devices in
the High-Frequency Regime
Coffee Break
LASCAS & IBERCHIP Registration
Tutorial III
Manuel Delgado Restituto
Implantable Neural
Recording Interfaces
18:00 - 18:30
LASCAS & IBERCHIP Registration
18:30
Welcome Cocktail
Sala Cabildo
2
Tutorial II - Session I
Analog Circuits I
Imaging Techniques
Gordana Jovanovic, Jose M. de
la Rosa, Gerardo Molina Salgado
Sala Ciudadela
Digital Filters
Session I-C IBERCHIP
CAD
Industry Presentations
Tutorial IV
Comb-based Decimation
Filters for Sigma-Delta A/D
Converters: Algorithms and
Implementation
Session I-B LASCAS
Data Converters
Sala Reconquista
Session II-B LASCAS
Communication
Systems & Signal
Processing
Session II-C IBERCHIP
Embedded Systems
& Computer
Architecture
Session III-B LASCAS
Session III-C IBERCHIP
Sala Cabildo
Sala Ciudadela
Test Techniques
Sensors
3
LASCAS & IBERCHIP PROGRAM
LASCAS & IBERCHIP PROGRAM
Day III - Thursday, 26th February 2015
Day IV - Friday, 27th February 2015
9:00 - 10:40
Session IV-A LASCAS
10:40 - 11:00
Coffee Break
11:00 - 12:40
Panel
Analog Circuits II
Digital Signal
Processing
Techniques I
Session IV-C IBERCHIP
CAD & Digital
Design
Electronic Industry in the Region: Status and Challenges
12:40 - 14:00
Lunch
14:00 - 15:00
Keynote II
15:00 - 16:20
Session IV-B LASCAS
David Atienza
Designing Multi-Parametric Wearable Monitoring
Systems for Scalable Healthcare
Session V-A LASCAS
Pattern Recognition
& Sensing
Session V-B LASCAS
Digital Signal
Processing
Techniques II
Fuzzy Logic &
Neural Networks
Coffee break
Young Professionals/MSc/PhD Students Forum - Poster Session
17:00 - 18:40
Session VI-A LASCAS
20:30
Digital &
ASIC Design
Coffee break
LASCAS Poster Session II – IBERCHIP Poster Session II
10:50 - 12:30
Session VII-A LASCAS
12:30 - 13:50
Lunch
13:50 - 15:00
Embedded Tutorial
15:00 - 16:40
Session VIII-A LASCAS
Session VI-C IBERCHIP
Signal Processing
in the Digital
Domain
16:40 - 17:00
Coffee Break
17:00 - 17:20
Closing Ceremony
Modeling &
Simulation of FET
Devices
Session VII-B LASCAS
FPGA-Based
Applications
Session VII-C IBERCHIP
Analog & RF
Maciej Ogorzalek
3D ICs - Challenges and Advantages
Analog & MixedSignal Circuits
Session VIII-B LASCAS
Biomedical &
Neuromorphic
Circuits and
Systems
Session VIII-C LASCAS
Computing
Techniques
Gala Dinner - Club Uruguay
Sala Reconquista
4
Session VI-B LASCAS
Keynote III
Sachin Sapatnekar
Reliability Issues in CMOS,
and Spin-Based Design Beyond CMOS
10:00 - 10:50
Session V-C IBERCHIP
16:20 - 17:00
RF Circuits
& Systems
9:00 - 10:00
Sala Cabildo
Sala Ciudadela
Sala Reconquista
Sala Cabildo
Sala Ciudadela
5
KEYNOTE I
ized near-threshold computing and memory blocks in order to deploy ultra-low power (ULP)
multi-core processing architectures for automated bio-signals analysis on WBSN. To illustrate the effectiveness of this approach, this talk focuses on cardiac and multi-parametric
monitoring systems and show how it is possible to achieve wearable ULP electrocardiogram
(ECG) arrhythmia detection systems and multi-parametric wellness monitoring devices that
can operate autonomously for long periods of time and support a graceful quality degradation of the system output based on the available power in the system at each moment in time.
FRANCO MALOBERTI
Friday 27th February, 9:00 - 10:00, Sala Reconquista
Data converters are essential elements for new advanced applications like gigabit Ethernet,
optical communications, radar, set-top box, ultra wide band communications, broadband
satellite receivers, and more. The resultant specifications establish an unprecedented combination of speed, resolution, and power efficiency. The use of modern nanometer CMOS
technologies and digital assisted method are key for obtaining proper results, especially
when the requirement is to operate at conversion speed in the GS/s range. For those extremely high-speed traditional power-hungry flash architectures have been recently replaced by time interleaving power effective A/D converters. The preferred single channel
schemes are the SAR or the folding flash architecture.
KEYNOTE III
KEYNOTE SPEECHES
Wednesday 25th February, 9:30 - 10:40, Sala Reconquista
“Data Converters: the road from hundred of MS/s to many GS/s”
University of Pavia, Italy
Therefore, presently, the road from hundred of MS/s to many GS/s ADC starts from highspeed SAR or equivalent power effective schemes and goes through techniques for making
effective the interleaved architecture. Namely, methods for a suitable clock generation, its
distribution and the correction of clock skew are necessary.
This presentation discusses state-of-the-art silicon implementations of high-speed single channel ADC and presents analog and digital techniques used to make the interleaved
scheme accurate and affordable.
Thursday 26th February, 9:00 - 10:40, Sala Reconquista
“Reliability Issues in CMOS, and Spin-Based Design Beyond CMOS”
SACHIN SAPATNEKAR
University of Minnesota, USA
As CMOS technologies have shrunk to the scale of about ten nanometers, reliability and aging problems have emerged as a major challenge in the design of parts used in the mobile
infrastructure, server, and automotive segments. A true reliability solution must link device
models to circuit techniques to architectural approaches. Current approaches based on projecting device-level models are often pessimistic (in some cases, by orders of magnitude)
because they ignore the inherent resilience of circuits to reliability failures. At the other end
of the spectrum, system-level models often ignore the physics of reliability. This talk will first
discuss research that allows modeling, design, and design automation at various levels to
meet in the middle to solve reliability problems at various levels of design abstraction.
Even with enhanced reliability, further scaling of CMOS circuits is likely to eventually become impractical. In the final segment of this talk, we will discuss options for a post-CMOS
era, with specific focus on spintronics, an exciting prospect for post-CMOS electronics. This
model of computing is based on the use of electron spin as a state variable, instead of charge
as in CMOS, and is based on switching nanomagnets. An overview of methods for building
memory and logic devices using spin-based devices will be provided, with projections for
future research in this area.
KEYNOTE II
“Designing Multi-Parametric Wearable Monitoring Systems
for Scalable Healthcare”
DAVID ATIENZA
PANELS
Embedded Systems Laboratory (ESL), EPFL, Switzerland
Latest progress in microelectronics have enabled the miniaturization of processing elements, radio transceivers and sensing elements of a large array of physiological phenomena. This situation has made plausible to realize low cost, low power, miniaturized, yet, smart
sensor nodes needed to develop wireless body-area sensor networks (WBSN). However, the
inherent resource-constrained nature of these systems, coupled with the harsh operating
conditions and stringent autonomy requirements, pose important design challenges to make
them provide automated analysis for complex biological signals. This talk discusses the use
of WBSN systems to build scalable healthcare ecosystems. Hence, it addresses system-level
design of next-generation smart WBSN platforms for personal health monitoring systems,
and highlights the unsustainable energy cost incurred by the relatively straightforward wireless streaming of raw sensor data. To achieve the extended autonomy required by long-term
ambulatory monitoring, this talk advocates for enabling more embedded intelligence onboard
these sensor nodes through a new system-level design approach. This approach exploits the
bio-signals features to apply the new compressive sensing paradigm in the design of special-
6
Wednesday 25th February, 14:00 - 15:10, Sala Reconquista
PANEL
“Industry Presentations”
Brief Sponsor’s Presentations.
This includes presentations by:
- Hercules Neves of UNITEC (www.unitecgroup.net)
- Jacobus Swart of IMEC (www2.imec.be)
- Victor Grimblatt of Synopsys (www.synopsys.com)
- Pedro Arzuaga of CCC (www.ccc.com.uy)
7
Thursday 26th February, 11:00 - 12:40, Sala Reconquista
Tuesday 24th February, 12:00 - 13:30 and 14:30 - 16:00, Sala Ciudadela
PANEL
TUTORIAL II
Panel organizer: VICTOR GRIMBLATT
ROBERTO S. MURPHY
“Electronic Industry in the Region: Status and Challenges”
“Characterization of Semiconductor Devices in the High-Frequency Regime”
Synopsys, Chile
Instituto Nacional de Astrofísica, Óptica y Electrónica (INAOE), México
The panel includes:
- Eudes Prado Lopes, CPqDBrasil
- Gerardo Monreal, Allegro Argentina
- Jose Antonio Scodiero, Fast Company Brasil
- Pedro Arzuaga, CCC Uruguay
- Victor Grimblatt, Synopsys Chile
- Juan Lestani, Unitec Semiconductors Brasil
After briefs presentations by the members of the panel, the discussion will be open to the public.
TUTORIALS
Tuesday 24th February, 12:00 - 13:30 and 14:30 - 16:00, Sala Cabildo
TUTORIAL I
“Subthreshold CMOS design”
CARLOS GALUP MONTORO AND MARCIO CHEREM SCHNEIDER
The use of semiconductor devices and passive components such as antennas, inductors and
transmission lines is everyday more important in the design and fabrication of integrated circuits for high-frequency applications. Circuit and system applications employing wireless communications are used nowadays for a wide variety of applications, and the trend clearly shows
that these types of circuits will be needed for a host of novel applications in the years to come.
This tutorial spans three fundamental aspects of semiconductor and passive devices for
high-frequency applications; their underlying physics, modeling and characterization. During the first part, the particular structure is analyzed with the aim of identifying the physical
mechanisms on which its performance is based, such as material properties, geometric factors and construction. A second part illustrates the different methodologies available to relate the physical phenomena to an electric equivalent circuit, addressing the need for reliable
and trustworthy models for the simulation stages of these devices. The final part of the tutorial focuses on device measurement in the high-frequency regime, covering topics such as
calibration techniques, de-embedding procedures, data transformation and interpretation.
The tutorial concludes with general guidelines for the design and analysis of semiconductor and passive elements, including parasitic effects which affect the performance of these
devices when the operation frequency is in the GHz range.
Tuesday 24th February, 16:30 - 18:00, Sala Cabildo
Universidade Federal de Santa Catarina, Brazil
TUTORIAL III
The main purpose of this tutorial is the design of integrated circuits for ultra-low-voltage
and ultra-low-power operation. In order to focus on circuit design rather than on the complete MOSFET model, we will emphasize the subthreshold operation of the MOS transistor.
Ultra-low-voltage circuits have gained considerable attention in recent years because of the
emergence of small batteries and self-powered applications. The main solution to reduce
the energy consumption of electronic circuits is to lower the supply voltage. Theoretically, the
minimum supply voltage for a CMOS inverter is 2 (ln2) (kT/q) = 36 mV at room temperature,
as shown by Swanson and Meindl in 1972.
In this tutorial we analyze CMOS logic gates and the Schmitt Trigger circuit in weak inversion
operation, and discuss circuit techniques to approach the theoretical low voltage limit. For
analog circuits the minimum supply voltage is usually considered higher than the minimum
necessary for the operation of digital circuits. Contrary to this common belief, we will show
that analog circuits such as rectifiers and oscillators can operate with supply voltages below
(kT/q). In the lecture we will discuss key concepts for ultra-low-voltage operation, such as
MOS transistors with zero or near zero threshold voltage, modeling issues, and ultra-lowvoltage biasing and building blocks. Finally, a section on ultra-low-voltage circuits for energy
harvesting is presented.
8
“Implantable Neural Recording Interfaces”
MANUEL DELGADO RESTITUTO
Instituto de Microelectrónica de Sevilla (Univ. Sevilla - CSIC), Spain
Besides fostering advances in neuroscience, wireless neural prostheses for the measurement of intracranial neural activity are expected to play a significant role in the development
of novel treatments for some neurological diseases and in the implementation of untethered
brain-machine interfaces. As long as these prostheses are implanted, they have to achieve
and maintain stable long-term recordings so that the need for re-surgery is essentially eliminated. This poses important challenges on the hardware implementation of the prostheses
as they have to exhibit ultra-low power consumption, not only to prevent from harmful effects in the brain but also to minimize energy requirements; low form factor; versatility, to
prove useful in different scenarios as determined by neurologists; and adaptability to deal
not only with the intrinsic statistical deviations of the fabrication process but also with the
non-stationary nature of the electrode-tissue interface.
This tutorial surveys some of the most recent advances in the implementation of wireless
neural prostheses covering different disciplines; since the fabrication of microelectrodes, to
the design of communication protocols, passing though the optimization of ultra-low power
analog front-ends and power efficient data converters. As a demonstration vehicle, an integrated 64-channel neural recording sensor suitable for acquiring Local Field Potentials
(LFPs) and Action Potentials (APs) will be described in detail. In this prototype, an on-chip
9
dedicated processor defines the operation mode of the channels and implements a fullduplex protocol for data transmission through a wireless link. In one operation mode, the
recording system can be configured to detect and compress neural spikes so that feature
vectors instead of raw signal samples are transferred. In another mode, the system runs
a self-calibration mechanism which automatically adapts the filter bandwidth and the gain
setting of the channels. The sensor also offers different alternatives for raw data transmission in which the number of active channels and the effective sampling rate are traded-off. In
all cases, the total throughput rate of the sensor keeps below 4Mbps as imposed by the wireless link. The sensor has been fabricated in a 0.13 µm standard CMOS process and consumes
330 µW from a 1.2 V voltage supply in the most power demanding mode.
Tuesday 24th February, 16:30 - 18:00, Sala Ciudadela
TUTORIAL IV
“Comb-based Decimation Filters for Sigma-Delta A/D Converters:
Algorithms and Implementation”
GORDANA JOVANOVIC DOLECEK(1), JOSE M. DE LA ROSA(2),
GERARDO MOLINA SALGADO(1)
(1)Department of Electronics, Institute INAOE, Mexico
(2)Instituto de Microelectrónica de Sevilla (Univ. Sevilla - CSIC), Spain
Friday 27th February, 13:50 - 15:00, Sala Reconquista
EMBEDDED TUTORIAL
“3D ICs - Challenges and Advantages”
MACIEJ OGORZALEK
Department of Information Technologies, Jagiellonian University, Poland
The most significant challenge for continued integration of complex systems is energy efficiency. 3D heterogeneous stacking of diverse circuit blocks is one of the most promising solutions.The tutorial will focus on three-dimensional integrated circuits (3D lCs) consisting of
multiple layers of systems connected vertically. We will discuss advantages and challenges
of current 3D TSV-based technologies and other types of connections available in news technologies such as carbon nanotubes. One can exploit various options and choices for silicon
and heterogeneous systems. Challenging questions include system types, functionalities,
the variety of materials, TSV-based vertical integration technologies, 3D layout and routing,
interconnect modeling, the system 3D architecture, energy efficiency, technological feasibility, and the multi-objective optimization. Comparisons between various solutions will be
presented and discussed. An overview of current new concepts for construction of heterogeneous layers on chip containing such devices as energy scavengers and energy storing
devices including hyper-capacitors and micro-batteries will be presented.
In oversampled Sigma-Delta analog-digital converters (SD ADC) analog signal is sampled
with the frequency much larger than the Nyquist frequency, which along with the quantization noise shaping, results in an high resolution compared with the traditional ADCs. This
process is done in the modulator, which is the most critical block of the overall ADC. The
sampling rate of the oversampled signal at the output of modulator, must be decreased to
the Nyquist rate (decimated) and the out-of-band components of the quantization noise must
be removed. However, the decreasing of the sampling rate may introduce the aliasing which
must be eliminated in order to prevent the distortion of the oversampled signal. Consequently, the main part of the decimator is the digital filter, called decimation or antialiasing filter,
which has to prevent the aliasing effect. The decimation is usually performed in different
stages. The most critical is the first stage because it works at high input rate. Due its simplicity, comb filter structures are frequently used at the first stage of decimation. New demands
on SD ADC pose the strong conditions for the comb decimation stage, requiring high decimation factor, low power and area consumption. Additionally, the magnitude characteristic must
have high alias rejections and a low passband droop to avoid the degradation of the signal
after decimation.
In the first part, we will explain the effect of aliasing in the time and frequency domain and
we will introduce comb filter, which is the simplest decimation filter. We will present the advantages and disadvantages of the comb filter and its two principal structures: recursive and
nonrecursive. We will also introduce the polyphase decomposition, which is useful to move
the filtering to lower rate. We will present principal methods for the improving the magnitude
characteristic of the comb filter in the passband, the stopbands, and in both: passband and
stopbands.
In the second part, we will discuss the implementation issue and how to measure the consumed power and used area in comb-based structure. We will present power efficient and
area efficient structures, as well as the structures with best trade-off between power and
area efficiency.
10
11
Wednesday 25th February, 11:00 - 12:40
LASCAS - Session I-A / Sala Reconquista
Wednesday 25th February, 15:10 - 16:30
LASCAS - Session II-A / Sala Reconquista
Analog Circuits I / Session chair: ANGEL ABUSLEME
Imaging Techniques / Session chair: THANOS STOURAITIS
11:00
“High Slew-Rate OTA With Low Quiescent Current Based On Non-Linear Current Mirror”
Pablo Perez, Francisco Veirano, Pablo Castro Lisboa and Fernando Silveira
15:10
“Resonant Frequency Calculation of Square Diaphragms: A Comparison”
Rayyan Manwar, Livingstone Arjunan, Majid Ahmadi and Sazzadur Chowdhury
11:20
“Resistorless Switched-Capacitor Current Reference Based on the MOSFET ZTC Condition”
Pedro Toledo, Hamilton Klimach, David Cordova, Sergio Bampi and Eric Fabris
15:30
11:40
“Design of CMOS Current-mode Multiplier-Divider circuits for type-2 FLC Applications”
Rodrigo B. Santos, Paloma Maria Silva Rocha Rizol and Leonardo Mesquita
“Pathology Grading in Retina Digital Images Using Student-Adjusted Empirical Mode
Decomposition and Power Law Statistics”
Mounir Boukadoum and Salim Lahmiri
12:00
“A Low-Noise Fully Differential Recycling Folded Cascode Neural Amplifier”
Sammy Cerida, Erick Raygada, Carlos Silva and Manuel Monge
15:50
“Image Filtering in a CMOS Analog CNN”
Fabian Souza de Andrade, Ygor Oliveira Da Guarda Souza, Edson Pinto Santana
and Ana Isabela Araújo Cunha
12:20
“A Novel and Highly Accurate Bandgap Monitor Circuit for Supply Sequencing”
Ashish Khandelwal, Bharath Kannan and Joseph Khayat
16:10
“Influence of Cascode and Simple Current Mirrors in Inner Product Implementations
for CMOS Imagers”
Fernanda Oliveira, José Gabriel Gomes and Antonio Petraglia
LASCAS - Session I-B / Sala Cabildo
Digital Filters / Session chair: GORDANA JOVANOVIC DOLECEK
11:00
“Design of Filterbanks Using a Fast Optimization Approach”
Iman Moazzen and Panajotis Agathoklis
11:20
“Signal Enhancement for Gunshot DOA Estimation with Median Filters”
Angelo M. C. R. Borzino, José A. Apolinário Jr., Marcello L. R. de Campos and Luiz W. P.Biscainho
11:40
“A Multi-Standard Interpolation Filter for Motion Compensated Prediction on High
Definition Videos”
Henrique Maich, Guilherme Paim, Vladimir Afonso, Luciano Agostini, Bruno Zatt and Marcelo Porto
12:00
“Realization of 4D Ladder Structured Digital Filters”
George Antoniou and Minas T. Kousoulis
12:20
“On simple comb decimation structure based on Chebyshev sharpening”
Miriam Guadalupe Cruz-Jimenez, David Ernesto Troncoso Romero and Gordana Jovanovic Dolecek
LASCAS - Session II-B / Sala Cabildo
Communication Systems & Signal Processing / Session chair: BLANCA ISABEL GEA
15:10
“Unconventional Signal Processing Architecture for Reconfigurable On-Chip
Communication Systems”
Jose Luis Vazquez, Remberto Sandoval, Blanca Isabel Gea, Ramon Parra and Mario Siller
15:30
“Dynamic Resource Allocation in LTE Systems using an Algorithm based on Particle
Swarm Optimization and BetaMWM Network Traffic Modeling”
Flávio H. T. Vieira, Bruno H. P. Gonçalves, Flávio G. C. Rocha, Luan L. Lee and Marcus V. G. Ferreira
15:50
“Optimal location of reclosers in distribution systems considering reliability in
communication channels”
Oscar Danilo Montoya Giraldo, Ricardo A. Hincapié, Mauricio Granada and Andrés Alzate
16:10
“A Comparison between RS+TCM and LDPC for G.fast Channel Coding”
Marcos Yuichi Takeda, Fernanda Smith and AldebaroKlautau
IBERCHIP - Session I-C / Sala Ciudadela
CAD / Session chair: JOSÉ RAPALLINI
11:00
“Desenvolvimento de uma Ferramenta para a Caracterização Temporal de Portas
Lógicas CMOS”
Ingrid Machado, Paulo Francisco Butzen, Cristina Meinhardt and Eric Fabris
11:20
“Uma Abordagem Sistemática para Analisar e Otimizar os Efeitos da Eletromigração
nos Sinais Internos das Células”
Gracieli Posser, Vivek Mishra, Palkesh Jain, Ricardo Reis and Sachin Sapatnekar
11:40
“Software Tool for the Analysis of Gate Activation in the ISCAS 85 Combinational Circuits”
Alberto Palacios Pawlovsky
12:00
“Uma Arquitetura para Exploração de Paralelismo Multinível utilizando Roteadores
Processantes”
Marcos Cruz, Monica Pereira and Marcio Kreutz
12:20
“Synthesis by Optimized Direct Mapping of Extended Burst-Mode gC Finite State Machines”
Duarte Oliveira, Lester Faria and Leonardo Romano
12
IBERCHIP - Session II-C / Sala Ciudadela
Embedded Systems & Computer Architecture / Session chair: LEONARDO STEINFELD
15:10
“Uma Plataforma Multicore Compatível com O Modelo de Programação OpenCL”
Ramon Nepomuceno, Jonatas Santos, Laysson Luz and Ivan Saraiva Silva
15:30
“Inferring Custom Architectures from OpenCL”
Krzysztof Kepa, Ritesh Soni and Peter Athanas
15:50
“Desarrollo de un prototipo de sistema de cosecha de energía biomecánica aplicado
a estudios neurocientíficos”
Eduardo Queccara and José Alcántara
16:10
“Sistema embarcado para detecção de direção rodoviária agressiva”
Juan Diego Diaz Lopez, Mauro Miyashiro and Fabiano Fruett
13
Wednesday 25th February, 16:30 - 17:20
LASCAS - Poster Session I
Wednesday 25th February, 17:20 - 19:00
LASCAS - Session III-A / Sala Reconquista
Session chair: PABLO AGUIRRE
Data Converters / Session chair: FRANCO MALOBERTI
“Dynamically Reconfigurable NoC using a Deadlock-Free Flexible Routing Algorithm
with a Low Hardware Implementation Cost”
Ernesto Cristopher Villegas Castillo, Gabriele Miorandi, Davide Bertozzi and Wang Chau
17:20
“An approach to the design of low-jitter differential clock recovery circuits for high performance ADCs”
17:40
“A Third-Order 1 MHz Continuous-Time Sigma-Delta Modulator in a 130 nm CMOS Process”
Paulo César C. de Aguirre, Hamilton Klimach and Altamiro Susin
18:00
“On the Design of Incremental Data Converters with Extended Range”
Mohammadreza Baghbanmanesh and Franco Maloberti
18:20
“MOS-only M-2M DAC for Ultra-Low Voltage Applications”
Israel Sperotto, Hamilton Klimach and Sergio Bampi
18:40
“Novel Two-Stage Comb Decimator with Improved Frequency Characteristic”
Gerardo Molina Salgado, Gordana Jovanovic Dolecek and Jose M. De La Rosa
“Hardware Architecture of the EKF Prediction Stage applied to Mobile Robot Localization”
Luis Federico Contreras Samame, Sérgio Messias Cruz, Carlos Humberto Llanos Quintero
and José Maurício Santos Torres Da Motta
“Area-oriented Iterative Method for Design Space Exploration with High-Level Synthesis”
Jeferson S. Silva and Sergio Bampi
“An Analytical Timing-Driven Algorithm for Detailed Placement”
Jucemar Monteiro, Marcelo Johann, José Luis Güntzel and Guilherme Flach
“A Basic Method for the Design of an Oscillator using an Electromechanical Resonator”
William Toro, David Altamar, Jorge Martinez and Mauricio Pardo
“Hardware implementation of a single-cycle one-dimensional median filter”
Alejandro Veiga and Grunfeld Christian
“Advancing in knowledge of the Frobenius Spectrum”
Jonas Augusto Kunzler, Rodrigo Pinto Lemos, Diego Fernando Burgos, Hugo Vinicius Leão E Silva,
Yroá Roblêdo Ferreira, Paulo César Machado and Getúlio Antero de Deus Júnior
“Analysis of two fault locators to different operating states in power distribution system”
Juan David Ramírez Ramírez, Juan José Mora Flórez and Sandra Milena Pérez Londoño
“Reducing the Signal Electromigration Effects on Different Logic Gates by Cell Layout Optimization”
Gracieli Posser, Lucas de Paris, Vivek Mishra, Palkesh Jain, Ricardo Reis and Sachin S. Sapatnekar
“FPGA Implementation of the CCSDS-123.0-B-1 Lossless Hyperspectral Image Compression
Algorithm Prediction Stage”
Ettore Napoli, Giorgio Lopez and Antonio G.M. Strollo
IBERCHIP - Poster Session I
LASCAS - Session III-B / Sala Cabildo
Test Techniques / Session chair: RAOUL VELAZCO
17:20
“Partial Triplication of a Sparc-V8 Microprocessor Using Fault Injection”
Cyril Bottoni, Benjamin Coeffic, Jean-Marc Daveau, Lirida Naviner and Philippe Roche
17:40
“On the Functional Test of the Cache Coherency Logic in Multi-core Systems”
Julio Perez Acle, Riccardo Cantoro, Ernesto Sanchez and Matteo Sonza Reorda
18:00
“Testing Fully Differential Amplifiers Using Common Mode Feedback Circuit: a case study”
18:20
“Influence of supplies on fast transient burst test in microcontrollers”
Yann Bacher, Cesar Gori, Nicolas Froidevaux, Henri Braquet, Gilles Jacquemod and Philippe Dupre
18:40
“Fault Location Method Based on Two End Measurements at the Power Distribution System”
Juan David Ramírez Ramírez, Juan José Mora Flórez and Cristian David Grajales Espinal
Session chair: PABLO AGUIRRE
“LM-NoC: Uma Linguagem de Modelagempara Redes em Chip”
Jonathan Wanderley, Ana Luisa Medeiros, Márcio Kreutz, Max Miller Silveira and Monica M. Pereira
“Paralelismo no Roteamento Global de Circuitos VLSI: Estado da Arte”
Diego Tumelero, Vitor V. Bandeira, Guilherme Bontorin and Ricardo Reis
“Multiple bus low power processor design”
Augusto Morita and Wilhelmus Van Noije
“Fuente de alimentación embebida”
Maria Isabel Schiavon, Daniel Alberto Crepaldo, Eduardo Bailón and Carlos Varela
“A Comparison between Direct Digital Measurement Technique and Digital Quadrature
Demodulation for Complex Bioimpedance Measurement Implementation in FPGA”
Allan Oliveira, Raphael Pereira, Joao Dias, Bernardo Leite and Andre Mariano
“Implementação em FPGA de uma FIFO Assíncrona Robusta de Alto Throughput”
Duarte Oliveira, Kledermon Garcia and Roberto D’Amore
“Projeto de um Circuito Integrado para Auxílio ao Controle de Servomotores”
Lucas Garcia and Roberto Neli
14
Juan Núñez, Antonio J. Ginés, Eduardo J. Peralias and Adoración Rueda
Isis Bender, Guilherme Cardoso, Tiago Balen, Arthur de Oliveira, Lucas Severo and Alessandro Girardi
IBERCHIP - Session III-C / Sala Ciudadela
Sensors / Session chair: ALFONSO CHACÓN
17:20
“Sistema de control y sensado de policromador MEMS”
Walter Aroztegui, Edgardo Ricci and José Rapallini
17:40
“Una plataforma MEMS para la medición IN-SITU y en tiempo real de la tensión/
esfuerzo inducido electroquímicamente en el electrodo de una batería de LITIO-ION”
Sergio Baron
18:00
“Optical characterization of uncooled bolometers based on La0.7Sr0.3MnO3 thin films”
Vanuza Nascimento, Bruno Guillet, Shuang Liu, Ammar Arian, Carolina Adamo, Darell
Scholom, Raimundo Freire and Laurence Méchin
18:20
“Sensor de Imagen CMOS con Detección de Color Sensible a la Polarización”
José Antonio Rapallini, Jorge Rafael Osio, Mauro Escobar, Ariel Cedola, M. A. Cappelletti,
E. L. Peltzer Y Blancá, S. H. Carbonetto and J. Lipovetzky
15
Thursday 26th February, 9:00 - 10:40
LASCAS - Session IV-A / Sala Reconquista
Thursday 26th February, 15:00 - 16:20
LASCAS - Session V-A / Sala Reconquista
Analog Circuits II / Session chair: ANTONIO QUEIROZ
Pattern Recognition & Sensing / Session chair: DAVID ATIENZA
9:00
“A Computer-Aided Approach for Voltage Reference Circuit Design”
Fabián Olivera and Antonio Petraglia
15:00
“Robust smartphone-based human activity recognition using a tri-axial accelerometer”
Cesar Torres Huitzil and Marco Nuno Maganda
9:20
“A CMOS Low Noise Transconductance Amplifier for 1-6 GHz Bands”
David Cordova, Eric Fabris and Sergio Bampi
15:20
“2D Amplitude-Modulation Frequency-Modulation - based Method for Motion Estimation”
Victor Murray, Paul Rodriguez, Maria Noriega, Alvaro Dasso and Marios Pattichis
9:40
“Signal Processing for a Standard Harmonic Analyzer”
Leonardo Trigo and Daniel Slomovitz
15:40
10:00
“Configurable low noise readout front-end for gaseous detectors in 130nm CMOS technology”
Hugo Hernandez, Wilhelmus Van Noije and Marcelo Munhoz
“Pattern Recognition Applied to Identification of Chronic Granulocytic Leukemia”
María Del Rocio Ochoa Montiel, Enrique Santamaría-Díaz, Carlos Sánchez-López,
Federico Ramírez-Cruz and Francisco Javier Albores-Velasco
16:00
10:20
“Simulation of MEMS energy harvesting generators based on bennet’s doubler”
Antonio Queiroz and Luiz Oliveira
“Motion capture sensor to monitor movement patterns in animal models of disease”
Fabian Hoeflinger, Rui Zhang, Tobias Volk, Enrique Garea-Rodríguez, Adnan Yousaf,
Christina Schlumbohm, Kerstin Krieglstein and Leonhard Reindl
LASCAS - Session IV-B / Sala Cabildo
Digital Signal Processing Techniques I / Session chair: ADORACIÓN RUEDA
9:00
“A Comparative Analysis of Inclusion of PMUs in the Power System State Estimator”
Miguel Yucra, Fabiano Schmidt and Madson Cortês de Almeida
9:20
“S-GMOF: A Gradient-based Complexity Reduction Algorithm for Depth-Maps Intra Prediction on 3D-HEVC”
9:40
“Analysis of source separation algorithms in industrial acoustic environments”
Clevis Lozano, Alfonso Chacon, Fernando Merchan and Pedro Julian
10:00
“Switched Reluctance Machine Fuzzy Modeling Applied on a MRAC Scheme”
Arnaldo Matute, Julio Viola and Jose Restrepo
LASCAS - Session V-B / Sala Cabildo
Digital Signal Processing Techniques II / Session chair: LUCIANO AGOSTINI
15:00
“Hardware Design of Fast HEVC 2-D IDCT Targeting Real-Time UHD 4K Applications”
Ruhan Conceição, Ândrio Araújo, Marcelo Porto, Bruno Zatt and Luciano Agostini
15:20
“Optimal Location and Sizing of Distributed Generators Using a Hybrid Methodology
and Considering Different Technologies”
Luis F. Grisales, Alejandro Grajales, Oscar D. Montoya, Ricardo A. Hincapié and Mauricio Granada
15:40
“Black Hole Algorithm for Non-technical Losses Characterization”
Douglas Rodrigues, Caio César Oba Ramos, André Nunes Souza and Joao Paulo Papa
Gustavo Freitas Sanchez, Mario Saldanha, Bruno Zatt, Marcelo Porto and Luciano Agostini
IBERCHIP - Session V-C / Sala Ciudadela
Fuzzy logic & Neural Networks / Session chair: ALESSANDRO GIRARDI
IBERCHIP - Session IV-C / Sala Ciudadela
CAD & Digital Design / Session chair: JULIO PEREZ ACLE
9:00
“LSPart: A Novel Tool for the Decomposition of Low-Power Gated-Clock Finite State Machines”
Luiz Ferreira, Gabriel Dalalio, Duarte Oliveira and Lester Faria
9:20
“An Approach for Design of Asynchronous Systems with Bundled-Data Implementation”
Kledermon Garcia, Duarte Oliveira and Roberto D’Amore
9:40
“Estudo e Implementação do Algoritmo Simulated Annealing para Posicionamento
de Células utilizando LabVIEW”
Walter Enrique, Calienes Bartra and Ricardo Reis
10:00
“Jezz: An Incremental Legalizer”
Guilherme Flach, Julia Puget, Jucemar Monteiro, Mateus Fogaça, Marcelo Johann, Paulo
Butzen and Ricardo Reis
10:20
“Digital IC Design Flow at IC-Brazil Training Program TC1”
Lucas A. de Paris, Pedro Toledo, Jerson P. Guex, Henrique Fellini, Mauro A. Costa Jr.,
Antonio Felipe C. de Almeida, Everton Reckziegel, Thiago N. Oliveira and Eric E. Fabris
16
15:00
“Propuesta de una arquitectura para una red neuronal artificial RBF sobre un FPGA”
Niels Prieto Bejar and Carlos Silva Cárdenas
15:20
“Simulation and Implementation of Nonlinear Controlled Oscillatory States in a DC
Motor with a Fuzzy Logic Controller using Concretion Based on Boolean Relations”
Andrés Camilo Barragán Pinzón
17
Thursday 26th February, 16:20 - 17:00
Young Professionals/MSc/PhD Students Forum - Poster Session
Thursday 26th February, 17:00 - 18:40
LASCAS - Session VI-A / Sala Reconquista
Session chair: MAURICIO PARDO
RF Circuits & Systems / Session chair: MANUEL DELGADO RESTITUTO
“Frame-level Redundancy Correction Technique for SRAM-based FPGAs”
Jorge Tonfat
17:00
“A Charge Transfer-Based High Performance, Ultra-Low Power PLL Charge Pump”
Susan Schober and John Choma
17:20
“A 0.55-V 1-GHz Frequency Synthesizer PLL for Ultra-Low-Voltage Ultra-Low-Power Applications”
17:40
“Design Optimization of a CMOS RF Detector”
Nicolas Barabino and Fernando Silveira
18:00
“Multimode 2.4 GHz CMOS Power Amplifier with Gain Control for Efficiency
Enhancement at Power Backoff”
Edson Santos, Bernardo Leite and André Mariano
18:20
“A Digitally Controlled Oscillator for Fine-Grained Local Clock Generators in MPSoCs”
Guilherme Heck, Leandro Heck, Matheus Moreira, Fernando Moraes and Ney Calazans
“A Study on Buffer Distribution for RRAM-based FPGA Structure Integrated System laboratory”
Somayyeh Rahimian
“Reliability Evaluation of Combinational Logic Structures”
Eduardo Liebl
“A Precision Flicker Noise Measurement Setup”
Rafael Puyol
“Analysis of Optimization Algorithms for Sizing Analog Circuits”
Robson A. Domanski
“Circuit Design for Sequential Logic Cells Validation”
Helder H. Avelar
“Design and digital implementation of the MAC layer of the Bluetooth standard”
Jorge Sanchez-Venegas
“A New Approach for Designing Low Power, Low Noise Multi-GHz Phase Locked Loops in Deep
Sub-μm Digital CMOS”
Susan Schober
“Special Signal Non-Default Routing Rules for Electromigration Improvement”
Lucas de Paris
“HW/SW Co-design of a Reconfigurable NoC for Telecommunication Algorithms”
Blanca Gea
Omar Abdelfattah, Ishiang Shih, Gordon Roberts and Yi-Chi Shih
LASCAS - Session VI-B / Sala Cabildo
Digital & ASIC Design / Session chair: CONRADO ROSSI
17:00
“ASIC Design and Prototyping for Education and Innovation with a Look on Latin America”
Jacobus Swart and Carl Das
17:20
“Overhead for Independent Net Approach for Global Routing”
Diego Tumelero, Guilherme Bontorin and Ricardo Reis
17:40
“A Design Methodology using Flip-Flops controlled by PVT variation detection”
Alexandro Giron, Victor Avendano and Esteban Martinez
18:00
“BAT-Hermes: A Transition-Signaling Bundled-Data NoC Router”
18:20
“A Fast Pruning Technique for Low-Power Inexact Circuit Design”
Johan Broc, Luca Amaru, JaumeJoven Murillo, Pierre-Emmanuel Gaillardon, Krishna
Palem and Giovanni De Micheli
Matheus Gibiluka, Matheus Trevisan Moreira, Fernando Gehm Moraes and Ney Laert Vilar Calazans
IBERCHIP - Session VI-C / Sala Ciudadela
Signal Processing in the Digital Domain / Session chair: JOSÉ A. APOLINARIO JR.
17:00
“Amplitude-transformed cosine compensator for CIC-based decimation filters”
David Ernesto Troncoso Romero
17:20
“Análise da Robustez a Falhas de um Filtro FIR”
Helder Avelar, Denis Franco and Paulo Butzen
17:40
“Síntesis e implementación de filtros adaptativos para reducción de ruido en señales
de audio en un sistema embebido basado en arquitectura ARM CORTEX-M4”
Juan Sebastian Rubiano Labrador, Héctor Leonardo Garzón, Jenny Zolanda Castellanos and Nubia Esperanza Aguilar
18
18:00
“Modelo de referencia de un modulador de la norma DTMB de Televisión Digital”
Reinier Díaz and Ernesto Fontes
18:20
“High Performance 2D-DCT Architecture for HEVC Encoder”
Maher Abdelrasoul, Mohammed Sayed, Maha Elsabrouty and Victor Goulart
19
Friday 27th February, 10:00 - 10:50
Friday 27th February, 10:50 - 12:30
LASCAS - Poster Session II
LASCAS - Session VII-A / Sala Reconquista
Session chair: LEONARDO BARBONI
Modeling & Simulation of FET Devices / Session chair: JACOBUS SWART
“Automated RDSon Characterization for Power MOSFETS”
Pedro J Escalona Cruz, Manuel A. Jiménez-Cedeño and Rogelio Palomera-García
10:50
“Development of a Compact Model for Tunnel FETs Designed for Circuit Simulation”
Matthias Schmidt and Carlos Galup-Montoro
“Real time image compression for eye tracking application”
Frederic Amiel, Barry Boubaccar, Maria Trocan and Marc Swynghedauw
11:10
“A Complete Compact Model for Flicker Noise in MOS Transistors”
Alfredo Arnaud and Alain Hoffmann
“Design and construction of a prototype system for gait analysis for research in subjects with
balance problems”
Luis Anza, Enrique Ferreira and Hamlet Suarez
11:30
“Threshold voltage extraction circuit for low voltage CMOS design using basic long-channel MOSFET”
11:50
“Nanoscale FinFET Global Parameter Extraction for the BSIM-CMG Model”
Alessandra Leonhardt, Luiz Fernando Ferreira and Sergio Bampi
12:10
“Techniques for square ELT simulation”
Pablo I. Vaz, Alberto Wiltgen Júnior and Gilson Inácio Wirth
“Evaluating SEU Fault-Injection on Parallel Applications Implemented on Multicore Processors”
Vanessa Vargas, Pablo Ramos, Raoul Velazco, Jean-François Méhaut and Nacer-Edine Zergainoh
“Evaluation of the clustering of video frames using Rank and Histogram methods with
Euclidean and City Block distance measurement for different levels of threshold”
Eddie Galarza, Nicolás Guil and Julián Ramos
“A novel Asynchronous Interface with Pausible Clock for Partitioned Synchronous Modules”
Duarte Oliveira, Tiago Curtinhas, Lester Faria and Leonardo Romano
“Design of an IDM-Based Determinant computing unit for a 130nm low power CMOS ASIC
acoustic localization processor”
Roberto Cerdas-Robles, Rodriguez Juan Agustin, Alfonso Chacon and Pedro Julian
“Modeling the Impact of Heavy Ion on FDSOI NanoCMOS”
Walter Enrique Calienes Bartra, Ricardo Reis and Andrei Vladimirescu
IBERCHIP - Poster Session II
Session chair: LEONARDO BARBONI
“Análise da influência da intensidade das forças de espalhamento no algoritmo SimPL”
Mateus Fogaça, Cristina Meinhardt, Paulo Francisco Butzen and Guilherme Augusto Flach
Luis Eduardo Toledo, Pablo Petrashin, Walter José Lancioni and Carlos Daniel Vazquez
LASCAS - Session VII-B / Sala Cabildo
FPGA-Based Applications / Session chair: JULIO PEREZ ACLE
10:50
“Hardware Implementation of a FPGA-based Universal Link for LVDS communications”
Giancarlo Patino, Luis Sanchez, Victor Murray and James Lyke
11:10
“An FPGA-Based Time-Domain Frequency Shifter with Application to LTE and LTE-A Systems”
Felipe Augusto Pereira de Figueiredo, Fabiano S. Mathilde, Fabrício L. Figueiredo and
Fabbryccio A. C. M. Cardoso
11:30
“A Study on Buffer Distribution for RRAM-based FPGA Structure”
Somayyeh Rahimian Omam, Xifan Tang, Pierre-Emmanuel Gaillardon and Giovanni De Micheli
11:50
“Dedicated Hardware for FFT Based Fast Acquisition of GNSS Signals”
Pablo Ezequiel Leibovich, Juan Gabriel Díaz, Javier Gonzalo García and Pedro Agustin Roncagliolo
12:10
“Implementation of a digital integrated circuit for the detection of illegal hunting and logging”
Carlos Salazar-Garcia, Jordan Montero, Pablo Alvarado-Moya, Rodriguez Juan Agustin and Alfonso Chacon
“Diseño y fabricación nacional de un circuito impreso multicapa con impedancia controlada
y cupón de prueba asociado”
Diego Brengi, David Caruso and Noelia Scotti
Analog & RF / Session chair: LINDER REYES
“A Terahertz Focal Plane Array for Imaging Applications in 180nm CMOS Technology”
Francisco Brito Filho
10:50
“PyHDL - A Cross-compiler from Pure Python to Hardware Description Languages for Modeling
and Simulation of Embedded Systems”
Jaime-Alberto Parra-Plaza
11:10
“Implementation of a Current Mode Max-Min Circuit in CMOS Technology”
Leonardo Mesquita, Paloma Maria Silva Rocha Rizol and Rodrigo Bispo Santos
“A Dual Reset D Flip-Flop Phase-Frequency Detector for Phase Locked Loops”
Susan Schober and John Choma
11:30
“Metodologia gm/ID com Redes Neurais Artificiais para o Projeto de Circuitos Analógicos
com Nanodispositivos”
Tanísia Possani and Alessandro Girardi
“Análise do Impacto da Variabilidade Física nas correntes ION e IOFF de dispositivos
FinFET sub 20nm”
Alexandra Lackmann Zimpeck, Cristina Meinhardt and Ricardo Reis
11:50
“Efficient High-Frequency Spin-Torque Oscillators Composed of Two Three-layer
MgO-MTJs with a Common Free Layer”
Alexander Makarov, Thomas Windbacher, Viktor Sverdlov and Siegfried Selberherr
12:10
“A 2.4 GHz Differential Up-Converter Flipped Voltage Follower Harmonic Mixer”
20
IBERCHIP - Session VII-C / Sala Ciudadela
“Una metodología para el diseño de filtros pasabanda asimétricos de alta Q y orden
fraccional a partir de integradores de orden entero”
Carlos Muñiz-Montero, Luis A Sánchez-Gaspariano, Carlos Sánchez-López and Alejandro Díaz-Sánchez
Gregorio Zamora-Mejía, José R. Cano-Martínez, Jaime Martínez-Castillo, and Alejandro Díaz-Sánchez
21
Friday 27th February, 15:00 - 16:40
LASCAS - Session VIII-A / Sala Reconquista
Analog & Mixed-Signal Circuits / Session chair: MACIEJ OGORZALEK
15:00
“S-Plane Bode Plots - Identifying Poles and Zeros in a Circuit Transfer Function”
Reza Hashemian
15:20
“Design of an Integrated Sampling and Conversion System for Energy Meters”
Evandro Cotrim, Luis Ferreira and Tales Pimenta
15:40
“Modeling, Simulation and Experimental Set-Up of a Boost-Flyback Converter”
Frank Florez, Juan Muñoz and Fabiola Angulo
16:00
“High Stability Voltage Controlled Current Source for Cervical Cancer Detection
using Electrical Impedance Spectroscopy”
José Alejandro Amaya Palacio and Wilhelmus Van Noije
LASCAS - Session VIII-B / Sala Cabildo
Biomedical & Neuromorphic Circuits and Systems / Session chair: ALFREDO ARNAUD
15:00
“A study to implement a Brain-Computer Interface (BCI) based on Sensorimotor Rhythms”
Israel S. Santos and Marilda M. Spindola
15:20
“Single Frequency Electrical Impedance Tomography System with Offline Reconstruction Algorithm”
15:40
“An RRAM-Based Oscillatory Neural Network”
Thomas Jackson, Abhishek Sharma, James Bain, Jeffrey Weldon and Lawrence Pileggi
16:00
“Step Down DC/DC converter for Micro-Power Medical Applications”
Matias Miguez, Alfredo Arnaud, Alejandro Oliva and Pedro Julian
16:20
“A Safe MOSFET Driver for Stimulation of Biological Tissue”
Joel Gak, Alfredo Arnaud and Pablo Mandolesi
Leonardo Cechet Moro and Rodrigo Wolff Porto
LASCAS - Session VIII-C / Sala Ciudadela
Computing Techniques / Session chair: RICARDO REIS
15:00
“Alchemy: An MSP430-based Reconfigurable Processor Architecture”
Caio S. Oliveira and Diógenes C. Da Silva Júnior
15:20
“Efficient Emulation of Quantum Circuits on Classical Hardware”
Calebe Conceicao and Ricardo Reis
15:40
“Towards reversible QCA computers: reversible gates and ALU”
Jeferson Chaves, Douglas Silva, Victor Camargos and Omar Vilela Neto
16:00
“TSV protection: Towards secure 3D-MPSOC”
Martha Johanna Sepulveda, Guy Gogniat, Daniel Florez, Jean-Philippe Diguet, Ricardo
Pires and Marius Strum
16:20
“Multi-hop Collaborative Min-Max Localization”
Alan Sá, Nadia Nedjah and LuizaMourelle
22
23
Conference Hotel
Gala Dinner
Address: Rambla Gran Bretaña 473
Tel: 2916 0001
Address: PeatonalSarandí 586
Tel: 2915 7820
NH COLUMBIA
24
CLUB URUGUAY