1. technology and computing

Workshop Proceedings
Organized by
Centro Universitário da FEI
Technically Sponsored by
IEEE FEI EDS Student Chapter
IEEE ED South Brazil Chapter,
IEEE SSCS Chapter of the South Brazil Session
IEEE UNICAMP ED Student Branch Chapter
Brazilian Microelectronics Society
NAMITEC Science & Technology National Institute
Sponsored by
CNPq
Tektronix
Organizing Committee
Marcelo Antonio Pavanello
Michelly de Souza
Renan Trevisoli Doria
Renato Camargo Giacomini
Rodrigo Trevisoli Doria
Salvador Pinillos Gimenez
2015
Preface
This volume contains the papers presented at SEMINATEC 2015: X Workshop
on Semiconductors and Micro&Nano Technology held on April 9-10, 2015 in S˜ao
Bernardo do Campo.
The SEMINATEC 2015 has been a continuation of previous workshops, all
focused on technology trends in the areas of micro and nanotecnology.
SEMINATEC has been organized by the Centro Universit´ario da FEI, in
S˜
ao Bernardo do Campo, Brazil, with support from the CNPq, and promoted
by the IEEE FEI EDS Student Chapter, the IEEE ED South Brazil Chapter,
the IEEE SSCS Chapter of the South Brazil Session, the IEEE UNICAMP
ED Student Branch Chapter, the Brazilian Microelectronics Society, and the
NAMITEC Science&Technology national institute.
We would like to sincerely express our gratitude to CNPq, Tektronix and
Centro Universit´
ario da FEI for their support.
April, 2015
Sao Bernardo do Campo
Marcelo Antonio Pavanello
Michelly de Souza
Renan Trevisoli Doria
Renato Camargo Giacomini
Rodrigo Trevisoli Doria
Salvador Pinillos Gimenez
Workshop Program
Thursday, April 09, 2015
08:00
Registration
08:50
Welcome and Introduction
09:00
Thermo-magnetic effects in nano scaled FET's: characterization, modelling, and
simulation
Prof. Edmundo A. Gutiérrez - INAOE, Mexico (IEEE EDS Distinguished Lecturer)
10:30
Coffee Break
11:00
INCT NAMITEC
Prof. Nilton Morimoto - USP, Brazil
12:00
Lunch
14:00
Smart sensor technology for niche applications
Prof. Edval Santos - UFPE, Brazil (IEEE EDS Distinguished Lecturer)
15:30
Coffee Break
16:00
On-chip capacitance ratio measurement using a switched-capacitor filter
Dr. Antonio Petraglia - UFRJ, Brazil
17:30
Poster Session & Cocktail
Friday, April 10, 2015
09:00
Theory of resistive switching in Memristors
Prof. Gustavo Dalpian - UFABC, Brazil
10:30
Coffee Break
11:00
Semiconductor Analysis from Attoampere to Kilovolts
Raphael Mendes Motta - Tektronix, Brazil
12:00
Lunch
14:00
Reliability of MOS Devices and Circuits
Prof. Gilson Inácio Wirth - UFRGS, Brazil
15:30
Concluding Remarks and Coffee End
Table of Contents
The New 30 THz Solar Telescope in S˜ao Paulo, Brazil . . . . . . . . . . . . . . . . .
A.S. Kudaka, M.M. Cassiano, R. Marcon, D.P. Cabezas, L.O.T. Fernandes, R.F. Hidalgo Ramirez, P. Kaufmann and R.V. de Souza
Design of 0.13m CMOS Low Noise Transimpedance Amplifiers for 10
Gbps Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Andre Ponchet, Ezio Bastida, Jacobus Swart and Roberto Panepucci
Development of Arrays of Field Effect Transistors Based on CVD
Graphene . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Aline M. Pascon, Cecilia C. C. Silva, Jair F. Souza, Leonardo R. C.
Fonseca and Jose A. Diniz
HATS: Ground-Based New Tool for THz Solar Flare Observations . . . . . .
R. Marcon, P. Kaufmann, A. Abrantes, E. Bortolucci, L. Fernandes,
A. Kudaka, N. Machado and F.C. Rufino
Reducing the Off-State Leakage Current for Applications in Radioactive
Environment by Using the Wave Layout for MOSFETs . . . . . . . . . . . . . . . .
Rafael Navarenho de Souza, Marcilei Silveira and Salvador Gimenez
Low-dropout Regulator Output Capacitor-free Topology . . . . . . . . . . . . . . .
Renan Martucci
1
3
5
7
9
111
ELECTROSPUNNANOFIBERSWITHINCORPORATED
PARTICLES AS MEMBRANE FOR SENSORS . . . . . . . . . . . . . . . . . . . . . .
Dem´etrius Saraiva Gomes and Ana Neilde Rodrigues Da Silva
13
Electrical characterization of MOS capacitors with thin silicon
oxynitrides aiming at MOS tunnel diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Verˆ
onica Christiano and Sebasti˜
ao G. Dos Santos Filho
15
Dielectrophoretic manipulation of individual nickel nanowires for
electrical transport measurements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Marcos Vinicius Puydinger Dos Santos, Lucas Lima, Rafael Mayer,
Fanny B´eron, Kleber Pirota, Stanislav Moshkalev and Jos´e Diniz
Visibility of Weak THz Sources on a Bright Background . . . . . . . . . . . . . . .
R.V. Souza, P. Kaufmann, D.P. Cabezas and L.T. Manera
17
19
Analysis of Vertical Field Dependent Mobility Model Applied to
FinFET Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Danilo O. Silva, Arianne S. N. Pereira and Renato Giacomini
21
Intrinsic Length and Temperature Influence on the Operation of PIN
SOI Photodiodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Carla Novo, Jo˜
ao Batista, Renato Giacomini and Denis Flandre
23
Study of gated PIN CMOS BULK photodiode concerning intrinsic
concentration and gate bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Renato Zapata Lusni, Carla Novo and Renato Giacomini
25
Short Channel Effects Comparison between Double and Triple Gate
Junctionless Nanowire Transistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Bruna Paz and Marcelo Antonio Pavanello
27
Modelling of the leakage current in MOS thin silicon oxynitrides aiming
at MOS tunnel diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B´
arbara Alandia, Verˆ
onica Christiano and Sebasti˜
ao Dos Santos
29
The effect of bias in X-Ray Effects on MOSFETs . . . . . . . . . . . . . . . . . . . . .
Felipe Leite, Marcilei Aparecida Guazzelli Da Silveira and Roberto Baginski Batista Santos
31
OCTO Layout Variations as an Alternative to Mitigate TID Effects . . . . .
Leonardo Fino, Marcilei Aparecida Guazzelli Da Silveira, Christian Renaux, Denis Flandre and Salvador Gimenez
33
Demonstration of a Low Voltage Power Converter with Application to
Photovoltaic Cells . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Antonio Telles, Saulo Finco and Jair Lins De Emeri Jr.
Photonic-Integrated Circuit Simulation with Measurement-extracted
Performance for Modulation and Photodetection . . . . . . . . . . . . . . . . . . . . . .
Stefan Tenenbaum, Leandro Zanvettor, C´elio Finardi, Andr´e Ponchet
and Roberto Panepucci
35
37
Process and Electrical 3D Simulations of Fabricated FinFET using
Brazilian Facilities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
M. A. Keiler, L. P. B. Lima, M. V. P. Dos Santos and J. A. Diniz
39
Study of Low-Field Mobility on SOI n-FinFETs with Standard and
Rotated Substrate Orientations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Thales Augusto Ribeiro and Marcelo Antonio Pavanello
41
Behavior of Irradiated MOSFETs submitted to Thermal Aneealing . . . . . .
Karlheinz Cirne, Marcilei Aparecida Guazzelli Da Silveira, Felipe Leite,
Nilberto Medina and Roberto Baginski Batista Santos
43
Analysis of Common-Source Current Mirrors Implemented with
Asymmetric Self-Cascode and Graded-Channel SOI nMOSFETs . . . . . . . .
Rafael Assalti and Michelly de Souza
45
Effects of High Temperature on the Harmonic Distortion of the
Asymmetric Self-Cascode of SOI nMOSFETs . . . . . . . . . . . . . . . . . . . . . . . .
L´ıgia D’Oliveira, Rodrigo Doria and Michelly de Souza
47
Drain Current Analysis in Planar MOS Magnetic Field Sensor with
Asymmetric Contacts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Rodrigo Silva, Andr´e Perin and Renato Giacomini
49
The influence of the mobility in JNT and FinFET devices with Self
Heating Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Genaro Mariniello and Marcelo Antonio Pavanello
51
Project and Development of Submicron pMOSFET Junctionless
Nanowire Transistor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Juliana Nemer and Marcelo Antonio Pavanello
53
Study of the Low-frequency noise in Submicron Graded-Channel Silicon
on Insulator nMOSFETS at room temperature . . . . . . . . . . . . . . . . . . . . . . .
Allan Molto, Rodrigo T. Doria, Michelly de Souza and Marcelo Antonio
Pavanello
MOS-Bipolar Pseudo-resistor Characterization Circuit and Extraction
Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pedro Benko and Renato Giacomini
55
57
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
The New 30 THz Solar Telescope in São Paulo, Brazil
A. S. Kudakaa, M. M. Cassianoa, R. Marconb, D. P. Cabezasa, L.O.T. Fernandesa, R.F. Hidalgo
Ramireza, P. Kaufmanna,c, R. V. de Souzaa,c
a
Escola de Engenharia, CRAAM, Universidade Presbiteriana Mackenzie, São Paulo, SP, Brazil
Instituto de Física “Gleb Wataghin”, Universidade Estadual de Campinas and Observatório Solar “Bernard Lyot”,
Campinas, SP, Brazil
a,c
Escola de Engenharia, CRAAM, Universidade Presbiteriana Mackenzie, São Paulo, SP and Centro de Componentes
Semicondutores, Universidade Estadual de Campinas, Campinas, SP, Brazil
e-mail: [email protected]
b
have found quiescent “plages” and small brightening
fluctuations during small class GOES soft X-ray bursts,
similarly to near-IR activity found in association to
large flares. We present here the recently installed 30
THz solar flare telescope in São Paulo, operating
simultaneously with an Hα telescope, giving a brief
technical description illustrated with the first results
obtained.
1. Abstract
It has been found that solar bursts exhibit one
unexpected spectral components with fluxes increasing
for larger sub-THz frequencies, distinct from the well
known microwave emission maximizing at few to tens
of GHz. The high frequency component has been
confirmed by recent 30 THz solar flare observations of
impulsive bursts with flux intensities considerably
larger than fluxes at sub-THz and microwaves
frequencies. These results raise serious problems for
interpretation. High cadence solar observations at 30
THz (continuum) are therefore an important tool for the
study of active regions and flaring events. We report the
recent installation of a new 30 THz solar telescope,
located at the top of one of the University’s buildings.
The instrument utilizes a Hale-type coelostat with two
20cm diameter flat mirrors sending light to a 15 cm
mirror Newtonian telescope. Radiation is directed to a
room temperature microbolometer array camera.
Observations are usually obtained with 5 frames/s
cadence. One 60mm Hα refractor has been added to
observe simultaneously. We describe the new
observatory giving examples of the first results
obtained.
3. The 30 THz solar telescope setup in São Paulo
The São Paulo 30 THz telescope follows the same
design utilized at El Leoncito [6]. A simplified block
diagram is shown in Figure 1. The instrument utilizes a
Hale-type coelostat with two 20 cm diameter flat
mirrors (Figure 2 (a)) sending light to a 15 cm mirror,
120 cm focal length Newtonian telescope feeding an
early type Wuhan IR928 30 THz uncooled camera
amorphous silicon 320 x 240 microbolometer array
sensitive to about 0.5 K (Figure 2(b)). The solar disk
image size on the array is set by the distance of the
camera to the primary, while the image quality is set by
afocal adjustment of the camera Germanium lens
placement with respect to the array.
2. Introduction
A number of solar bursts exhibit unexpected distinct
spectral components: one corresponds to the well
known microwave emission maximizing at few to tens
of GHz, and another with fluxes increasing for larger
sub-THz frequencies. Observations carried out at 0.2
and 0.4 THz by the Solar Submillimeter Telescope
(SST), in El Leoncito, San Juan, Argentina, have clearly
evidenced the sub-THz flux component increasing with
frequency [for example 1-3]. A dramatic demonstration
of this component was shown with the 30 THz
observation at El Leoncito of one intense 30 THz
impulsive burst exhibiting flux several times larger than
sub-THz and the microwave components, associated to
a white light flare [4].
One first setup designed to detect solar flares at 30
THz has been installed at “Bernard Lyot” Solar
Observatory, Campinas, Brazil and another one at El
Leoncito observatory, in Argentina Andes [5-7] . They
Fig. 1. Simplified block diagram of São Paulo 30 THz 15 cm
Newtonian solar telescope showing the principal optical setup
arrangements, and the parallel Hα telescope.
The “photometric beam” is set by the diffraction
limit angle, which is of about 15” for the 15 cm
aperture. The camera produces analog video signal
1
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
by two orders of magnitude compared to microwaves
and sub-THz fluxes. The broad microwaves to 30 THz
spectra for these two events confirm the existence of
two separate components; one is the well known
emission spectrum with a maximum in the microwave
range of frequencies, and the other with fluxes
increasing with frequencies in the sub-THz to THz
range [1].
which is converted into 640x480 pixels frames digital
data usually taken at 5/s cadence,
4. Concluding remarks
The 30 THz solar telescope will receive one
upgraded camera, which shall improve the sensitivity by
a factor of 5. Regular observations are planned together
with the Hα telescope, in support of 30 THz and
HASTA Hα observations carried out at El Leonito,
Argentina Andes.
(a)
(b)
Fig. 2. (a) Hale-type coelostat installed at the top of one
university’s building to project the solar radiation into the
laboratory. (b) TheNewtonian telescope. The 15 cm primary is
in the background. In the foreground the secondary facing the
primary deflects radiation into the 30 THz camera, at the top.
Acknowledgements
3. First results
We acknowledge M. Luoni (IAFE) and C. Francile
(OAFA for providing with Argentina HASTA Hα data
and the collaboration in observations by M.V. Gutierrez
Escate and J.F. Valle Silva. This research was partially
funded by Brazil agencies FAPESP (Proc. Nr.
2006/06847-1 and 2013/24155-3), CNPq, Mackpesquisa
and US AFOSR.
Two intense solar 30 THz impulsive bursts were
detected on August 1st and October 27, 2014, associated
to soft X-ray GOES class M and X events, shown in
Figure 3 (a,b).
References
[1] Kaufmann, P., de Castro, C. G., Levato, H., Gary, D. E.,
Costa, J. E., Marun, A., Pereyra, P., Valio, A. and Correia, E. :
2004, Astrophys.J. 603, L121.
[2] Kaufmann, P. Giménez de Castro, C. G., Correia, E.,
Costa, J. E., Raulin, J. P. and Válio, A. S.: 2009, Solar Phys.
255, 131.
[3] Silva, A.V.R. : 2007, Share, G. H., Murphy, R. J., Costa, J.
E., de Castro, C. G., Raulin, J.-P. and Kaufmann, P.: Solar
Phys. 245, 311.
[4] Kaufmann, P., White, S. M., Freeland, S. L., Marcon, R.,
Fernandes, L. O., Kudaka, A. S., de Souza, R. V., Aballay, J.
L., Fernandez, G., Godoy, R., Marun, A., Valio, A., Raulin, J.P. and Giménez de Castro, C. G.: 2013, Astrophys.J. 768,
L134.
[5] Melo, A.M., Kaufmann, P., Kudaka, A. S., Raulin, J.-P.,
Marcon, R., Marun, A., Pereyra, P. and Levato, H. : 2006,
Publ.Astron.Soc. Pacific 118, 1558.
[6] Marcon, R., Kaufmann, P., Melo, A. M., Kudaka, A. S.
and Tandberg-Hanssen, E.: 2008, Publ. Astron, Soc. Pacific
120, 16.
[7] Cassiano, M. M. Kaufmann, P., Marcon, R., Kudaka, A.
S., Marun, A., Godoy, R., Pereyra, P., Melo, A. and Levato,
H.: 2010, Solar Phys. 264, 71.
[8] Miteva, R., Kaufmann, P., Cabezas, D. P., Fernandes, L.
O. T., Freeland, S. L.,Karlický, M., Kerdraon, A., Kudaka, A.
S., Luoni, M. L., Marcon, R., Raulin1, J.-P.,Trottet, G., White,
S. M.: 2015, Astron.Astrophys., submitted.
[9] Kaufmann, P., White, S.M., Marcon, R., Kudaka, A.S.,
Cabezas, D., Cassiano, M.M., Francile, C., Fernandes, L.O.T.,
Hidalgo Ramirez, R.F., Luoni, M., Marun, A., Pereyra, P.,
Raulin, J.-P., de Souza , R. V.: 2015, J.Geophys.Res.,
submitted.
(a)
(b)
Fig. 3. 30 THz solar flare brightening near the peak burst
emission compared to Hα image obtained by HASTA: (a)
August 1s, 2014 [9]; (b) October 27, 2014[6].
Estimated flux densities were of about 20000 SFU and
35000 SFU respectively (1 SFU = 10-22W-1m-2), larger
2
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
Design of 0.13µm CMOS Low Noise Broadband Amplifiers for 10 Gbps
Applications
A. F. Poncheta , E. M. Bastidaa, J. W. Swartb and R. R. Panepuccia
a
CTI Renato Archer
Universidade Estadual de Campinas - UNICAMP
e-mail: [email protected]; [email protected];
[email protected]; [email protected]
b
1. Abstract
This paper presents a set of two broadband low noise
amplifiers in 0.13µm CMOS technology. Experimental
results indicate that the amplifiers can be used as
transimpedance amplifiers for 10 Gbps applications, since
S21 is flat from 40 kHz up to 8 GHz. Careful layout design
and bias optimization guarantee a very low noise figure
compared to other 0.13 µm CMOS designs reported in
literature.
2. Introduction
A transimpedance amplifier for optical receivers
must be designed with a minimal in band equivalent
input noise current since this figure basically determines
the overall receiver sensitivity. In order to obtain this
result, as it was demonstrated in reference [1], we used
the criterion of minimizing the noise factor F50 of the
designed circuits.
Although CMOS technologies with gate lengths
equal or lower than 90 nm should allow better circuit
noise and gain performances, they were still very
expensive. For this reason, we decided to use a 0.13 µm
CMOS technology which offers a better trade-off
between cost and performance for 10 Gbps optical
receivers applications.
Fig.1: nmos transistor bias point optimization.
The topology of the first CMOS circuit is formed by
series connection of two cascode stages. This TIA has
17dB gain with a 9.4 GHz bandwidth and a 54 dBΩ
transimpedance gain with 11 GHz bandwidth.
3. CMOS Circuit Design and Performances
For the design of the 10 Gbps circuits, a common
used topology for the TIA is the regulated cascode [1,
7]. This topology has a low input resistance and it can
be broadband without the use of inductive peaking
techniques. However, regulated cascode suffers of high
input noise density. Since the TIA is the first block of
the receiver chain, noise figure is critical.
Both circuits presented in this work have as the
input stage a cascode. For optimal noise performance,
the input cascode was designed with optimal finger
width and bias point optimization. The finger width of
the first stage was set to 2µm to reduce the input noise
density current. The bias point was defined based on the
analysis of one single nmos transistor. Ft, current
density and minimum noise figure are shown in figure
1. Gain and bandwidth were optimized based on Ft
versus current density analysis. Bandwith was
maximized with negative feedback and inductive
peaking techniques.
Fig.2: Two stage cascode TIA schematic.
Fig.3: Two Stage Cascode TIA Microphotograph.
Fig. 4 shows the circuit performance.
3
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
Table I shows a performance comparison between our
10 Gbps TIAs and previously developed circuits
available from literature.
TABLE I.
DEVELOPED
PERFORMANCE COMPARISON WITH PREVIOUSLY
SI BASED CMOS (C) AND BICMOS (B) TIAS
Reference
[2]
[3]
[4]
[5]
[6]
[7](*)
This work
ZT
75
62.3
54
74
54
52.9
54
Supply Voltage (V)
1.8
1.8
1.8
2.5
1.0
1.2
1.5
PD capacitance (fF)
450
150
250
220
220
400
150
Bandwidth
With PD (GHz)
7.2
9
9.2
7.4
13.4
14.3
11
7.5
Noise current
density (pA/√ ))
19
17
11
≥ 28
39
6.6
5.9
Pdc (mW)
91.8
55
30
50
Fig.4. Two Stage Cascode s- parameters and ZT.
The second CMOS circuit is composed by a cascode
input stage followed by two single inverter stages and a
final source follower stage. This circuit was designed to
work as a broadband TIA and also as a broadband LNA.
When loaded with a 150 fF PIN photodiode it has 7.5
GHz bandwidth and 50 dBΩ transimpedance gain.
Fig.5 shows its basic circuit diagram. Fig. 6 the chip
microphotograph and Fig. 7 the experimental results.
108
137
200
2.2
2.7
(*) Simulated results
4. Conclusions
Two broadband low noise amplifiers were presented in
this works. Experimental results show that the two
amplifiers have bandwidth suitable for 10 Gbps
applications. Table I shows that both circuits have the
lowest noise current density compared to other designs.
Acknowledgments
We would like to thank Fapesp and CTI for the
financial support and equipment for measurements.
Fig.5: Chip2 schematics.
References
[1]
[2]
[3]
Fig.6: Chip 2 Microphotograph.
[4]
[5]
[6]
[7]
Fig.7: Chip 2 S-parameters and ZT.
4
J.Gao: “Fast Calculation of Transimpedance Gain and
equivalent Input Noise Current Density for High Speed
Optical Preamplifier Design.” Microwave Journal May
12 2011.
Jun-De Jin and S.S.H. Hsu: “A 75dBΩ 10Gbps
Transimpedance Amplifier in 0.18 nm CMOS
Technology”,
IEEE Photonics Technology Letters,
vol.20, pp.2177-2179, 2008.
A.K. Petersen et al.: “Front-end CMOS Chipset for
10Gbps Communication”, pp.93-96, Digest of 2003
RFIC Symposium .
B. Analui and H Ali: “Multi-pole Bandwidth
Enhancement Technique
for Transimpedance
Amplifiers”, European Conference on Solid State
Circuits (ESSCIRC) Proceedings, pp.303-306, Session
C16, Sept 2002.
Analog Devices ADN2028 10 Gbps Transimpedance
Amplifier Data Sheet, 2003;
C. Kromer et al, "A low-power 20 GHz 52-dBΩ
Transimpedance amplifier in 80-nm CMOS", IEEE
Journal of Solid State Circuits, vol.39, no. 6, pp.885-894,
Jun. 2004;
D. Kim et al, “12.5 Gbps Analog Front-End of an
Optical Transceiver in 0.13 µm CMOS”, 2013 IEEE
International Symposium on Circuits and Systems
(ISCAS2013), May 19-23, 2013.
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
Development of Arrays of Field Effect Transistors Based on CVD Graphene
A. M. Pascona, C. C. C. Silvaa,b, J. F. Souzaa, L. Kubotab, L. R. C. Fonsecaa and J. A. Diniza
a
Center for Semiconductors Components, School of Electrical and Computing Engineering, University of
Campinas, 13083-870 Campinas, SP, Brazil.
b
Institute of Chemistry, University of Campinas, 13083-960 Campinas, SP, Brazil.
e-mail: [email protected]
wafer that contained the arrays of FETs, we washed the
graphene several times with DI water. After that the
graphene/PMMA was transfer just in one step to the of
the devices and the PMMA was etching in acetone bath.
Fig. 1 (a) shows a CVD graphene monolayer
transferred on 300 nm SiO2, where it is possible to see
that the graphene film grew homogenous and that the
sample is free from PMMA residues and other
contamination. The Raman spectra obtained from
different areas of the CVD graphene (Fig. 1 (b))
displays the typical characteristics of a graphene
monolayer free of defects [4].
1. Abstract
We report an achievement of large area of
monolayer graphene produced by chemical vapor
deposition process and their implementation into arrays
of FETs composed by tantalum nitride electrodes.
Raman spectroscopy and electronic microscopy show us
that a large number of FET-graphene devices can be
fabricated through a simple, fast and scalable approach.
2. Introduction
Since graphene was successful isolated for the first
time by microcleaving of graphite [1], this material has
attracting a significant attention of all scientific
community, mainly due to its outstanding electronic
properties, making it an ideal material to replace the
silicon in the traditional Field Effect Transistors (FETs).
However, the implementation of graphene in the
development of FETs has two major issues that should
be overcome. The first is that graphene obtained from
microcleaving or exfoliation of graphite, does not
feature like a scalability technique to be employed in the
fabrication of arrays of FETs. The second issue is
related with the high contact resistant that appears in the
interface metal/graphene. In order to replace the silicon
like a channel material to graphene, a suitable contact
with electrodes is required. Aiming to overcome the
related issues, herein we have addressed the
achievement of large area of monolayer graphene
produced by chemical vapor deposition (CVD) process
and their implementation into arrays of FETs.
Furthermore, we evaluated the effects of replace the
conventional, non-refractory metallic electrodes such as
Ti/Au or Ti/Pd for a refractory metallic electrodes, such
as tantalum nitride (TaN) in the contact resistance [2].
3. Method and Results
The CVD graphene was grown based on the
procedure proposed by Ruoff and coworkers [3]. A
copper foil with 25µm of thickness was used as the
substrate and catalyst. The methane gas was employed
like a carbon source. The total time for the growth
process was 2 hours, under inert atmosphere at 1000ºC.
For remove the grew monolayer graphene of the copper
foil, we spin coated PMMA onto graphene followed by
the chemical etching of the copper under FeCl3 solution.
Before to do the transfer process to the top of SiO 2
Fig. 1. (a) Optical microscopy image of a monolayer of
transferred graphene on 300 nm SiO2 substrate.
Magnification 50x. In (B) Raman spectroscopy of sample
showed in (a) in different areas.
Fig. 2. (a) shows the schematic representation of our
developed FET [5]. The Figure 2 (b-c) show the CVD
graphene isolated between the source and drain TaN
electrodes, due the photolithography step followed of
the oxygen plasma etching, to remove the graphene in
5
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
the outside area. All this process was carried out directly
on a die of 2.5 cm2 containing four arrays with 300
FETs each. The last two processes define the active
region of the device, where the electronic transport will
occur through the graphene layer. These images (Fig. 2.
b-c) show that the graphene layer is in contact with the
electrodes, as the gate dielectric.
Acknowledgments
to be fabricated through a simple, fast and scalable
approach.
In future, electrical characterization will be
performed to attest the improvements achieved using
the TaN like metal for contact electrodes.
This work is financially supported by CAPES and
CNPq. CCC Silva acknowledges the Science Without
Border Program for the fellowship and the NanoMaterials and devices group (USA) for the facilities and
support in the synthesis of CVD graphene.
References
[1] K. S. Novolselov et al, Science 306, 666 (2004);
[2] A. M. Pascon et al., Phys. Status Solidi B, 1–8
(2014).
[3] Xuesong Li, et al., Science 324, 1312 (2009).
[4] A. C. Ferrari et al., PRL 97, 187401 (2006).
[5] Souza, J. F., Development of Materials and Methods
of Fabrication of Chemical/Biochemical Sensors
based on Silicon and Carbon Nanostructures
(ISFET, CNTFET and GraFET), PhD, School of
Electrical and Computer Engineering, University of
Campinas, 2012.
Fig. 2. (a) Schematic representation of a FET with graphene
layer[5]. SEM image of a monolayer graphene between
source and drain electrodes after lithography and oxygen
plasma etching processes with magnification of (b) 10000 and
(c) 50000.
4. Conclusions
At the moment, our results suggest that our method
allows that a massive number of FET-Graphene devices
6
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
HATS: Ground-Based New Tool for THz Solar Flare Observations
Rogério Marcona,b, Pierre Kaufmannc,d, André Abrantese, Emilio C. Bortoluccid, Luis Olavo T. Fernandesc,
Amauri S. Kudakac, Nelson Machadoe, Fernanda C. Rufinoa
a
Instituto de Física Gleb Wataghin, Universidade Estadual de Campinas, Campinas, SP, Brazil
b
Observatório Solar “Bernard Lyot”, Campinas, SP, Brazil
c
Escola de Engenharia, Craam, Universidade Presbiteriana Mackenzie, São Paulo, SP, Brazil
d
Centro de Componentes Semicondutores, Universidade Estadual de Campinas, Campinas, SP, Brazil
e
Propertech Ltda., Jacareí, SP, Brazil
1. Abstract
Recent sub-THz and 30 THz observations revealed an
unexpected new spectral component, with fluxes increasing
towards THz frequencies, simultaneously with the well known
component peaking at microwaves, bringing challenging
constraints for interpretation. The knowledge of the complete
THz flare spectrum is the essential requirement for
understanding the origin of this radiation. We present the
concept, fabrication and performance of a telescope
photometric system to observe solar flares at 0.85 and 1.4 THz
from the ground at a high altitude site (>5000 m), named
HATS (High Altitude Terahertz Solar telescope). An
innovative optical setup was introduced to allow observations
of the full solar disk with high sensitivity to detect small burst
transients (tens of solar flux units) with time resolution of less
than one second. The HATS experiment uses Golay cell
detector at the focus of 46 cm Newtonian telescope, installed
on a fully robotic equatorial positioner. The incoming
radiation undergoes low-pass filters made of rough surface
primary mirror and membranes, 0.85 and 1.4 THz metal mesh
band-pass filters installed in the same chopper wheel. The
HATS now undergoes operational tests in Brazil, and is
planned for operations in 2015 at a site to be selected in the
Andes Cordillera, above 5000 m altitude.
Fig. 1. The March 13, 2012 solar burst was observed at a wide
range of frequencies, from MHz, GHz (RSTN and solar mm-w
polarimeters), sub-THz (SST), 30 THz (at El Leoncito), visible, UV
(SDO), GOES soft X-rays, RHESSI soft and hard X-rays and FERMI
hard-X rays. The whole spectrum shows double components, one in
the GHz to sub-THz range, another extending to 30 THz (after [4]).
2. GHz, Sub-THz and THz Flare Observations
A number of solar bursts observed at GHz, sub-THz and 30
THz frequencies indicate an emission spectral component at
this range [1-4], distinct from the well known microwaves
emission that maximizes at few to tens GHz. These results
raise serious interpretation problems to explain both the subTHz and the concurrent microwave component [5,6] (Fig. 1).
The physical nature of the THz emission remains mysterious.
New insights on the physical processes involved need
the complete THz spectral description. Solar activity may be
observed through few atmospheric THz transmission
“windows” at exceptionally good high altitude ground based
locations [7].
3. The Ground-Based HATS Experiment
The terrestrial atmosphere present transmission windows at
sub-THz and THz frequency bands at high altitude sites for
low precipitable water vapour content (PWV) [7,8].
Transmissions better than 50% at 0.67 and 0.85 THz bands
and better than 15% at 1.3 and 1.5 THz bands can be attained
at 5000m altitude with PWV < 1mm.
A telescope has been designed for photometry of solar
flares at 0.87 and 1.4 THz. A short focal length 46 cm
diameter mirror, producing a solar image smaller than the
Golay input cone diameter (about 14 mm).
7
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
degrees the predicted minimum detectable flux densities
become ˂ 5 SFU at 0.87 THz and of ˂ 40 SFU at 1.4 THz.
A site is being selected for definitive installation and
operations in 2015. The best candidates are Chajnantor, Chile
Atacama plateau, at 5000 and Famatina Mountain, above
5200m altitude, in Argentina La Rioja region.
Acknowledgments
These researches and developments are being partially
funded by Brazil agencies FAPESP, CNPq Mackpesquisa,
INCT NAMITEC and U.S. NASA and AFOSR.
References
[1] P. Kaufmann et al. “A new solar burst spectral
component emitting only in the terahertz range”,
Astrophys.J., vol. 603, pp. L121-L124, 2004.
[2] A.V.R. Silva et al.,"Evidence that synchrotron emission
from nonthermal electrons produces the increasing
submillimeter spectral component in solar flares", Solar
Phys., vol. 245, pp. 311- 326, 2007.
[3] P. Kaufmann et al.,“Sub-terahetz, microwaves, and high
energy emissions during the December 6, 2006 flare at
18:40 UT”, Solar Phys., vol. 255, pp. 131-142. 2009.
[4] P. Kaufmann et al.: “A bright impulsive solar burst
detected at 30 THz”, Astrophys. J., vol. 768, 134 (9pp)-.
2013.
[5] G.D. Fleishman, E. Kontar, “Sub-THz Radiation
Mechanisms in Solar Flares, Astrophys. J., vol. 709, pp.
L127-L132, 2010.
[6] S. Krucker et al.: "Solar flares at submillimeter
wavelength", Astronon. Astrophys. Rev, vol. 21, , article
id. #58, 2013.
[7] J. Suen, M. Fang, P. Lubin, “Global distribution of
water vapor and cloud cover—sites for high-performance
THz applications”, IEEE Trans. THz Science and
Technology, vol. 4, pp. 86-100, 2014,
[8]
S. Matsushita, et al., “FTS measurements of submilliemeter atmospheric opacity at Pampa la Bola II:
Supra-Terehertz windowsn and model fittings”, PASP, vol. 51,
Fig. 2. Schematic diagram of HATS photometric telescope
603-624, 1999.
Fig. 3. Left, show the complete HATS assembly. Right panels, top
right: the case containing the Golay cell and chopper placed at the
Newtonian focus; middle: the chopper wheel exhibiting the windows
with metal mesh band-pass filters, one at 0.87 THz and another at
1.4 THz; lower panel shows the 46 cm rough surface mirror.
The Golay cell detector input cone is placed at the tescope
Newtonian focus, as shown in Figures 2 and 3. Band-pass
metal mesh filters are placed in the same chopper wheel. The
radiation input at each frequency is measured once every 600
ms.
Preliminary tests performed at Propertech facilities, Jacareí,
SP. Brazil have shown that the system can detect three sigma
excess temperature excess smaller than 0.5 K at each
frequency. For solar observations at an elevation angle of 45
8
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
Reducing the Off-State Leakage Current for Applications in Radiation
Environment by Using the Wave Layout for MOSFETs
Rafael Navarenho de Souzaa, Student Member, IEEE, Marcilei A. Guazzeli da Silveirab, Member,
IEEE and Salvador Pinillos Gimeneza, Member, IEEE
a
Department of Electrical Engineering, University Center of FEI, São Bernardo do Campo, São Paulo, Brazil
b Department of Physics University Center of FEI, São Bernardo do Campo, São Paulo, Brazil
1. Abstract
This paper presents an experimental comparative
study between the Metal-Oxide-Semiconductor Field
Effect Transistors (MOSFET) manufactured with the
Wave ("S" gate geometry) and the standard layout
(CnM) taking into account the Total Ionizing Dose
(TID) effects and considering that the devices were
biased during the radiation procedure to potentiate the
effects. Because of the special layout characteristics and
the different effects of the bird’s beaks regions of the
Wave nMOSFET (WnM) compared to the conventional
rectangular layout, the Wave layout proposal for
MOSFETs is able to increase the device TID tolerance
without adding any cost to the Complementary MOS
(CMOS) manufacturing process.
Fig.1. The WnM layout style top view details.
The TID effects cause long-term damage in the
oxide layers of electronic devices, worsening their
electrical performance of the MOSFET [1]. New
materials, multiple-gates and three-dimensional (3D)
devices are under intense development (1), as can be
found in the International Technology Roadmap for
Semiconductors (ITRS) [2] in order to overcome the
scaling limits [3-5]. Many efforts have been made to
improve the devices' radiation hardness, which mainly
can be divided into two categories: one is related to the
optimization of CMOS manufacturing processes with
different materials and technologies, second focuses on
using non-standard layout for MOSFET. In this context,
the innovative Wave nMOSFET [6] fits in the second
category to be one more alternative to Integrated
Circuits (ICs). Therefore, this paper presents an
experimental comparative study between the WnM and
CnM with biased devices during the radiation procedure
in order to create traps and emphasize the TID effects,
and then compare with experimental results the OffState leakage current of the CnM and WnM.
The WnM comes from the Circular Annular Gate
MOSFET (CAGM) [6], which is an asymmetric device,
because the internal region area (AINT) is different from
the external region area (AEXT). By dividing it into the
middle, moving the semicircles in the opposite
directions, and then connecting the gate to compose a
symmetrical layout with an “S” or Wave format.
The Longitudinal Electrical Field (LEF) varies in the
channel length (L) [6-8] and it is higher in the drain
region of the superior semicircle, because the drain
region area of the superior semicircle (AD_IDBC) is
smaller than the inferior semicircle area (AD_EDBC) [6-8].
It was demonstrated that the overall WnM IDS is higher
than the one found in the standard layout (CnM),
considering the same gate area (AG) and bias conditions
[6-8].
The WnM presents a different electrical behavior
and the bird’s beaks regions' parasitic transistors
activation of the WnM behave in a different way as
well. The LEF influence along the channel and parasitic
transistors activation in the BBR present different
behavior for the TID effects.
Thus, the result of the WnM IDS and the parasitic
transistors' effects of the WnM are different when
compared with the CnM result, after TID.
3. Wave Layout Details
4. Experimental Details
Figure 1 presents the layout of the WnM. It is
possible to observe the gate, the drain and source for the
superior and inferior semicircles, the longitudinal
electrical field ( / / ) in the channel, and the bird's beaks
regions (BBR).
First of all, the Devices Under Test (DUT) were
electrically characterized (Pre-Radiation condition) with
the Keithley 4200 (drain current, IDS, as a function of
the gate voltage, VGS, and of the drain voltage, VDS).
After that, the WnM and the CnM were exposed to 10
2. Introduction
9
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
keV X-rays radiation using a Shimadzu XRD-7000. The
radiations were conducted to a cumulative dose up to
1.0 Mrad at a dose rate of 400 rad/s in biased devices.
The “ON” bias state was used, which is the gate at the
bias supply voltage (5V), and the source, drain, and
substrate at ground. Bulk transistor radiated in the ON
state produces the largest radiation-induced leakage
current, and measured in its lowest current state (the
OFF state), it will show the largest increase in leakage
current [9-10].
The devices were manufactured by using the 0.35
m the “On-Semiconductor” (Bulk) manufacturing
CMOS process, via MOSIS Educational Program
(MEP). The channel length used was equal to 2.3 m
[11].
April 9 - 10, 2015, São Bernardo do Campo
6. Conclusions
The Wave layout style is able to enhance the
radiation tolerance and is less sensitive to the TID. Its
distinctive longitudinal electrical field and the different
activation of the parasitic transistors in the bird's beaks
regions of the Wave layout style for MOSFET reduce
the radiation impacts. The Off- State leakage current of
the WnM is lower than the CnM after TID.
Thus, this innovative layout can be considered as an
option to be used in ICs operating in the radiation
environment (space and medical applications).
Acknowledgments
The authors would like to thank MOSIS, CNPq,
CAPES, FINEP (CITAR) and FAPESP.
5. Experimental Results and Discussions
References
Figure 2 presents the experimental curves of the
WnM and CnM (L=2.3 m) of Log IDS/(W/L) as a
function of VGS for VDS=4V.
[1] H. Barnaby, “Total-Ionizing-Dose effects in modern
CMOS technologies,” IEEE Trans. Nuclear Science, vol. 53,
no. 6, pp. 3103- 3120, 2006.
[2] International Technology Roadmap for Semiconductors
website. Available: http://public.itrs.net/.
[3] G. K. Celler and S. Cristoloveanu, “Frontiers of silicon on
insulator,” J. Appl. Phys., vol. 93, no. 3, pp. 4955, 2003.
[4] J.P. Colinge, et al, “Silicon on insulator “gate all around”
device,” in Proc. IEDM Tech. Dig., pp. 595, 1990.
[5] X. Huang, W.-C. Lee, C. Kuo, D. Hisamoto, L. Chang, J.
Kedzierski,E. H. Anderson, H. Takeuchi, Y.-K. Choi, K.
Asano, V. Subramanian, T.-J. King, J. Bokor, and C. Hu,
“Sub-50 nm P-channel FinFET, IEEE Trans. Electron
Devices,” vol. 48, no. 5, pp. 880, 2001.
[6] S. P. Gimenez, “The Wave SOI MOSFET: A New
Accuracy Transistor Layout to Improve Drain Current and
Reduce Die Area for Current Drivers Applications,” 215th
ECS Meeting, ECS Trans., v. 19. pp. 153-158, San Francisco,
2009.
[7] A. L. da Silva, “Electrical Behavior Study of the Wave
SOI nMosfet and Conventional Counterpart,” M.S thesis FEI, São Bernardo do Campo, 2010.
[8] R. Navarenho de Souza, and S. P. Gimenez, “Experimental
Comparative Study Between the Wave Layout Style and its
Conventional Counterpart for Implementation of Analog
Integrated Circuits,” ECS Trans., v.49, pp. 519-526, 2012.
[9] J. R. Schwank, M. R. Shaneyfelt, and P. E. Dodd,
“Radiation Hardness Assurance Testing of Microelectronic
Devices and Integrated Circuits: Radiation Environments,
Physical Mechanisms, and Foundations for Hardness
Assurance,” SANDIA NAT. LAB. DOC., Albuquerque, New
Mexico, 2008.
[10] R. Shaneyfelt, J. R. Schwank, P. E. Dodd, and J. A. Felix,
“Total Ionizing Dose and Single Event Effects Hardness
Assurance Qualification Issues for Microelectronics,” IEEE
Trans. Nuclear Science, vol. NS-55, no. 4, pp.1926-1946,
Aug. 2008.
[11] The MOSIS Service, http://www.mosis.com, 2010.
Fig 2. The Log IDS/(W/L) as a function of VGS with VDS= 4 V
of the WnM and CnM for L= 2.3 m after TID.
In the Fig. 2, verify that there is a high variation of
the drain current and different behavior for the CnM and
WnM, because the devices were biased during the
radiation procedure the IOFF results are well affected
[9,10].
The Off- State leakage current (IOFF) of the CnM and
WnM prior to TID are similar, considering VGS = 0V.
However, after TID of 1 Mrad the CnM IOFF is 75%
higher (and therefore less efficient) than the one found
in the WnM IOFF. TID issues can be relieved with layout
strategies, the effects of the traps created after radiation
that cause impacts in the device operation and the
parasitic transistors' effects in the bird's beaks region
can be decreased. Hence, it is noted that the resulting
influence of the traps in the device and the parasitic
transistors activation after radiation in the WnM are
smaller than the CnM, and because of that, the WnM
has less leakage current.
10
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
Low-dropout Regulator Output Capacitor-free Topology
R. F. Martuccia and L. T. Manerab
a
M.A.Sc. Student, Author
Ph.D. Tutor, Co-Author
e-mail: [email protected]
b
B. LDO Capacitor-free with Damping factor control
LDO Capacitor free Regulator consists of some gain
stages and some control stability stages[7], [12]–[15].
The gain stages are: Differential Amplifier (1st Stage),
Transconductance Boosting (2nd Stage), PMOS pass
device (3rt Stage). For control stability, there are two
stages: Damping Factor Control (DFC) [9]-[11] and
Sense Current [15]. The purpose is the generation of a
stable reference and supply voltage for all charge load
range, without an external off-chip capacitor.
Fig. 2 provides a block diagram of the final
implemented circuit topology.
1. Abstract
Demand for system-on-chip solutions has increased
the interest in low dropout (LDO) voltage regulators
which do not require a bulky off-chip capacitor to
achieve stability and quickly transient response thereby
contributing to a small area. Also called capacitor less
LDO (CL-LDO) regulators, it provides the same
response of the classical circuit structures but without
off-chip passive and active components.
2. Low-dropout Regulator and Capacitor-free
variation
A. Classical Low-dropout Topology
The regulator circuit can be partitioned into four
functional blocks: the reference, the pass device, the
sampling resistor, and the error amplifier (Fig.1).
For the classical regulators [1]-[3], [8], there is also
an external capacitor with value of a few micro Faraday,
commercial components, not from each design
technology. This component has a equivalent series
resistance (ESR) describe in the data-sheets of each
capacitor.
The reference circuit needs to be robust at point to
provide a stable reference for the rest of the circuit. This
reference is the base for the feedback branch that come
from the sampling resistor array in proportion with the
output reference. The difference is amplified by the
error amplifier, a circuit responsible to drive a large
output capacitance from the next stage [4]-[6], the pass
device, and then a large output current is sourced by it
to all the rest of the electrical circuits of the
system-on-chip, with good power source rejection ratio
(PSRR), with good stability and small module
variations.
Fig.2. Proposed LDO Capacitor-free topology.
The first stage is the differential amplifier, which is
responsible to provide to the next stage the difference
between Bandgap reference and the output reference.
The next stage, transconductance boosting, have as
principle charge the pass device with it’s higher gate
capacitance. In total, the LDO regulator has two
feedback ways for the output signal. The first one is
made by the proportional resistive array to input
differential amplifier. Capacitor Cm1 provides a branch
from output to the second stage, a short feedback way,
that assists only in high frequency responses.
Pass device, as the third gain stage, is the main
device of the system, witch is responsible for the low
drop-out voltage between it’s source and drain pins.
As stages of stability, the first one is the DFC,
responsible for the stability in low current load. For
high load current, the sense current stage, additional to
DFC produce the desired stability.
The Damping-factor-control system needed to be
implemented in this case to improve a better accuracy in
the stability, changing the value of the damping factor
( ζ ). If the damping factor is too small, frequency peak
occurs and pole-zero cancellation by separated zeros is
not effective [9]-[11]. If the damping factor is too large,
the complex poles become separated real poles and the
loop-gain bandwidth will be degraded. A standard
Fig.1. Classical LDO topology.
11
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
second-order equation (1) is an example to understand
it's importance :
2ζ s2
F ( s )=1+s +
pc p² c
Acknowledgements
I would like to thank for the financial support of
CNPq and a technical one of LSItec and André Couto.
(1)
References
Damping-factor ( ζ ) is given by :
ζ=
1
2
√
[1] Zhan, C; KI, W. H. Output-Capacitor-Free Low-Dropout
Regulators: Analysis and Design. Lambert Academic
Publishing, 2012. 123p.
[2] Rincón-Mora, G. A. Current Efficient, Low Voltage, Low
Dropout Regulators. November 1996. 177p. Degree of Doctor
of Philosophy in Electrical Engineering - Georgia Institute of
Technology.
[3] Pelicia, M. M. Projeto e Implementação de um Regulador
de Tensão Low Dropout Utilizando Tecnologia CMOS. May
2002. 114p. Degree of Master of Electrical Engineering University of Campinas.
[4] Allen, Philip E; Holberg, Douglas R. CMOS Analog
Circuit Design. Second edition. Oxford University Press,
2012. 784p.
[5] Razavi, B. Design of Analog CMOS Integrated Circuits.
Tata McGraw-Hill, 2012. 684p.
[6] Gray, Paul R; Hurst,Paul J; Lewis, Stephen H; Meyer,
Robert G. Analysis and Design of Analog Integrated Circuits.
Fourth edition. John Wiley & Sons, INC, 2001. 875p.
[7] Milliken, R. J. A Capacitor-less Low Dropout Voltage
Regulator with Fast Transient Response. December 2005. 96p.
Degree of Master of Electrical Engineering - Texas A&M
University.
[8] Texas Instruments, Technical Review of Low Dropout
Voltage Regulator Operation and Performance.
(Aug. 1999) [Online]. Available: www.ti.com.
[9] Leung, K. N; Mok, P. K. T. Analysis of Multistage
Amplifier-Frequency Compensation. IEEE Transactions on
Circuits and Systems-I: Fundamental Theory and
Applications, Vol. 48, No. 9, p.1041-1056, September 2001.
[11] Leung, K. N; Mok, P. K. T. A Capacitor-Free CMOS
Low-Dropout Regulator with Damping-Factor-Control
Frequency Compensation. IEEE Journal of Solid-State
Circuits, Vol. 38, No. 10, p. 1691-1702, October 2003.
[11] Leung, K. N; Mok, P. K. T; Ki, W. H; Sin, J. K. O.
Three-Stage Large Capacitive Load Amplifier with
Damping-Factor-Control Frequency Compensation. IEEE
Transactions on Solid-State Circuits, Vol. 35, No.2,
p.221-230, February 2000.
[12] Milliken, R. J; Silva-Martínez, J; Sánchez-Sinencio, E.
Full On-Chip CMOS Low-Dropout Voltage Regulator. IEEE
Transactions on Circuits and Systems-I: Regular Papers, Vol.
54, No. 9, p. 1879-1890, September 2007.
[13] Rincón-Mora, G; Allen, P. E. A Low-Voltage, Low
Quiescent Current, Low Drop-Out Regulator. IEEE Journal of
Solid-State Circuits, Vol. 33, No. 1, p. 36-44, January 1998.
[14]Al-Shyoukh, M; Lee, H; Perez, R. A Transient-Enhanced
Low-Quiescent Current Low-Dropout Regulator with Buffer
Impedance Attenuation. IEEE Journal of Solid-State Circuits,
Vol. 42, No. 8, p. 1732-1742, August 2007.
[15] Zhan, C; Ki, W. H. Output-Capacitor-Free Low-Dropout
Regulators: Analysis and Design. Lambert Academic
Publishing, 2012. 123p.
( C g C OUT ) g mDFC
⋅
( gm2 g mp ) C f
(2)
Where Cg is the gate capacitance of the pass device,
COUT is the output capacitance, C f is the feedback branch
capacitance, gm2 is the transconductance of the second
gain stage, gmp is the transconductance of the pass
device and gmDFC is the transconductance of the
damping-factor-control stage.
C. Results
All the tests were made with sweep in current load,
capacitance load, voltage supply and process. Table I,
summarizes the sweep values of all those parameters.
Table I. Parameter's values for the tests.
90nm CMOS technology
Parameter
Min
Typ
Max
Load Current
1 μA
10 mA
Load Capacitance
10 pF
10 nF
Temperature
-40 ºC
40 ºC
105 ºC
Input Voltage
1.6 V
1.8 V
2.0 V
Bias Current
425 nA
500 nA
575nA
Table II shows the results for different analysis. The
main concern of the project is a small variation in the
output voltage, not only in dc but in transient responses
too, since the topology doesn't have an output capacitor.
Table II. Results.
Test
Description
DC
Quiescent
Current
DC Gain
Gain Margin
Phase Margin
PSRR@60Hz
PSRR@20kHz
Transient Peak
Line
Regulation
Transient Peak
Load
Regulation
Value
Min
Max
1.196 V
1.201V
21 μA
25 μA
120 dB
-67 dB
77 º
-54 dB
-48 dB
145 dB
-15 dB
87 º
-51 dB
-38 dB
4.3 mV
(0.36%)
14 mV
(1.16%)
11 mV
(0.91%)
30mV
(2.5%)
April 9 - 10, 2015, São Bernardo do Campo
Note
Monte Carlo
analyses
Monte Carlo
analyses
Corner analyses
Corner analyses
Corner analyses
Corner analyses
Corner analyses
Step 1.6V to
2.0V supply
voltage
Step 1mA to
10mA load
current
3. Conclusions
A CMOS LDO, without output capacitance was
presented in 90nm TSMC technology. The system is
completely adaptive, where each stage is responsible for
benefit the response in one or more tests. The total area
of CL-LDO is 300.2 μm x 271.9 μm.
12
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
ELECTROSPUN NANOFIBERS WITH INCORPORATED PARTICLES AS
MEMBRANE FOR SENSORS
Demetrius Saraiva Gomesa,c and Ana Neilde Rodrigues da Silvaa, b
a
LSI/PSI/USP – Universidade de São Paulo, São Paulo, 05508-010, Brazil
FATEC/SP – Faculdade de Tecnologia de São Paulo, São Paulo, 01124-060, Brazil
c
UNASP/SP – Centro Universitário Adventista de São Paulo, 05828-001, Brazil
e-mail: [email protected]; [email protected]
formation of composites with various physical and
chemical properties, among them the conductivity [4].
In this study, we used two polymer matrices:
Polyacrylonitrile (PAN) and Fluoride Polyvinylidene
(PVDF) [5,6]. Both polymers were dissolved in N, N
dimethylformamide (DMF) to prepare solutions of
polymer. Phthalocyanines present applications in many
devices [7] and can be added to PAN or PVDF
dispersions in order to electrospun fibers. The
incorporation of particles such as carbon black, increases
the mechanical performance of polymers [8] and also its
electrical conductivity [9]. In previous work was
demonstrated the feasibility of starch particles
incorporation into nano and microfibers [10].
In this paper, we present some results of the
incorporation of copper phthalocyanine, carbon black
and starch in electrospun nano and microfibers aiming to
apply them in membranes that can be used in sensors.
1. Abstract
These work presents the preliminary results of the
prospective study of nanocomposite production from the
mixture of different particles: starch, carbon black and
copper phthalocyanine to a dispersions of polivinilidene
fluoride or polyacrylonitrile dissolved in N, N
dimethylformamide, (PVDF/DMF) or (PAN/DMF)
respectivelly. These results are part of a more
comprehensive study that intends to establish a model of
incorporation of different particles into different
polymers. So, it is possible generating conductive
nanofibers from the dispersion of PAN/carbon black
which can be applied in membranes and nanosensors
devices. Also, as copper phthalocyanine has a
sensitivity to ammonia, it was possible electrospun
nanofibers on the surface of a Piezoelectric Quartz
Crystal (PQC), a micro device constructed for detection
of ammonia.
3. Experimental
2. Introduction
Polyvinylidene fluoride (PVDF, MW=534,000),
Polyacrylonitrile (PAN, MW=150,000), anhydrous
N,N-dimethylformamide (DMF, 99.8 %) and copper
phthalocyanine (CuPc) was purchased from SigmaAldrich Inc. Carbon black powder (Vulcan XC-72R® average size 30 nm) was purchased from Cabot
Corporation Inc.), and Cassava (Manihot esculenta
Crantz, 5μm diameter) was homemade produced. All
mixtures were stirred at 900 rpm and 50°C during 24
hours. Fiber was characterized by optical microscopy
(Leica Mycrosystem GMB), and by scanning electron
microscopy (SEM, Jeol JSM-6360).
Among various types of materials, 1D nano-scaled
materials, such as nanofibers, have been widely used in
different areas such as science, engineering and
technology. Nanofibers can have a diameter between
tens to hundreds of nanometers, which give them an
enormous surface area per volume, high porosity, high
gas permeability and small pore size. These properties
make the nanofibers one of the candidates for many
important applications such as membrane in adsorption
or as a filter medium, among others [1,2]. Polymeric
nanofibers can be obtained by various methods among
them electrospinning. Also, it can be modified in many
ways, from electroless deposited metal to addition of
different kind of particles to the polymer solution in
order to obtain membrane with filtration interesting
features [3].
Electrospinning is a simple and economical process
for obtaining fibers at the nanometer scale. This method
allows obtaining fibers from different kinds of polymer
solutions, since it has proper viscosity. In this process
when an external electric field with a high voltage is
applied to the polymer solution the electrical charges
can overcome the surface tension of the viscous
polymer solution after a polymer fiber is ejected toward
the collector and the solvent is evaporated during the
process. The nanofibers produced can also give the
advantages of the precursor polymer solution like the
4. Results and Discussion
Fibers with Carbon Black: It was possible to see a
relationship between fiber diameter and carbon black
concentration.
400
350
b)
Absolute Viscosity(cP)
b
300
c)
250
200
150
100
50
1:0,0
1:0,2
1:0,4
1:0,6
1:0,8
1:1,0
PAN: Carbon Black
Fig.1: Morphology of PAN fibers / Vulcan, b) Absolute
viscosity and c) diameter variation in function of PAN carbon
black mass ratio.
The fiber morphology, figure 1 a) and the diameter
variation in function of carbon black concentration,
13
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
figure 1 b), confirms the particle incorporation into the
fibers. The ratio between the viscosities of the solutions
with and without the addition of carbon black is about
3.3, close to the values of relative viscosity (figure 1 c).
Fibers with Starch: To validate the use of
PAN/starch fiber as an active material for detection,
fibers were electrospun over quartz crystals for QCM
analysis. Fiber morphology and diameter were
dependent on the amount of starch in the solution, as
observed by SEM analysis (figure 2 a) and b), also the
curves from diameter variation shows two different
regimes which correlate with relative viscosity data
(figure 3 a). Also was observed a crack during the SEM
analysis probably due to electron description suggesting
that the starch acts as an absorbent inside the fiber. In
10% of relative humidity a reversible change of the
signal of 10 Hz was observed, figure 4 b). It means that
water molecules could permeate the PAN chains
(probably due to hydrogen bond formation).
April 9 - 10, 2015, São Bernardo do Campo
The fibers from PAN/cups are more sensible than the
fibers from PVDF/CuPc as can be inferred from the
results resumed in Table I, but the sensibility independ
of the polymer used since in both cases the ammonia
was adsorbed over the fiber's surface. Consequently, the
ammonia detection using polymeric fibers added with
copper phthalocyanine is possible.
4. Conclusions
The diameter of the nanofibers electrospun from all
composite solutions studied increased in function of
particle concentration. In all the studied solutions the
viscosity increases in function of particle incorporation.
The analysis of the morphology by SEM also confirms
the particle incorporation into the fiber. Fibers with
Starch incorporated adsorbed water and tests with the
vapor of ammonia demonstrated that the fibers
produced from both solution, PAN/CuPc and
PVDF/CuPc, are promising to be used as sensitive layer
and also for detection of gas contaminants.
Acknowledgments
The authors would like to thank Mr. Adir J. Moreira
for the SEM measurements, INCT Namitec and
UNASP-SP for the financial support.
Fig. 2: a) fibers with starch particles, b) diameters versus
PAN/starch ratio obtained from SEM analysis.
References
D. R. Paul, L. M. Robeson, “Polymer nanotechnology:
Nanocomposites”, Polymer 49 (2008) 3187–3204
[2] N. Bhardwaj, S.C. Kundu, “Electrospinning: A fascinating fiber
fabrication technique” Biotechnology Advances 28 (2010) 325–
347.
[3] Shaik A. A. N. Nasreen, S. Sundarrajan, Syed A. S. Nizar, R.
Balamurugan and S. Ramakrishna, “Advancement in
Electrospun Nanofibrous Membranes Modification and Their
Application in Water Treatment”, Membranes 2013, 3, 266-284.
[4] Xie, Jingwei, Xia, Younan, “Electrospinning: An Enabling
Technique for Nanostructured Materials”, Material Matters
2008, 3.1, 19.
[5] C. A. R. Brito Júnior, R. R. Fleming, L. C. Pardini, N. P. Alves.
“Poliacrilonitrila: Processos de Fiação Empregados na
Indústria.” Polímeros, vol. 23, n. 6, p. 764-770, 2013.
[6] S. M Damaraju, S. Wu, M. Jaffe, Treena Livingston Arinzeh,
Structural changes in PVDF fibers due to electrospinning and its
effect on biological function. Biomed. Mater. 8 (2013) 045007
(11pp).
[7] C. A. R. Brito Júnior, R. R. Fleming, L. C. Pardini, N. P. Alves.
“Poliacrilonitrila: Processos de Fiação Empregados na
Indústria.” Polímeros, vol. 23, n. 6, p. 764-770, 2013.
[8] Agnes F. Martins, Bruno de A. Napolitano, Leila L.Y. Visconte,
Regina C.R. Nunes, Ana M. Furtado. “Propriedades Mecânicas e
Dinâmico-mecânicas de Composições de Policloropreno com
Negro de Fumo”. Polímeros: Ciência e Tecnologia, vol. 12, nº 3,
p. 147-152, 2002.
[9] S.M. Senthil Kumar, Jaime Soler Herrero, Silvia Irusta, Keith
Scott. “The effect of pretreatment of Vulcan XC-72R carbon on
morphology and electrochemical oxygen reduction kinetics of
supported Pd nano-particle in acidic electrolyte.” Journal of
Electroanalytical Chemistry 647 (2010) 211–221.
[10] A. N. R. da Silva, M. L. P. da Silva, E. R. Fachini, Journal of
Physics: Conference Series 421(1) 012013 (2013)
doi:10.1088/1742-6596/421/1/012013
[1]
Fig.3: a) Relative viscosity and b) QCM measurements
Fibers with phtalocyanine: Optical image of fibers
electrospun from 1:1.0 PAN/CuPc dispersion confirms
the phtalocyanine incorporation. Graphs in figure 4b)
and 4c) show that the fiber diameters and the dispersion
viscosity
increases
with
the
phtalocyanine
concentration.
Fig. 4: a) optical image of the fibers with copper
phthalocyanine incorporated, b) Diameter and c) absolute
viscosity vs PAN/CuPc ratio.
Table I: Mass variation in function of PQCs frequency
PAN/CuPc
∆F (Hz)
∆m (ppb)
-20
124.2
-14
86.9
-9
55.9
-6
37.2
PVDF/CuPc
∆ (Hz)
∆m (ppb)
-31
192.4
-17
105.5
-11
68.3
-12
74.5
14
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
Electrical characterization of MOS capacitors with thin silicon oxynitrides
aiming at MOS tunnel diodes
V. Christiano and S.G. dos Santos Filho
University of São Paulo – LSI/PSI/EPUSP
e-mail: [email protected]
deposited at a work pressure of 4x10-6 torr by
evaporation. The definition of the capacitors area was
done by lithography, in which, four capacitors were
obtained at a fishbone geometry, which consists of a
vertical central line cut by horizontal lines with the
same width (L) separated by a distance (D). Also, at the
end of the vertical central line, there is a pad for electric
contact. Subsequently, the silicon oxynitride grown on
the wafer backside was removed and another deposition
of aluminum was done at the same condition. Finally,
the processed sample was annealed at 350°C in
ultrapure argon.
The current-voltage (I-V) curves of the MOS
capacitors
were
extracted
by
an
HP4140
picoamperimeter, in order to obtain I-V curves, and HP
4280 C meter, employed at 1MHz in order to obtain
Capacitance-Voltage (C-V) characteristics.
1. Abstract
Thin silicon oxynitrides (2.42 nm) grown by rapid
thermal oxidation (RTO) in ultrapure nitrogen and
oxygen (5N2:1O2 ratio), under the temperature of 850
°C, were used as gate dielectric in MOS capacitors
aiming at MOS tunnel diodes. The electrical
characterization pointed out to current-voltage
characteristics consistent with MOS tunnel diodes for
large areas along wafers, 3 inches in diameter.
2. Introduction
Scaling down is the main requirement for the
evolution of Giga scale integration (GSI) technology.
On the other hand, metal-oxide-semiconductor (MOS)
structures have been used for alternative devices, such
as MOS tunnel diodes. A challenge is to grow uniform
thin films, keeping a high quality interface and a small
defect density [1-2]. Although, some authors [3-5]
report the rapid thermal oxidation (RTO) as an
interesting technique to grow uniform thin films,
especially when nitrogen is added during the growing.
The
oxynitrides
present
propitious
electrical
characteristics to be applied as gate dielectric in MOS
tunnel diodes, particularly due to the leakage current
prevention related to an enriched nitrogen interface [3,
6].
In this work, MOS capacitors with thin silicon
oxynitrides grown by RTO were electrically
characterized with the aid of Capacitance-Voltage and
Current-Voltage characteristics.
4. Results and Discussion
The first stage of the electrical characterization was
done before annealing the sample. Fig.1. shows the
measured C-V curves with an initial light, from the
inversion to the accumulation region, using a 100 
resistor associated in series with the MOS capacitor.
Considering a p-MOS capacitor, the curves present an
unexpected behavior since the inversion capacitance is
higher than the accumulation capacitance, which also
reduces to negative values.
3. Experimental
C [F]
The manufacturing process to obtain the MOS
capacitors starts with Si-p wafers (100), 3 inches in
diameter, chemically cleaned by a modified RCA
cleaning [7], followed by a dip in diluted
hydrofluoridric acid (d-HF) at room temperature. Then,
the thin silicon oxynitrides (about 2.42 nm) were grown
by rapid thermal oxidation (RTO), carried out in an
adapted conventional thermal oxidation furnace [8].
Each wafer was oxidized, at the temperature of 850°C
for 80 s in a mixed ambient of nitrogen and oxygen at
5N2:1O2 ratio and also passivated in pure nitrogen at 2
L/min for 80 s. Following, 200 nm of aluminum was
1,8x10
-10
1,2x10
-10
6,0x10
-11
0,0
-6,0x10
L100-D100
L100-D150
L50-D100
L50-D50
-11
-2
-1
0
1
2
Vg [V]
Fig.1.CV for the sample obtained at 850 °C, during 80 s for
5N2:1O2.
15
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
diameter were used to grow 2.42 nm thin silicon
oxynitrides by RTO, aiming to the fabrication of MOS
tunnel diodes. The electrical characterization pointed
out to current-voltage characteristics consistent with
MOS tunnel diodes.
Fig.2 shows the obtained I-V curves. They were also
extracted having a 100  resistor to limit the current
and prevent the device breakdown. Considering the
accumulation region, the capacitors led to improve their
current for gate voltages higher than 1V, even keeping
the same current magnitude, about 10-6 A.
Acknowledgments
The Authors would like to thank CNPq for the
financial support.
-3
6,0x10
-3
10
-3
3,0x10
I [A]
-4
10
0,0
-2
I [A]
-5
10
-1
0
Vg [V]
1
2
References
-6
10
[1] M. Depas, R.L. Van Meirhaeghe, W.H. Laflère and F.
Cardon, “Tunnel oxides grown by rapid thermal xidation,”
Microelectronic Engineering, vol. 22, pp. 61-64, 1993.
[2] K.-M. Chang, W.-C. Yang, C.-F. Chen and B.-F. Hang,
“The changing effect of N2/O2 fas flow rate ratios on ultrathin
nitrogen-enriched
oxynitride
gate
dielectrics”,
J.
Electrochemical Soc., vol. 151, pp. F118-F122, 2004.
[3] Z.H. Lu, S.P. Tay, R. Cao and P. Pianetta, “The effect of
rapid thermal N2O nitridation on the oxide/Si (100) interface
structure”, Appl. Phys. Lett, vol. 67, pp.2836-2838, 1995.
[4] A. Beyer, G. Ebest and R. Reich, “Metal-insulatorsemiconductor solar cells with silicon oxynitride tunnel
isulator by using rapid thermal processing”, Appl. Phys. Lett.
68, pp. 508-510, 1996.
[5] Z.Q. Yao, H.B. Harrison, S. Dimitrijev and Y.T. Yeow,
“The electrical properties of sub-5-nm oxynitride dielectrics
prepared in a nitric oxide ambient using rapid thermal
processing”, IEEE Elect., Dev. Lett., vol. 15, No. 12, pp. 516518, 1994.
[6] K.-M. Chang, W.-C. Yang and C.-F. Chen, “1.0 nm
oxynitride dielectrics prepared by RTP in mixtures of N2 and
O2 ambient”, J. Electrochemical and Solid.-State Lett., vol. 6,
pp. G119-G121, 2004.
[7] L.Z. Toquetti and S. G. dos Santos Filho “Estudo
experimental da obtenção de oxinitretos de silício ultrafinos
para porta MOS” Ph.D. Thesis presented at Escola Politécnica
of USP, 2005.
[8] V. Christiano and S. G. dos Santos Filho, “RTP silicon
oxynitrides to fabricate MOS tunnel diodes”, Microelectronics
Technology and Devices (SBMicro), 2013 Symposium on, pp.
1,- 4, 2-6 Sept. 2013.
L100-D100
L100-D150
L50-D100
L50-D50
-7
10
-8
10
-9
10
-2
-1
0
1
2
Vg [V]
Fig.2. I-V for the sample obtained at 850 °C, during 80 s for
5N2:1O2. In let is presented the same curve kepping I axis
linnear.
After annealing the sample, the I-V characteristics,
also obtained using a series resistor of 100  are
presented in Fig.3. The profile is similar to those
exhibited in Fig.2, excluding a soft dispersion observed
in the inversion region between -1 and 0 V, although the
current is somewhat lower in the accumulation region
for all the capacitors.
-3
6,0x10
-3
10
-3
I [A]
3,0x10
-4
10
0,0
-2
I [A]
-5
10
-1
0
Vg [V]
1
2
-6
10
L100-D100
L100-D150
L50-D100
L50-D50
-7
10
-8
10
-9
10
-2
-1
0
1
2
Vg [V]
Fig.3. I-V curves for the same sample exhibited in Fig.2 after
sinterization under the temperature of 350°C.
Considering Fig.1 and Fig.2, it is noteworthy that the
current profile is consistent with a MOS tunnel diode
before and after annealing.
5. Conclusion
P-silicon wafer with large area of 3 inches in
16
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
Dielectrophoretic manipulation of individual nickel nanowires for electrical
transport measurements
M. V. Puydinger dos Santosa,b, L. P. B. Limab, R. A. Mayera, F. Bérona, K. R. Pirotaa, S.
Moshkalevb, and J. A. Dinizb
a
b
Institute of Physics “Gleb Wataghin”, University of Campinas, 13083-859 Campinas, SP, Brazil.
School of Electrical and Computer Engineering and Center for Semiconductor Components, University of Campinas,
13083-970 Campinas, SP, Brazil.
e-mail: [email protected]
1. Introduction
Nanowires (NW) are appropriate elements for
electronic devices that require ultra-low power
consumption, given the low current levels and high
sensitivity they usually exhibit [1-5]. In addition, since
NW present low current levels and high sensitivity, they
can be used as sensors devices for several applications.
One of the major challenges when dealing with
transport measurements in NW is to trap them between
electrodes which allows electrical characterization and
therefore fabrication of nanowire-based devices.
Electrically neutral NW can be deposited by
dielectrophoresis (DEP) method, which requires the
application of an alternate electric field between
electrodes. Properly isolated Ni nanowires (NiNW)
were dispersed in a dimethylformalmide (DMF)
solution and dielectrophoretically manipulated to make
electrical contact between electrodes. Electrodes
geometry and DEP electrical parameters were varied to
evaluate the NiNW deposition efficiency by this
technique. In addition, electrical characterizations of the
NW and of the contact resistance between the NW and
electrode were performed by current versus voltage
curves. Significant reduction of contact resistance was
achieved by ion-beam assisted deposition of Pt cap
layers on the NW extremities.
Fig.1. Schematics of experimental procedures: (a) dielectric
layer formation on top of n+-Si wafer by thermal oxidation;
(b) electrodes definition by photolithography and lift-off; (c)
NiNW deposition on electrodes by DEP experiment and (d)
contact resistance reduction after the deposition of Pt layer by
GIS-FIB.
The NiNW (length = 4 μm, diameter = 35 nm) were
fabricated via pulsed electrodeposition into anodized
alumina membrane [6] They were released from the
membrane by chemical etching with a 1 M NaOH
solution at 27 ºC under agitation. NiNW were then
cleaned with deionized water (18 MΩ.cm) and
dispersed in DMF, in order to avoid NW clusters
formation. The NiNW deposition was performed by
DEP, conducted with a HP 8116A Pulse/Function
Generator configured with 3 VPP and null offset (Fig.
1c). The sinusoidal signal was generated for a frequency
range between 50 kHz to 1 MHz. Before DEP process,
the solution (concentration of 108 NiNW/mL) was
sonicated for 120 seconds, in order to disperse
uniformly the NiNW into the DMF. For each pair of
electrodes, the DEP field was applied during 60 seconds
on a solution volume of 1 µL. The DMF excess was
rinsed with deionized water (18 MΩ.cm) before being
dried with N2. Finally, a 10 nm-thick cap layer of Pt was
deposited on the NiNW extremities to reduce the
contact resistance with the electrodes (Fig. 1d), using a
Ga+ focused ion beam (GaFIB)/scanning electron
microscope (SEM) with a gas injection system (GIS)
tool [8-11]. The ion source used in this work was a FEI
Nova 200 Nanolab GaFIB/SEM dual beam system with
energy of 30 keV, current of 10 pA and tilt angle of 0º.
Under these conditions, the milling process of NiNW
and electrodes was significantly reduced.
2. Experimental Details
Pt electrodes were defined on a SiO2/Si structure.
First, a 300 nm-thick SiO2 layer was grown on an n+type Si (100) wafer (electrical resistivity of 1-10 Ω.cm)
by wet thermal oxidation in a conventional furnace, in
order to act as a dielectric layer (Fig. 1a). Then,
photolithography was performed to define the electrodes
region. 80 nm-thick Pt layer was deposited by a physical
vapor deposition (PVD) system and lift-off process was
carried out to define electrodes (Fig. 1b). Three different
electrodes geometries were fabricated to evaluate the
effect of electrode shape on DEP force. The total
electric field distribution over the gap area was
simulated using COMSOL Multiphysics simulation
tool.
17
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
The electrodes resistance is 120 Ω, thus NiNW
resistance is around 6 kΩ (ρNiNW=1.3×10-5 Ω.cm), which
is consistent with the resistivity of NiNW of similar
dimensions [11].
3. Results and Discussion
The maximum deposition efficiencies for geometry
1 were 85% and 60% for 100 and 600 kHz, respectively,
for averages of 3.4 and 8.7 deposited NiNW (Fig. 2). On
the other hand, the efficiency was maximized at 600
kHz for geometries 2 and 3, with value of 50% and
averages of 2.7 and 2.0 NiNW, respectively (Fig. 3).
This behavior can be attributed to electric field
inhomogeneities and lower trapping area over the gap
present between electrodes geometries 2 and 3. For
geometry 1, since it presents a larger electrode area, it
captures more NiNW during DEP process and increases
the probability of success, even with electric field
intensity slightly lower than geometries 2 and 3.
Fig.4. I x V curves for NiNW before (non-linear, left and down
axes) and after (linear, right and up axes) 10 nm-thick Pt
layer deposited by GIS tool of GaFIB.
4. Conclusions
Fig.2. Charts of (a) deposition efficiency and (b) average
number of NiNW, obtained for DEP experiment as a function
of electric field frequency, for three electrodes geometries.
This work presented DEP manipulation of NiNW
over Pt electrodes defined by photolithography and liftoff. The studied NiNW are a promising feature to be
used as sensors devices, since they can be manipulated
with high efficiency to make contact with electrodes and
their electrical, thermal and/or optical output signals (in
response to the environment stimulus) can be further
processed. After the investigation of NiNW deposition
mechanisms, GIS–GaFIB tool was used for Pt
deposition of 10 nm-thick cap layers on the nanowires
extremities to successfully reduce contact resistance
between NiNW and electrodes. In addition, NiNW
present ferromagnetic properties, which allows their low
level currents to be controlled through magnetic fields.
Thus, they can be studied as a promising alternative to
the traditional Si-based MOSFET devices.
Fig.3. SEM analysis of NiNW deposited on Pt electrodes for
(a) geometry 1, (b) geometry 2 and (c) geometry 3, after DEP
experiment (VPP = 3 V, f = 100 kHz (upper row) and 600 kHz
(lower row).
References
[1] J. Wu et al, Appl. Phys. Lett. 105, 183506 (2014).
[2] M. Li et al, J. Phys. D: Appl. Phys. 47, 063001 (2014).
[3] K. W. Seo et al, J. Vac. Sci. Technol. A 32, 061201-1
(2014)
[4] M. N. Ou et al, Appl. Phys. Lett. 92, 063101 (2008).
[5] J. J. Boote et al, Nanotechnology 16, 1500 (2005).
[6] D. C. Leitao et al, J. Non-Cryst. Solids 354, 5241 (2008).
[7] L.P.B. Lima et al, ECS Trans. 49, 367 (2012).
[8] M. V. Puydinger dos Santos et al, J. Vac. Sci. Technol. B
31, 06FA01 (2013).
[9] K. A. Unocic et al, J. of Microsc. 240, 227 (2010).
[10] S. E. Wu et al, Nanotechnology 16, 2507 (2005).
[11] S. Mani et al, IEEE Trans. Nanotechnol. 5, 138 (2006).
[12] U. Yogeswaran et al, Sensors 8, 290 (2008).
When the NiNW makes contact with the electrodes,
a large contact resistance is usually present, leading to a
Schottky-like contact (non-linear). After depositing a 10
nm-thick cap layer of Pt on the NiNW extremities to
reduce the contact resistance, the resulting behavior is
ohmic (linear), as shown in Figure 4 [7]. In the current
study, we obtained current (I) versus voltage (V) curves
by applying current – without exceeding 6 µA to avoid
NiNW damage due to heat dissipation – while
measuring voltage with a four-wire setup. We observed
a transformation from a non-linear behavior for asdeposited system to a linear one, after Pt layer
deposition, as well as a resistance reduction (Fig. 4).
18
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
Visibility of Weak THz Sources on a Bright Background
R.V. Souzaa,b, P. Kaufmanna,b, D. P. Cabezasa and L. T. Manerab,c
a
Escola de Engenharia, CRAAM, Universidade Presbiteriana Mackenzie, São Paulo, SP, Brazil
Centro de Componentes Semicondutores, Universidade Estadual de Campinas, Campinas, SP, Brazil
c
Faculdade de Engenharia Elétrica e de Computação, Universidade Estadual de Campinas, Campinas, SP, Brazil
e-mail: [email protected]
b
component in solar flares, identified at sub-THz and at
30 THz frequencies [8][9] raised challenging physical
questions to understand the origin of these mysterious
emissions.
Significant
improvement
in
the
characterization of the flaring phenomena at 30 THz (10
µm band, also called mid-IR) will be obtained with the
identification weaker and smaller emission sources on
the bright background solar photosphere.
1. Abstract
One of the image processing challenges is the
recovery of weak spatial structures with small angular
sizes lying on intense background. The problem is
common to spatial sensing using distinct imagers at
various ranges of the electromagnetic spectrum. This
problem becomes particularly relevant for image
analysis obtained in the THz range of frequencies to
resolve small emitting sources on bright backgrounds
and further blurred by limited angular resolution set by
the apertures. One application of great interest is the
identification of spatial structures in THz solar flares
recently discovered. The transient events occur over the
bright solar photosphere. We have developed techniques
to enhance the visibility of finer spatial structures, by
successively applying linear and non-linear filters,
diverging filters convolution over the image matrix,
defocusing areas of lesser interest, and applying a multiresolution algorithm to the analysis, dividing the image
in multiple layers processed using Gaussian wavelet
filter. This technique has been successfully applied to a
THz solar flare observed with high frames cadence
revealing smaller bright sources.
3. Image processing by filter composition
In order to process the solar flare 30 THz images
with intense, bright, and partially homogeneous
background, we applied a composition of filters on
distinct and successive steps, as follows.
Referring to the block diagram shown in Fig. 1, the
brightness of the originally acquired image (A) is
reduced by applying a linear filter (F1). The lateral
borders brightness is further reduced with the
convolution of divergent filters on the image matrix of
data points (F2). After this step, we begin the
procedures to enhance the global and local contrasts
using available linear or non-linear filters (F3). The
noise is further reduced by defocusing the image (F4) in
order to enhance the region of interest in the image (B).
In the second step the contrast is again and further
extended [3] by composing the linear filter to reduce the
brightness and the non-linear filter to enhance again the
region of interest (F5) (see C1 in Fig. 1, as an example).
At this phase the bright points may begin to become
evident. The multi-resolution analysis algorithm [5] is
applied, to divide the image in 6 layers which are
analysed [7] by using Gaussian wavelet filters (F6, F7
and F8) separately.
In layers 1 and 2 are the low-pass filters (F6) that
smooth out the image and reduces the grey levels. The
result is a blurred image with noise increased due to the
enhancement of the brighter structures. See image D in
Fig. 1. On these two layers it is necessary to apply a
typical filter (F9) for threshold noise level in the
wavelet domain [10][11] (image E). The intermediary
3rd and 4th layers actuate on the relative importance of
the image grey scale (F7). In order to better define the
borderlines, curve lines, or the sunspots, the divergent
and high-pass filters are applied in each layer (F9). The
filter (F8) reinforce the importance of the darker
2. Introduction
The understanding of various phenomena in science,
in physics and biology in particular, require the
knowledge of imaging details obtained at different
ranges of the electromagnetic spectrum. Techniques
have been developed for decades to improve the image
quality for technical and scientific analysis. For
example, the pioneer image characterization by texture
processing [1], the background subtraction largely
applied for recognizing moving structures in static
videos [2], the contrast enhancement for pattern
recognition [3]. Wavelet filters are helpful to enhance
feature shapes [4], while the multi-resolution algorithms
[5] and analysis [6] subtract noise and allowing images
to be decomposed into various levels of resolution,
enhancing details in each level [7]. However there are
no complete techniques available to identify weak
sources on extended, bright and partially homogeneous
background, as are quite typical in images obtained in
the THz-visible range of electromagnetic frequencies.
The discovery of a new THz spectral emission
19
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
structures (image G). Finally we apply the segmentation
technique [3] to the image. The region of interest is
enlarged, filter F5 is applied again on it to produce the
final image shown at the right upper panel. The
presence of at least two bright weak sources are
revealed and well defined.
April 9 - 10, 2015, São Bernardo do Campo
over a bright background.
CRAAM/30THz 14:24 UT
F
A
F1
Fig. 2. The October 27, 2014 30 THz solar burst brightening.
Left panel, with enhanced contrast exhibiting one single
blurred source. Right, after image processing procedures
shown here, exhibiting at least two bright sources. The
"photometric beam" (Airy disc) is shown at lower left for each
panel.
F2
F3
B
F4
F5
Acknowledgments
C1
These researches are partially funded by Brazil
agencies FAPESP, CNPq, INCT NAMITEC and US
AFOSR.
C
References
F10
[1] R. M. Haralick, K. Shanmugam, and I. Dinstein, “Textural
Features for image classification,” IEEE Transactions on
sistems, man, and cybernetics, vol. smc-3, no. 6, November
1973, pp. 610-621 .
[2] M. Piccardi, “Background subtraction techniques: a
review” IEEE International conference on systems, man and
cybernetics, 2004, pp. 3099-3104.
[3] B. Jahne, “Digital Image Processing, Springer-Verlag,
2002, pp. 427-439.
[4] E. J. Stollnitz, T. D. DeRose and D.H. Salesin. “Wavelets
for computer graphics: A primer, part 1”. IEEE Computer
Graphics an Applications, 15(3): May 1995, pp. 76-84.
[5] S.Mallat, “ A theory for multiresolution representation
signal decomposition: The Wavelet representation”. IEEE
Transactions on Pattern Analysis and Machine Intelligence,
New York, 1989a, V.11, n.7, p. 674-693.
[6] Daubechies, I. “the wavelet transform, time frequency
localization and signal analysis”. IEEE Transactions on
Information Theory. New York, 1990, v.36, pp. 961-1005.
[7] Coifmann, R. “Adapted Multiresolution analysis,
computation, signal processing and operator theory”.
In:Congress of Mathematicians, 1990, pp. 879-887.
[8] P. Kaufmann et al. “A new solar burst spectral component
emitting only in the terahertz range”, Astrophys.J., vol. 603,
pp. L121-L124, 200.
[9] P. Kaufmann et al. “A Bright Impulsive Solar Detected at
30 THz”., Astrophys.J., vol. 783, 2013, pp. 768-777.
[10] D. L. Donoho, I. M. Johnsine. “Ideal Spacial Adaptation
Via Wavelet Shrinkage” Biométrica, London, 1994,V. 81, n.3,
pp. 425-455.
[11] H. Storm, “ Noise Reduction of Speech Signals With
Wavelets”. Gothenburg: Departament f Mathematics,
Chalmers University of Techology and Gothenburg
University, 1998. pp. 21-79.
F9
D
F6
F7
E
F8
Fig.1. 30 THz images of solar flare of October 27, 2014, near
maximum emission. The original acquired image (A), top left.
The following left panels from the top show effects of step
filters applications. The image (B) exhibits the results of the
application of preliminary filters, while the image (C) is
processed with the non-linear filter (gamma function - C1).
The wavelet filter is applied next. The result is the improved
resolution flare image at the top, right, exhibiting at least two
well-defined bright structures.
The Fig. 2 show a preliminary comparison of the
initial observed image (left) with the processed image
(right) which shows at least two sources, smaller than
the diffraction limit angle (i.e. the “photometric beam”).
3. Concluding remarks
We have shown that image processing by filter
composition can be a powerful technique to improve the
analysis of 30 THz images of solar flares enhancements
20
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
Analysis of Vertical Field Dependent Mobility Model Applied to FinFET
Simulation
D. O. Silva, A. S. N. Pereira and Renato Giacomini
Centro Universitário da FEI, São Bernardo do Campo 09850, Brazil
e-mail: [email protected]
1. Abstract
This work aims to analyze the accurateness of simulated drain
current of Triple Gate SOI nFinFETs compared to previous
published experimental data for different channel lengths. The
study covers the application of analytical mobility models used in
simulations and evaluates the influence of characteristics related to
reduction in physical dimensions of the transistors. The Shirahata
mobility model combined with the maximum mobility (0) of
Klaassen model, besides the RSD were considered in simulations.
In general, the simulations results were quite accurate to
reproduce the experimental data. The analysis shows that it is
necessary to correct the carriers’ mobility behavior for Coulomb
and surface roughness scattering phenomena, and mainly their
dependence with channel lengths.
Fig.1. Simulated Triple Gate SOI FinFET.
Table 1 presents the characteristics of the simulated devices,
where L is the channel length, LEXT is the source and drain regions
length, WFIN is the fin width, HFIN is the fin height, NA is the p-type
doping concentration of channel region, ND is the n-type doping
concentration of source and drain regions, tox is the gate oxide
thickness, tbox is the buried oxide thickness and RSD is the source
and drain series resistance provided by [3]. The simulations were
performed with Shirahata’s mobility model to consider the
scattering by phonons (ph) and surface roughness (sr), combined
with the maximum mobility (0) extracted from simulation with
the Klaassen’s model to represent the scattering by Coulomb (c),
besides the RSD consideration as previously shown in [5]. A low
drain voltage bias (VDS=50mV) was used in simulations and gate
voltage (VGS) ranging from 0 to 1V. The IDSxVGS curves were
used to extract the effective mobility curves from
transconductance [2]. The IDSxVGS curves as well as the effective
mobility curves were used to analyze the differences between
experimental and simulated results.
2. Introduction
The FinFET (Fin-Field Effect Transistor) is a MOSFET
device with potential for future industrial application, because of
its good performance in nanometric dimensions [1]. The
continuous reduction of physical size in transistors of new
technologies brought particularities to the devices, such as the
existence of multiple gates and short channel effects, which cause
changes in the behavior of devices when compared to
conventional transistors. As a result the analytical models used to
describe the behavior of conventional devices usually cannot
describe with accuracy the phenomena of FinFETs. The carriers’
mobility is one of the most sensitive parameters to technology
changing, since it depends on the temperature, doping
concentration, crystallographic orientation and the applied electric
fields. Besides that, mobility is an important parameter to
determine accurately the current drive of MOS devices [2]. Based
on this context, it is worth to study the devices characteristics
applied to analytical mobility models, in order to investigate
which aspects are important to accurately reproduce the SOI
FinFETs behavior in device simulations.
This work does the analysis of the mechanisms and the
parameters in mobility models which generate differences
between the simulated drain current and some experimental data
already published [3].
Table I. Characteristics of simulated devices.
L (m)
0 (cm2/Vs)
LEXT (nm)
WFIN (m)
HFIN (m)
0,25
1020
1
1200
20
30
60
10
1300
NA (cm-3)
ND (cm-3)
tox (nm)
tbox (nm)
RSD (m)
1015
1020
2
145
170
4. Results and Discussion
Fig. 2 shows the normalized IDSxVGS curves for three different
channel lengths. It can be noticed that the device with L=1m is
the most accurate regarding all VGS range. Fig. 3 presents the
effective mobility curves versus VGS, where is also possible to
observe the good accuracy of simulation for L=1m. The
discussion of errors will be divided according to intensity of the
applied vertical electric field (En), which is proportional to VGS, as
follows.
3. Device Simulation
Fig. 1 shows the Triple Gate (TG) SOI FinFET simulated in
Atlas device simulator [4]. In [5] a comparative study of mobility
models used for FinFETs simulations was conducted, and it was
found that the combination of Klaassen and Shirahata mobility
models showed greater accuracy regarding the experimental
curves.
21
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
18
This can occur due to the volume inversion, which was not taken
into account in simulations, or sr that is predominant in
moderated and high fields. Volume inversion can increase the
mobility in thin devices due to the deviation of the inversion
charges from the interfaces in direction to silicon body [1].
However, this phenomenon can be significant only on devices
with WFIN≤10nm [1].
So, in moderate and high fields the errors are mainly
attributed to sr, which is L dependent [1]. It can be observed in
the longer device the sr influence must start at lower En to result
in increased degradation of the mobility, and also the IDS. In the
smaller device the sr influence must start at higher En to reduce
the degradation of mobility and current, and then get a better
response on the experimental curves for VGS≥0.5V. This can be
corrected by the parameters E2 and p2 in Shirahata model [4],
which is related to sr.
16
IDS /(W/L) (A)
14
10m
1m
0.25m
L=
L=
L=
12
10
8
6
4
Opened: Atlas Simulation
Closed: Experimental Ref. [3]
2
0
0.0
0.2
0.4
0.6
0.8
1.0
VGS (V)
Fig.2. Normalized drain current as a function of gate voltage.
400
L=
L=
L=
10m
1m
0.25m
300
250
C. Analysis without field influence
200
As general discrepancies, the lateral diffusion influence can be
cited, which were not considered in simulations and changes the
effective lengths. This can directly influence IDS values and also
the degradation from series resistance. The different
crystallographic orientations can also contribute to the errors
obtained in the simulations. In TG FinFETs, the lateral channels
usually reach lower mobility values compared the mobility in top
channel [1]. But, as the devices tends to be thinner with scaling
process, the influence of top channel could be neglected with
time.
2
Mobility (cm /V.s)
350
April 9 - 10, 2015, São Bernardo do Campo
150
100
50
0
0.0
Opened: Atlas Simulation
Closed: Experimental Ref. [3]
0.2
0.4
0.6
0.8
1.0
1.2
1.4
VGS (V)
Fig.3. Effective mobility as a function of gate voltage.
A. Analysis at low fields
5. Conclusions
The low field mobility in simulations was calculated from
Klaassen model [4]. It can be observed in Fig. 3 that for the longer
devices (L=1 and 10m) the experimental behavior before the
maximum mobility is reproduced quite well. However, for the
device of L=0.25m, in Figs. 2 and 3, it is noticed that the
simulated curve starts the conduction before the experimental one.
This can occur due to short channel effects (SCE), corner effects,
trapped charges in the interface (Ni), or the extracted 0 of
simulation with Klaassen’s model. Regarding SCE, the natural
length () should be 10% higher than channel length to suffer of
such effects [1], but in this case the calculated  is around 5% of
L. About corner effect, it can reduce the threshold voltage (VT) in
TG devices but only for devices with NA≥1017cm-3 [1]. Ni can also
be neglected because when considered Ni=5x1010cm-2 in
simulations, the variation of the results was less than 5%, where in
the worst case the percentage error for this region were of 24%
with Ni, and 20% without Ni in the device with L=1m.
Hence, the errors at low fields are mainly attributed to the
Klaassen model, which could not accurately describe the c on the
TG FinFET with reduced channel length.
This paper presented a study on the errors obtained in SOI
nFinFETs simulations in Atlas Simulator. The analysis shows that
to improve the response of the simulations it is necessary to
evaluate the dependence of scatterings by Coulomb and surface
roughness as a function of the channel length. For low field
mobility, the errors were attributed to the Klaassen model, which
could not accurately describe the c on the TG FinFET with
reduced channel length. For moderated and higher fields the
errors were attributed to c, which is correlated with the channel
length and must be corrected by E2 and p2 parameters of the
Shirahata model.
Acknowledgments
The authors would like to thank Centro Universitário da FEI,
FAPESP and CNPq.
References
[1] COLINGE, J.P. FinFETs and Other Multi-Gate Transistor. New York:
Springer, 2008.
[2] SZE, S.M. Physics of Semiconductor Devices. New York: John Wiley
& Sons, 1981.
[3] J. Song et al, “Compact Modeling of Experimental n-and p-Channel
FinFETs”, IEEE Trans. Electron Devices, 2010.
[4] ATLAS User’s Manual, SILVACO (2010).
[5] D.O. Silva et al, “Estudo dos Modelos de Mobilidade para a Simulação
de FinFETs Considerando a Degradação pela Resistência Parasitária”,
SPGABC, 2014.
B. Analysis at moderated and high fields
For the device with L=10m it can be seen in Figs. 2 and 3
that for VGS≥0.6V the experimental curve suffers greater
degradation that the simulated curve. And the opposite behavior is
observed for the smaller device, where the simulated curve suffers
higher degradation that the experimental curve for VGS≥0.5V.
22
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
Intrinsic Length and Temperature Influence on the Operation of PIN SOI
Photodiodes
C. Novoa , J. Baptistaa, R. Giacominia and D. Flandreb
a
Electrical Engineering Department , Centro Universitário da FEI, São Bernardo do Campo, Brazil
b
ICTEAM Institute, UC Louvain, Louvain-la-Neuve, Belgium
e-mail: [email protected]
comparing its value at higher temperature, the curves
show a difference in current concerning VBG, because
when the device is operating in accumulation mode
(VBG=-15V), the current is the largest one.
This can be explained by the fact that in inversion, there
is a higher recombination rate since the current is
specially composed by majority carriers, that are the
holes
1. Abstract
This paper addresses an analysis of the operation of
lateral SOI PIN photodiodes with different intrinsic
lengths in the 300 to 500 K range simultaneously
considering back-gate bias and temperature influences.
Experimental results showed that the mode of operation
changes the behaviour of the devices concerning dark
and photocurrents, while the temperature variation
produces different trades in photocurrent related to the
absorption length and the diffusion length variation.
Table I. Lateral SOI PIN technological parameters
LI
1 µm
2 µm
5 µm
10 µm
100 µm
2. Introduction
LTOTAL
249.16 µm
250 µm
249.4 µm
251.28 µm
204.08 µm
.
IDARK [A]
The detection of ultra-violet is used in many
application fields [1,2] with operating temperatures up
to 500K. The use of SOI PIN Photodiodes is required to
provide high quantum efficiency [3]. These devices
consist of highly doped P and N regions separated by an
intrinsic region (with light P-type residual doping) with
length LI. The characterized devices follow the 0.13μm
technology from ST described in [6]. They consist of
five devices with different intrinsic lengths (LI), but
keeping the same total area (ATOTAL) by changing the
numbers of fingers (m). Table I summarizes the main
lengths, including the total length (LTOTAL) and Figure 1
shows a schematic cross-section of the studied devices
that have a doping profile of P+P-N+.
m
105
75
39
22
2
1
0,1
0,01
1E-3
1E-4
1E-5
1E-6
1E-7
1E-8
1E-9
1E-10
1E-11
1E-12
1E-13
1E-14
1E-15
Black Symbols: T=300K
Red Symbols: T=400K
Blue Symbols: 500K
Closed: VBG=0V
Open: VBG=-15V
LI=5m
-1,5
-1,0
Center: VBG=+15V
-0,5
0,0
0,5
1,0
VD [V]
Fig.2. Dark current as a function of VD for different
VBG at T=300K, 400K and 500K
Fig.1. Cross-Section of PIN SOI Photodiode.
3. Measurements Results
In order to make a comparison between devices with
different intrinsic lengths, Figure 3 shows the total
diode current as a function of VD for a illumination
source of λ=400nm (ultra-violet wavelength). It is
shown that devices with smaller LI, have higher current
levels, because of the lower recombination rates and the
change in temperature, produces different built-in
potential, so the direct polarization starts at different VD.
Figure 2 shows the dark current of the device with
LI=5µm as a function of the anode voltage (VD) for
different back-gate voltages (VBG) and different
temperatures. One can note that the rise in temperature
produces larger levels of currents due to the elevated
thermal generation of carriers. It can be noticed as well,
that for room temperature (T=300K), the VBG variation
almost does not influence the dark current, but when
23
1,5
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
0,01
Closed Symbols: T=500K
Open Symbols: T=300K
1E-3
IPHOTOGENERATED/m [A]
LI=2m
1E-5
LI=5m
LI=10m
1E-6
VBG=-15V
1E-7
T=500K
1E-8
1E-9
-11
-1,00 -0,75 -0,50 -0,25
0,00
0,25
0,50
0,75
1,00
1
VD [V]
Fig.3. Total current as a function of VD for different
intrinsic lenghts and temperaturas in accumulation
mode.
4
5
6
7
8
9
10
IPHOTOGENERATED/m [A]
6
7
8
9
10
99,0 99,5 100,0
Acknowledgments
The authors acknowledge CNPq, CITAR and
CAPES for the financial support
References
[1] O. Bulteel and D. Flandre, ECS Trans., 19 (4), p. 175
(2009).
[2] M. Ingles and M. Steyaert, in Integrated CMOS Circuits
for Optical Communications, p.87, Springer-Verlag, Berlin
(2004)
[3] L. Shi and S. Nihtianov, IEEE Sensors Journal, 12 (7), p.
2453 (2012).
[4] A. Afzalian and D. Flandre, IEEE Trans. Electron Devices,
52 (6), p.1116 (2005).
[5] S. M. Sze, Physics of Semiconductor Devices, p.743, John
Wiley and Sons, New York (1981).
[6] Afzalian, Doctoral Thesis, UCL Louvain, Belgium (2006).
[7] D. Flandre et al, Solid-State Electronics, 45 (4), p.541
(2001).
[8] C. Novo et. al, Semicond. Sci. Technol., 29, p.1 (2014).
-11
3
5
In this work it was shown that the operation of PIN
photodiodes are strongly influenced by the intrinsic
length and temperature variation. Smaller devices with
many fingers presented higher current levels especially
in accumulation mode, but when comparing just one
finger, longer devices presented the best result, due to
the larger photosensitive area.
>T
2
4
4. Conclusions
VBG=-15V
1
3
LI [m]
VD=-1V
-10
2
Fig.5. Normalized photogenerated current as a
function of LI in inversion mode.
The influence of the numbers of fingers of the
devices can be seen in Figure 4 and Figure 5, where it is
shown the photogenerated current normalized by the
number of fingers as a function of intrinsic lengths for
two different situations: in accumulation and inversion
modes of operation respectively.
For both situations, the normalized photogenerated
current increases as LI is higher, because of the
increased photosensitive area.
One important fact that can be noticed when
comparing the two plots is that the behavior in current
with the temperature variation is the opposite. In one
hand, for accumulation mode (Figure 4), the current
decreases with temperature, and in the other hand, for
inversion mode, the current decreases with temperature.
10
>T
10
T=300K
1E-10
10
|I
|I
|I
|I
|I
|I
|I
|I
|I
VD=-1V
VBG=+15V
LI=1m
1E-4
ITOTAL [A]
-10
10
April 9 - 10, 2015, São Bernardo do Campo
99,0 99,5 100,0
LI [m]
Fig.4. Normalized photogenerated current as a
function of LI in accumulation mode.
24
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
Study of gated PIN CMOS BULK photodiode concerning intrinsic concentration
and gate bias.
Renato Zapata, Carla Novo, Renato Giacomini
Centro Universitário da FEI
e-mail: [email protected]
1. Abstract
In this paper we studied the behaviour of gated PIN CMOS
photodiodes by varying intrinsic carriers concentration and gate bias. It
was observed that the flat-band voltage and the threshold bias varies
depending on the gate position,. Another valid observation was the
increase in the device current as the intrinsic concentration decreases.
Furthermore, the gate terminal provides high charge control, although it is
an obstacle to the light.
Fig.1. Cross-section of one finger of a PIN photodiode.
2. Introduction
Many light sensor devices operate using the photoelectric nature of
light. The light particle (photon) has an energy that can be absorbed by an
electron in the valence band, promoting its transition to the conduction
band. This free electron must be quickly separated from the hole by an
electric field to avoid recombination [1]. One of the most common
photosensor is the PIN photodiode. This device consists of a PN junction
separated by an intrinsic region (which in practice corresponds to a
weakly doped region). The gate terminal localized above the intrinsic
region can make the control of charges in the intrinsic region. Although it
implies reducing the photosensitive region, the control gate gives us the
possibility of inducing charges in the substrate in a convenient way, in
order to provide photocurrent control.
Fig.2. (A) Offset left: device with the gate adjacent to P+ region. (B)
Offset right: device with gate adjacent to N+ region. (C) Central gate:
gate in the middle of the device. (D) Dual gate: device with
simultaneous right gate and left gate. (E) Full gate: gate all over the
entire intrinsic region. (F) No gate: common lateral PIN photodiode,
with no gate.
3. Device characteristics
4. Results and discussion
The characterized devices were simulated using the 0.25μm ONSemiconductor Technology described in [2],. The main technologic
parameters are shown in Table 1, [3]. A cross-section of one finger of the
device can be seen in Figure 1.
Six types of devices were simulated. The first one can be seen in
Figure 2-A. It has a left offset gate, which is placed adjacent to the P+
region. In the same way, Figure 2-B and Figure 2-C represent the right
offset gate device and the central gate device respectively, placed adjacent
to the N+ region and exactly in the middle of the intrinsic region. Figure 2D shows de dual gate device, which has two gates adjacent to the P+ and
N+ regions, with a space with no gate in the middle. A typical gated
lateral photodiode can be seen in Figure 2-E where the gate is over the
entire intrinsic length. A no gate device was simulated as well (see Figure
2-F) for comparisons. These six lateral PIN junction devices were
simulated in order to study the difference in operational behaviour due to
the intrinsic concentration and gate bias .
In order to study the effects of the gate position in the devices, some
important parameters of MOS capacitors were calculated using equations
1,2,3 and 4. The values of threshold bias (VT), flat-band bias (VFB) and
the maximum depth of the depletion layer (dmáx) in function of the
intrinsic P-Type doping concentration are plotted in Figure 3.
(1)
(2)
(3)
(4)
Where ΦF is the Fermi potential, kT/q is the thermal potential, NA is
the doping concentration, ΦM is the metal gate work function, ΦS is the
silicon work function, εSI is the silicon permittivity, q is the elemental
charge, tOX is the silicon-oxide thickness, Qdepletion is the depletion region
charge (in Coulombs), QSS is the interface charge and εOX is the siliconoxide permittivity [4]
As can be seen in Figure 3, the intrinsic concentration increase causes
a decrease in the flat-band bias and an increase in the threshold bias. As
the intrinsic region is doped with P-type material, gate bias must have
positive values in order to generate electrons at the first interface. Thus, the
greater the intrinsic doping concentration, the greater required gate bias to
promote inversion. For this reason, the threshold voltage increases with
the intrinsic concentration rises. On the other hand, the flat-band voltage
decreases (in a lower rate) when there are more holes (or P-Type doping
Table I. Parameters of Lateral PIN diodes.
Parameters
P and N region width (LP and LN)
Intrinsic region width (LI)
Oxide layer thickness (tox)
Junctions thickness (tP,tN)
Intrinsic region doping concentration (NI)
P region doping concentration (NP+)
N region doping concentration (NN+)
6.5 µm
11 µm
13.8 nm
0.15 µm
6x1016cm-3
1x1019cm-3
1x1020cm-3
25
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
Figure 7.
6.00E-011
6.00E-011
5.50E-011
5.50E-011
Maximum depletion region depth
5.00E-011
Flat-Band bias
Threshold bias
ID [A]
14
4.50E-011
4.00E-011
-3
13
-3
NI = 1x10 cm
VD= -1.5V
NI = 1x10 cm
14
-3
15
-3
NI = 1x10 cm
7
NI = 1x10 cm
3.50E-011
16
NI = 1x10 cm
3.00E-011
4.50E-011
-3
13
-3
14
-3
15
-3
16
-3
NI = 1x10 cm
NI = 1x10 cm
VD= -1.5V
NI = 1x10 cm
3.50E-011
-3
12
NI = 1x10 cm
CENTRALGATE
4.00E-011
NI = 1x10 cm
3.00E-011
2.50E-011
(A)
1E13
1E14
1E15
-3
-2
3
(B)
-3
-2
-1
0
1
2
3
VG [V]
3.40E-011
3.20E-011
Figure 4 shows the photogenerated current under light incident of
637nm of wavelength as a function of the gate bias for several different
intrinsic concentrations for the full gate device. At first sight, one can
observe that there is an increase in device current when intrinsic doping is
low. This is a consequence of the reduction in the recombination rate of
photogenerated carriers, increasing the amount of electrons separated by
the electric field. This same trend is observed in the device with a gate
adjacent to the N + region (Right Gate), as can be seen in Figure 5.
ID [A]
3.00E-011
12
-3
13
-3
14
-3
15
-3
16
-3
NI = 1x10 cm
5.00E-011
NI = 1x10 cm
NI = 1x10 cm
RIGHTGATE
NI = 1x10 cm
VD= -1.5V
NI = 1x10 cm
1
2
2.60E-011
RIGHT
CENTRAL
FULL
LEFT
2.20E-011
NI = 1x10
2.00E-011
-3
-2
-1
16
0
1
2
3
VG [V]
Fig.7. Total current of the device in function of the gate bias.
Another point observed in the simulations was that the Right-Gate
device presented higher current level than the Full-Gate device. Although
the Full Gate promotes a wider depletion region, it is a huge obstacle to
the incidence of light, creating a trade-off between great charge control on
the first interface and incident light obstacle. In Figure 5 can be seen that
under positive gate bias, reducing the concentration of intrinsic 1x1013cm-3
to 1x1012cm-3 we have a reduction in the current level. It is possible that
lower concentrations also causes more pronounced reductions, This fact
leads us to conclude that there is an optimal value of intrinsic
concentration, which results in a maximum current. Probably, this value is
situated between 1x1013cm-3 to 1x1012cm-3. It is more likely that in this
polarization, the carriers concentration is so low that the resistance in the
depletion region increases until a point where the current reduces.
3.00E-011
0
2.80E-011
2.40E-011
6.00E-011
-1
2
3.60E-011
Fig 3. Flat-Band bias, Threshold bias and maximum depletion
region depth in function of the intrinsic region doping. Source [4]
-2
1
Gate device. (B) Central Gate device.
1E16
-3
-3
0
VG [V]
Nintrinsic [cm ]
4.00E-011
-1
Fig.6. Total current of the device in function of gate bias. (A) Left
0
1E12
ID [A]
12
LEFTGATE
ID [A]
5.00E-011
dMAX [m]
VG [V]
is higher). The increase in the intrinsic concentration, promotes another
important effect, the decrease of the maximum depletion region depth,
since it becomes more difficult to neutralize all the holes.
1.15
1.10
1.05
1.00
0.95
0.90
0.85
0.80
0.75
0.70
0.65
0.60
0.55
0.50
0.45
0.40
0.35
0.30
0.25
0.20
April 9 - 10, 2015, São Bernardo do Campo
3
VG [V]
Fig.4. Total current of the device in function of the gate bias varying
the doping concentration of the intrinsic region.
4.00E-011
5. Conclusions
3.50E-011
Through simulations, it has been noted that the flat-band bias, as well as
the maximum depletion region depth, are reduced as the intrinsic
concentration increases. The opposite happens with the threshold bias,
which is increased with the doping increase. The simulations have shown
that the carriers recombination decreases when we have fewer holes in the
material. This was borne out by generating a curve of current as a function
of intrinsic concentration. We also observed that Right-Gate and FullGate devices had a similar behavior concerning to VG, just as happened
with the Left-Gate and the Central-Gate. It was found that the gate
provides higher charge control, although promoting a reduction in current
level due to opacity of the gate material, which prevents the light to
achieve the silicon material.
ID [A]
3.00E-011
2.50E-011
12
-3
13
-3
14
-3
15
-3
16
-3
FULLGATE
NI = 1x10 cm
VD= -1.5V
NI = 1x10 cm
NI = 1x10 cm
2.00E-011
NI = 1x10 cm
NI = 1x10 cm
1.50E-011
-3
-2
-1
0
1
2
3
VG [V]
Fig.5. Total current of the device in function of the gate bias varying
the doping concentration of the intrinsic region.
Also we can note in Figure 5 that both Right Gate and Full Gate have
the same behavior concerning gate bias variation. When the gate bias
(VG) reaches values between -2 and -1 volts, a gradual increase of the
current level happens. This variation becomes less pronounced and
occurs in a wider gate bias range when the intrinsic concentration
decreases. This happens due to the remoteness of the flat band bias and
threshold voltage as shown in Figure 3. Figure 6 shows the total current
as a function of the gate bias for the Left-Gate device (A) and the CentralGate device (B). The same trend observed in the devices of Figures 4 and
5 is presented here. The greater de intrinsic concentration, the smaller the
current level. On the other hand, the current level gradually changes in the
range of -2V and -1V of VG because there is a variation in the current, but
there is no increase in its level. It is interesting to note that the Full-Gate
and Right-Gate devices behave the same way, analogously to the LeftGate and Center-Gate, which behave similarly as well. This can be seen in
References
[1] C.F.James, Fundamentals of linear electronics: integrated and discrete.
Fundamentals of linear electronics: integrated and discrete. Cengage
Learning. 2001. Pg. 91.
[2] ON-SEMI.
[3] Novo.C.,Zapata.R. Batista.J. Stolf R. Giacomini R.; “Optimized design of
lateral PIN photodiodes regarding responsivity and SNR as a function of
operating temperature”. Centro Universitário da Fei: São Bernardo do
Campo, 2014.
[4] J.A. Martino, M. A. Pavanello, P.B. Verdonck. Caracterização elétrica de
Tecnologia e Dispositivos MOS. São Paulo, 2003.
26
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
Short Channel Effects Comparison between Double and Triple Gate
Junctionless Nanowire Transistors
Bruna Cardoso Paza and Marcelo Antonio Pavanelloa
a
Centro Universitário da FEI, São Bernardo do Campo, Brazil
e-mail: [email protected]
dimensional numerical simulations of JNTs implemented on
SOI technology considering double (DG) and triple (TG)
gate topologies. As shown in Fig. 1B, the double gate
devices are simulated with a thick top gate oxide thickness in
order to avoid the influence of the top gate. Figs. 1C and 1D
presents the front and the perspective view of the triple gate
architecture.
1. Abstract
In this work a comparison of short channel effects
occurrence in junctionless nanowire transistors with double
and triple gate structures is performed through three
dimensional numerical simulations. The threshold voltage
roll-off, degradation of the subthreshold slope and DIBL are
considered as figures of merit in this work.
2. Introduction
In order to continue the CMOS roadmap, different
technologies have been proposed by the scientific
community in the past few years. Different structures and
topologies have been studied to find the best performance
such as their digital and analog behavior, power
consumption and cost of fabrication. Whatever the
technology target of study, great scalability is always
requested in order to increase the number of devices per area
in the chip. On the other hand, the reduction of the
dimensions of transistors may cause some problems known
as short channel effects (SCEs) [1]. For example, Silicon-onInsulator (SOI) technology [2], multiple gate devices [3] and
junctionless nanowire transistors (JNTs) [4] have been
developed to reduce short channel effects.
The multiple gate architectures have been of great
interest of study, once the charges in the channel region are
better controlled by the gate, which reduces the SCEs and
allows stronger scaling in comparison to planar transistors
[3].
JNTs are characterized by being a stripe of silicon
uniformly doped from source to the drain as shown in Fig.
1A. Besides facilitating the fabrication of nanometric
transistors, once they do not have sharp junctions between
channel and source/drain, these devices have shown
advantages over inversion mode transistors in both digital
and analog applications [5, 6].
The operation mode of JNTs can be divided in three
modes, which are full depletion, partial depletion and
accumulation. When applied a gate voltage (VGS) lower than
the threshold voltage (VTH), the channel region is fully
depleted and the device is turned off. When VGS is between
VTH and the flatband voltage (VFB), the depletion starts to
reduce from the center of the silicon layer leaving a neutral
region, a body current appears and the device is turned on.
When VGS > VFB, there is an accumulation regime at the
surface, no depletion is observed and a surface current starts
to flow [7].
This work presents a comparison based on three
(A)
(B)
(C)
(D)
Fig.1. A: JNT cross section; B: Front view of 2G transistor;
C: Front view of TG transistor; D: 3G transistor perspective.
3. Devices Characteristics and Simulator
The JNTs have been simulated with Sentaurus Device
Simulator, from Synopsys [8], presenting uniform N-type
doping concentration of 5×1018cm-3 in channel region and Ptype polysilicon as gate material. Besides that, all transistors
have the geometrical dimensions indicated in Table I.
Table I. JNTs physical dimensions used in simulations.
Parameter
3G JNT 2G JNT
Top gate oxide thickness (tox,top)
2
40
Lateral gate oxide thickness (tox,lat)
2
2
Fin height (H)
10nm
100nm
Buried oxide thickness (tBOX)
100nm
Fin width (W)
20
Total channel length (L)
From 30 to 1000nm
In these simulations, it has been considered different
models, which describe the carriers’ mobility dependencies
on the doping concentration, temperature, normal electric
field, velocity saturation of the carriers in high electric fields,
27
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
dependence of the bandgap narrowing and recombination on
the doping concentration. For all the simulations the
temperature was set at 300K.
300
DIBL [mV/V]
250
4. Results
Fig. 2 shows the drain current normalized by the
effective channel width (Wef = 2×H for 2G and Wef = 2×H+
W for 3G) versus the gate voltage of triple and double gate
JNTs, for VDS=50mV. The results are presented in
logarithmic scale so it is possible to observe the stronger
degradation of the subthreshold characteristic in the 2G
devices. Moreover, due to the differences in VTH and the
stronger degradation of the subthreshold slope (S), 2G JNTs
present off state current (IOFF defined here as IDS at VGS =
0V) several orders of magnitude higher than the 3G JNTs.
IDS/Wef [A/m]
5E-5
5E-5
5E-6
5E-6
3G JNT
VDS=50mV
5E-9
2G JNT
5E-10
5E-11
5E-12
0.0
VDS=50mV
5E-9
L=30, 40, 50, 60, 80, 5E-10
100, 125, 250, 375,
5E-11
500, 625,750, 875,
1000nm
5E-12
0.5
1.0
1.5
2.0
0.0
VGS [V]
L=30, 40, 50, 60,
80, 100, 125, 375,
625, 875, 1000nm
0.5
1.0
1.5
VTH,1- VTH,2
DIBL = ___________
VDS,2 - VDS,1
100
50
L[nm]
1000
From the results presented in Fig. 3, it is possible to note
that the effects caused by reducing the total channel length
are much stronger in 2G than in 3G JNTs. For VTH the
degradation is two times higher in the worst case, L = 30nm,
and it is 175% and 280% higher for S and DIBL,
respectively. Besides this, one can observe that the SCEs
become apparent in the curves of Fig. 3 for transistors
shorter than 80nm. Moreover, from 80nm to 1000nm the
degradation of the parameters is quite similar between the
2G and 3G JNTs studied.
5E-8
5E-8
280%
150
Fig.3. VTH (A), S (B) and DIBL (C) vs L for 2G and 3G JNTs.
5E-7
5E-7
200
100
L reduction
L reduction
3G JNT
2G JNT
(C)
0
5E-4
5E-4
April 9 - 10, 2015, São Bernardo do Campo
5. Conclusions
This work has presented a comparison between the
SCEs in 2G and 3G JNTs through the analysis of
simulations where VTH, S and DIBL parameters have been
extracted for several channel lengths.
With this work we could observe that the influence of
the top gate in the channel region may reduce very
significantly VTH roll-off, S and DIBL degradation,
improving scalability and performance. For S we have
shown an improvement of 175% on the subthreshold slope
obtained for 2G JNTs with L of 30nm.
2.0
VGS [V]
Fig.2. IDS/Wef vs VGS with VDS=50mV for 3G and 2G JNTs.
Figs. 3 show the results extracted for VTH, S and DIBL
as a function of L for 2G and 3G JNTs. VTH and S have been
obtained from the IDS-VGS curves at VDS = 50mV, while
DIBL has been calculated according to the expression
indicated in Fig. 3C, where VTH,1 and VTH,2 are the threshold
voltages extracted at VDS,1 = 50mV and VDS,2 = 1.5V.
0.8
Acknowledgments
(A)
VTH [V]
0.7
0.6
The authors would like to thanks FAPESP and CNPq
for the financial support to this work.
70mV
0.2
0.1
140mV
VDS = 50mV
References
3G JNT
2G JNT
[1] J. P. Colinge, C. A. Colinge, Physics of Semiconductor Devices,
Kluwer Academic Publishers, NY, 2002.
[2] J. P. Colinge, Silicon-On_Insulator Technology: Materials to
VLSI, 3rd Boston Edition, Kluwer Academic Publishers, NY, 2004.
[3] J. P. Colinge, FinFETs and Other Multi-Gate Transistors. 1st
Springer Edition, 2008.
[4] J. P. Colinge, et al., SOI gated resistor: CMOS without junctions,
IEEE International SOI Conference, pp. 1-2, 2009.
[5] R. T. Doria et al., Junctionless multiple-gate transistors for
analog applications, IEEE Transactions on Electron Devices, vol.
58, pp. 2511-2519, 2011.
[6] S. Barraud et al., Scaling of trigate junctionless nanowire
MOSFET with gate length down to 13nm, IEEE Electron Device
Letters, vol. 33, pp. 1225-1227, 2012.
[7] J. P. Colinge, et al., Nanowire transistors without junctions,
Nature Nanotechnology, vol. 5, n. 3, pp. 225-229, 2010.
[8] Sentaurus Device User Guide, Version C-2009.06, 2009.
0.0
100
1000
L[nm]
250
3G JNT
2G JNT
(B)
S [mV/dec]
200
150
VDS = 50mV
175%
100
50
100
1000
L[nm]
28
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
Modelling of the leakage current in MOS thin silicon oxynitrides aiming at MOS
tunnel diodes
B. S. Alandiaa , V. Christianoa and S.G. dos Santosa
a
University of São Paulo - LSI/PSI/EPUSP
e-mail: [email protected]
parameters from C-V characteristics measured in
parallel with G-V characteristics.
1. Abstract
Thin silicon oxynitrides (2.42nm) were grown by
rapid thermal oxidation (RTO) in ultrapure nitrogen and
oxygen (5N2:1O2 ratio) at 850°C. Using this recipe, high
levels of leakage current were obtained (> 10-3A), so
that, the accumulation capacitance ceases to be constant
and stationary deep depletion starts to occur. The
modelling of the leakage current pointed out to currentvoltage characteristics consistent with MOS tunnel
diodes for large areas of 250m x 250m and 700m x
700m.
4. Electrical Modeling
C-V curves were modeled by the electrical circuits
shown in Fig.1., where 𝐶𝑂 is the accumulation
capacitance, 𝑌𝑐 is an admittance that represents a
leakage process [4], 𝑅𝑆 [5] is the series resistance
associated to the silicon substrate, 𝑅is a series resistance
intentionally introduced in order to limit the leakage
current and aiming to extract C-V and G-V curves for
capacitors with 700m in length (for capacitors with
length of 250m 𝑅 = 0), 𝐶𝑆 is the silicon capacitance,
𝐶𝑀𝐷 is the measured capacitance and 𝐺𝑀𝐷 is the
measured conductance.
2. Introduction
Due to a constant need in reducing the dimension of
MOS devices without loss in performance, ever more
thin gate oxides has been employed in the fabrication of
metal-oxide-semiconductor (MOS) structures including
alternative devices such as MOS tunnel diodes. [1]. On
the other hand, the thickness reduction causes some side
effects such as tunneling current [2] through the oxide
and deep depletion in the silicon body [3].
Both effects will be studied in more detail in this
article by obtaining curves of the Capacitance-Voltage
(C-V) and Conductance-Voltage (G-V), besides an
electrical modeling and detailed calculations to
determine parameters of interest.
Fig.1. (a) Electrical model considering the leakage current
through the MOS structure and (b) capacitance and
conductance measured at the accumulation region.
3. Experimental
Since the leakage current was around 10-3 A at
accumulation, 𝐶𝑂 is short-circuited in the model
because the leakage is very high through the oxide
(infinite admittance). As a result, considering equal
impedances for circuits in Figs. 1 and 2, we can deduce
a simple expression for silicon capacitance (𝐶𝑆 ) as
follows:
For the fabrication of MOS capacitors, it was used
Si wafers (100) p-Type with resistivity ranging from 1
to 10cm and cleaning was performed According to the
following steps: H2O DI rinse during 5min; Immersion
in a 4 H2O + 1 H2O2 (30%) + 1 NH4OH (35%) solution
at 90°C during 15min; H2O DI rinse during 5min;
Immersion in a 4 H2O + 1 HCl (36.5%) solution at 90°C
during 15min; H2O DI rinse during 5min; Dip in 80
H2O + 1 HF (49%) solution during 100s; H2O DI rinse
during 5min and finally drying in ultrapure N2.
Following, the thin (2.42nm) gate oxide (SiO2) was
grown by RTO using a mixture of 5N2:1O2 at
850C°.Then, 200nm-aluminum films were deposited by
thermal evaporation onto this ultrathin oxides. Finally,
lithography was performed to define the square MOS
capacitors areas with 250m and 700m in length.
MOS capacitors were electrically characterized with
the aid of HP 4280 C at 1MHz or Agilent E4980A
Precision LCR Meter at 1MHz in order to obtain
𝐶𝑆 =
𝐺𝑀𝐷 ²+(𝜔.𝐶𝑀𝐷 )²
𝜔²𝐶𝑀𝐷
(1)
And, a simple expression for series resistance (𝑅𝑆 ),
given by:
𝐺𝑀𝐷
𝑅 + 𝑅𝑆 = 𝐺 ²+(𝜔.𝐶
(2)
)²
𝑀𝐷
𝑀𝐷
Where 𝜔 = 2𝜋𝑓. Knowing the 𝐶𝑆 values found in
(1) we can obtain the values of the width of the
depletion region (𝑊𝐷𝑀𝐴𝑋 ) at the invesion using the
following expression [3]:
𝜀0 𝜀𝑆𝑖 𝐴𝑔
𝑊𝐷𝑀𝐴𝑋 = 𝐶
(3)
𝑆
29
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
where 𝜀0 is the relative permittivity, 𝜀𝑆𝑖 is the silicon
permittivity and 𝐴𝑔 is the area of the capacitor.
Finally, from the WDMAX values, we can stablish or
not if deep depletion occurs. In addition, the substrate
doping (𝑁A ) was obtained as follows [3]:
1
(4)
𝑁𝐴 =
WDMAX. It is noteworthy that the high level of leakage
current establishes a stationary deep depletion in the
silicon since WDMAX was systematically higher than WD
(equilibrium value of the depletion width). At the
inversion region the leakage process is shielded by the
depletion region, so that, the leakage current decreases
from ~10-3A to the ~10-6 A for the square MOS
capacitors, 700m in length. Therefore, the gatedielectrics structures are working as MOS tunnel diodes.
𝜌 𝜇𝑝 𝑞
where 𝜌 is the resistivity, 𝜇𝑝 is the holes mobility and 𝑞
is the effective charge of the electron. Using (4) we also
extracted the equilibrium value of the depletion width in
order to compare it with the stationary value of the deep
depletion [3]:
𝑊𝐷 = √
2 𝜀0 𝜀𝑆𝑖 1
𝑞
𝑁𝐴
April 9 - 10, 2015, São Bernardo do Campo
Table I. CS, R+RS and WDMAX as extracted from the modelling
250m
700m
Sample A1 Sample B1 Sample A2 Sample B2
(5)
𝐶𝑀𝐼𝑁 (pF)
3.480.19
3.250.33
41.72.1
42.30.02
0.00
12.61.8
15.32.7
3.430.09
41.82.1
42.50.3
𝐺𝑀𝐼𝑁 (𝜇 S)
0.00
5. Results and Discussion
𝐶𝑆 (pF)
3.480.19
Fig. 2 and Fig. 3 show C-V and G-V curves for
square MOS capacitors, 250m and 700m in length,
respectively.
𝑊𝐷𝑀𝐴𝑋 (𝜇𝑚)
𝑅 + 𝑅𝑆 (Ω)
-3
0.00
1.880.18
0.00
17721
21538
1.890.05
1.250.12
1.190.01
𝑁𝐴 (cm )
0.18 – 1.79 E16
𝑊𝐷 (𝜇𝑚)
0.27 – 0.85
6. Conclusions
In conclusion, thin silicon oxynitrides (2.42 nm)
were grown by rapid thermal oxidation (RTO) in
ultrapure nitrogen and oxygen (5N2:1O2 ratio) at 850°C
and high levels of leakage current were obtained (> 10 3
A), so that, the accumulation capacitance ceases to be
constant and stationary deep depletion starts to occur.
The modelling of the leakage current pointed out to
current-voltage characteristics consistent with MOS
tunnel diodes for large areas of 250m x 250m and
700m x 700m.
Fig.2. C-V and G-V curves for square MOS capacitors,
250m in length.
Acknowledgments
It is noteworthy that the accumulation capacitance is
not constant due to high level of the leakage current to
which the capacitors have presented.
The authors would like to thank CNPq for the
financial support.
References
[1] M. Depas, R. L. Van Meirhaeghe, W. H. Laflere, and F.
Cardon, “Electrical characteristics of Al/SiO2/n-Si tunnel
diodes with an oxide layer grown by rapid thermal oxidation”,
Solid-State Electron., vol. 37, p. 433-441, 1994.
[2]S.-H. Lo, D. A. Buchanan, Y. Taur, and W.Wang,
“Quantum mechanical modeling of electron tunneling current
from the inversion layer of ultra-thin-oxide nMOSFET’s,”
IEEE Electron Device Lett., vol. 18, p. 209–211,1997.
[3] E.H. Nicollian and J.R. Brews, “MOS physics and
technology, 1st ed.,. Wiley: New Jersey, 1982.
[4]K. J. Yang, E.M. Hu, "MOS capacitance measurements for
high-leakage thin dielectrics,” IEEE Trans. Electron Dev., vol.
46, p. 1500, 1999.
[5]S.M. Rajab, I.C. Oliveira, M. Massi, H.S. Maciel, S. G. dos
Santos Filho, R.D. Mansano, "Effect of the thermal annealing
on the electrical and physical physical properties of SiC thin
films produced by RF magnetron sputtering." Thin Solid
Films, vol. 515, p. 170, 2006.
Fig.3. C-V and G-V curves for square MOS capacitors,
700m in length.
Thus, we can assume that the accumulation
capacitance is being short-circuited. Based on the model
in Fig. 1, it was extracted CS, R+RS and WDMAX.
Table I shows the extracted CS, R+RS, WD and
30
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
The effect of bias in X-Ray Effects on MOSFETs
F.G.H. Leitea, R.B.B. Santosa, M.A.G. Silveiraa
a
Centro Universitário da FEI, São Bernardo do Campo – São Paulo
E-mail: [email protected], [email protected]
dose.
Due to thermal annealing at room temperature, all
data used in the analysis were extracted 168 hours after
the irradiation [2, 3]. Threshold voltage was extracted
using the second derivative method.
The nMOS was biased with VGS = 3.17 V and
VDS = 815 mV. The pMOS was biased with
VGS = -3.17 V and VDS = - 1.39 V.
Figure 2 shows the electrical circuit used to bias the
nMOS and pMOS devices. A development board based
on ARM Cortex-M0+ was used to apply the VG voltage
while an ADC pin was used to read the VR voltage
which is proportional to the drain current I D. Estimated
drain current was shown in a LCD display, so it was
possible to observe how the drain current changed
during irradiation of the device (Fig. 3).
1. Abstract
The ionizing radiation from radiation sources can
affect electronic devices in multiple ways. The ionizing
radiation generates electron-hole pairs in the oxide and
in the Si/oxide interface of the MOS structure, which
may change some parameters of the device, such as
threshold voltage and carrier’s mobility [1, 2]. The way
the electron-hole pairs are generated and trapped in the
oxide defects depends on the electric field in the oxide,
which interferes in the current of charge carriers in the
depletion region. The electric field may have different
directions regarding the channel type of the device [1,
2].
In this work, we evaluate the damage of ionizing
radiation on P and N type MOSFETs and show how
bias voltages (VGS and VDS), during the irradiation,
affects the damage imposed on the device.
2. Methodology
The off-the-shelf IC CD4007 was used as a sample.
This IC contains 3 CMOS logic inverter and all of its
six MOSFETs may be biased individually.
The devices under test (DUT) were irradiated using
the X-Ray diffractometer Shimadzu XRD-7000 (Fig. 1)
with the following setup: effective energy of 10 keV
and a dose rate of 96 (5) rad(Si)/s. The table 1
summarizes the experimental setup and overall status.
Table I. Experimental setup and status.
IC
11
12
Dose Rate
(rad(Si)/s)
96 (5)
96 (5)
Total Dose
Accumulated
100 krad
100 krad
Device
Biased
nMOS
pMOS
15
96 (5)
100 krad
-
Fig.2. Electrical circuit used to bias the devices.
DUT
Fig.3. Electrical circuit used to observe drain current in
real time.
3. Results
Fig.1. The X-Ray Diffractometer setup for irradiation.
The IDS-VGS curves were extracted using specific
equipment for electrical characterization. The DUTs
were analyzed before and after accumulating radiation
Figure 4 presents ID-VGS characteristic curves for
the nMOS and the pMOS devices in the biased and in
the unbiased conditions during irradiation. The results
31
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
may be interpreted as follows. The electric field
generated in the oxide due to the voltage applied to the
device affects the behavior of the electron-hole pairs
that are generated by ionizing radiation. With no bias
voltage, the electrons flows through the gate terminal
and the holes are trapped in the oxide traps and interface
traps [4]. The electric field’s direction depends on the
device’s type. In the nMOS, the electric field push more
holes towards the interface traps, which increases the
drain current. In the pMOS, the opposite effect occurs.
The electric field pulls more holes towards the gate
terminal, which makes the threshold voltage lower.
Fig.6. VTH as a function of total accumulated dose for
biased and unbiased pMOS.
4. Conclusions
The results suggest that ionizing radiation effects on
MOSFETs depends on the presence or absence of bias
and on the type (P or N) of the device,. This is an
important fact to bear in mind when evaluating the
worst-case scenario. The results show that the worstcase scenario for nMOS is when a bias voltage is
applied in the device while the worst-case scenario for
pMOS is when no bias voltage is applied.
Fig.4. ID-VGS curve for nMOS and pMOS devices on
biased and unbiased conditions.
Regarding the shift of the threshold voltage (VTH),
the shift was greater for nMOS biased and lower to the
pMOS biased. This means that the worst-case condition
depends on the type of the device (Fig.5 and Fig.6).
Acknowledgments
This work was supported by Centro Universitário
da FEI, FINEP/CITAR, FAPESP and CNPq.
References
[1] CANDELORI, A.; CESCHIA, M.; PACCAGNELLA, A.;
WYSS, J.; BISELLO, D.; GHIDINI, G. Thin oxide
degradation after high-energy ion irradiation. IEEE
Transactions on Nuclear Science, vol. 48, no. 5, out. 2001.
[2] CLAYES, C.; SIMOEN, E. Radiation effects in advanced
semiconductor materials and devices. Berlin: Springer, 2002.
[3] SCHRIMPF, R. D.; FLEETWOOD, D. M. (Ed.).Radiation
effects and soft errors in integrated circuits and electronic
devices. Singapore: World Scientific, 2004.
[4] SILVEIRA, M.A.G.; SANTOS, R.B.B.; LEITE, F.G.H;
CUNHA, F.G.; CIRNE, K.H.; MEDINA, N.H.; ADDED, N.;
AGUIAR, V.A.P. Radiation Effect Mechanisms in Electronic
Devices. Proceedings of Science, X LASNPA, no. 77, 2013.
Fig.5. VTH as a function of the total accumulated dose
for biased and unbiased nMOS.
32
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
OCTO Layout Variations as an Alternative to Mitigate TID Effects
L. N. S. Finoa, M. A. G. da Silveirab, C. Renauxc, D. Flandrec and S. P. Gimeneza
a
Department of Electrical Engineering, Centro Universitário da FEI
b
Department of Physics, Centro Universitário da FEI
c
ICTEAM / ELEN, Université catholique de Louvain
e-mail: [email protected]
Lengths Effect (PAMDLE) and 3 - Deactivate the
Parasitic MOSFETs in the Bird’s Beak Regions Effect
(DEPAMBBRE) [3].
1. Abstract
This paper performs an experimental comparative
study between the OCTO SOI MOSFET (octagonal gate
geometry) and its derivations (different angles) as a total
ionizing dose (TID) effects mitigation strategy. After a
TID equal a 600 krad were analyzed the leakage current
(ILEAK) behaviour in order to indicate the better
configuration for digital applications in radioactive
environment. The α angle equal to 53.1° achieved
promising resultsfor low power and low voltage
applications due ILEAK reduction in function of the TID.
3. Device Description
The OSM is an evolution of diamond SOI MOSFET
(designed with a hexagonal gate style) through a cut
factor “c” defined as a percentage reduction on the
edges of hexagonal channel region, resulting in an
octagonal gate. The OSM can be design with different α
angles (in the metallurgical junction) as indicated in Fig
1a by the symbol “α”. Fig 1a, 1b and 1c represent the α
angle equal to 53.1°, 90° and 126.9°, respectively. All
devices showed in Figure 1 adopt the same cut factor
“c” (equal to 25%) and channel width “W” (equal to
30μm) and shorter dimension “b” (equal to 5μm). In
Fig. 1c, b (equal to 5μm) and B (equal to 16.5μm) are
respectively the shorter and longer dimensions of the
channel length (L). In Figs 1a and b the B value are
equal to 50μm and 27.5μm respectively.
2. Introduction
The OCTO Fully Depleted (FD) Silicon-On
Insulator (SOI) technology, also called OSM, combine
into one device architecture most advantages needed for
mainstream applications allowing low power, high
performance and radiation robustness at the same time
[1, 2 and 3]. SOI technologies have already
demonstrated their ability to mitigate Single-Event
Effects (SEE) due to their structure [4]. However
radiation effect studies dedicated to total ionizing dose
(TID) effects in FDSOI technologies have highlighted
that radiation-induced positive charge trapping into the
buried oxide (BOX) directly impacts the main currentvoltage characteristics [5, 6, 7], through electrostatic
coupling effects [8] inherentto this particular device
architecture.
This was identified asa main drawback for the use of
FDSOI technologies for radiationdedicated applications.
However, this TID sensitivitycan be mitigated in OSM.
The threshold voltage shift of FDSOI n-type is strongly
correlated with chargetrapping in the buried oxide.TID
induces negative threshold voltage shifts in FDSOI
transistors since the radiation-inducedtrapped charges
are mainly positive.
Thinner buried oxides, which areless dose sensitive
than thicker ones, not necessarily improve theradiation
hardness of fully depleted transistors because of the
higher coupling effect. The lateral parasitic transistor is
more affected by the buried oxide charge trapping than
the main active transistor.
Considering the OSM devices that have your
channel region changed from a rectangular design
(standard device) to octagonal arises three special
effects: 1- Longitudinal Corner Effect (LCE), 2 -Parallel
Association of MOSFETs with Different Channel
(a)
(b)
(c)
Fig.1. Octo device with angles equal to 53.1° (a), 90° (b) and
126.9° (c)
4. Experimental Details
All samples (n-channel FD SOI MOSFET) were
manufactured in the WINFAB clean rooms of the
Université catholique de Louvain (UCL), Belgium, with
tox, tSi and tBOX equal to 30 nm, 80 nm and 390 nm,
respectively and the channel and drain/source doping
concentrations equal to 6.1016 cm-3 and 1.1020 cm-3,
respectively. The supply voltage of this CMOS
technology is equal to 5V.
The analyzed transistors are irradiated in a floating
condition [9] and on wafer at room temperatureusing
10-keV X-rays at a constant dose rate of 23.5krad/min
(392rad/s) by a Shimadzu XRD-7000. Static electrical
measurements are performed using a Keithley 4200
after each irradiation step from 500 krad to 600 krad
33
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
with steps of 50 krad.
Previous works also demonstrate the benefits by
using the octagonal device in non-radioactive
environment as well in environment with ionizing
radiation [1, 2, and 3]. However, this paper aims to
show the impact of the angle αon the leakage current
(ILEAK) after a total ionizing dose equal to 600 krad.
bird’s beak region (DEPAMBBRE effect) and lower
perimeter than the others devices Consequently, the α
angle equal to 53.1° of the OSM allows alow power and
high performances at the same time for radioactive
environment applications.
5. Experimental Results
The authors would like to thank CNPq, FAPESP,
CAPES and FINEP (CITAR) for the financial support.
Acknowledgments
Figure 2 exhibits the transfer characteristics curves
of OSM before and after irradiation with drain biased at
3.0V considering α angles equal to 53.1°, 90° and
126.9°
References
[1] Fino, L.N. S., Renaux C., Flandre D., and Gimenez S. P,
“Experimental Study of the OCTO SOI nMOSFET and Its
Application in Analog Integrated Circuits”, ECS Trans., v.49,
p.527-534, 2012.
[2] Fino, L.N. S., Silveira, M. A. G., Renaux C., Flandre D.,
and Gimenez S. P.. Improving Unit Voltage Gain Frequency
of Integrated Circuits by Using OCTO Layout Style. In:
EUROSOI 2013: Ninth Workshop of the Thematic Network
on Silicon on Insulator Technology, Devices and Circuits,
Paris. EUROSOI 2013, 2013;
[3] Fino, L.N. S., Silveira, M. A. G., Renaux C., Flandre D.,
and Gimenez S. P. “Total Ionizing Dose Effects on the Digital
Performance of Irradiated OCTO and Conventional Fully
Depleted SOI MOSFET. In: Radiation Effects on Components
and Systems, 2013, RADECS 2013. London.
[4]V. Ferlet-Cavrois, P. Paillet, M. Gaillardin, D. Lambert, J.
Baggio, J.R. Schwank, G. Vizkelethy, M. R. Shaneyfelt, K.
Hirose, E.W. Blackmore,O. Faynot, C. Jahan, and L. Tosti,
“Statistical analysis of thecharge collected in SOI and bulk
devices under heavy ion and proton irradiation – Implications
for digital SETs,” IEEE Trans. Nucl. Sci., vol.53, no. 6, pp.
3242–3252, Dec. 2006.
[5] W. C. Jenkins and S. T. Liu, “Radiation response of fullydepletedMOS transistors fabricated in SIMOX,” IEEE Trans.
Nucl. Sci., vol.41, no. 6, pp. 2317–2321, Dec. 1994.
[6] P. Paillet, M. Gaillardin, V. Ferlet-Cavrois, A. Torres, O.
Faynot, C.Jahan, L. Tosti, and S. Cristoloveanu, “Total
ionizing dose effects ondeca-nanometer fully depleted SOI
devices,” IEEE Trans. Nucl. Sci.,vol. 52, no. 6, pp. 23452352,
Dec. 2005.
[7] J. R. Schwank, M. R. Shaneyfelt, P. E.Dodd, J. A. Burns,
C. L. Keast,and P. W. Wyatt, “New insights into fully
depleted SOI transistor responseafter total-dose
irradiation,”IEEE Trans. Nucl. Sci., vol. 47, no.3, pp. 604–
612, Jun. 2000.
[8] H. K. Limand J. G. Fossum, “Threshold voltage of thin
film silicon-oninsulator(SOI) MOSFET’s,” IEEE Trans.
Electron Dev., vol. ED-30,no. 10, pp. 1244–1251, Oct. 1983.
[9] A. Griffoni, S. Gerardin, P. J. Roussel, R. Degraeve, G.
Meneghesso, A. Paccagnella, E. Simoen and C. Claeys, “A
Statistical Approach to Microdose Induced Degradation in
FinFET Devices,” IEEE Trans. Nucl. Sci., vol. 56, no. 6, pp.
3285-3292, December, 2009.
[10] P. C. Adell, H. J. Barnaby, R. D. Schrimpf, and B.
Vermeire, “Band-to-Band tunneling (BBT) induced leakage
current enhancement in irradiated fully depleted SOI devices,”
IEEE Trans. Nucl. Sci, vol. 54, no.6, pp. 2174–2180,2007.
IDS/ (W/L)(A)
-2
10
VDS=3.0V
-3
10
-4
10
-5
10
-6
10
-7
10
-8
10
-9
10
-10
10
-11
10
-12
10
-2
OSM 90° pre
OSM 53.1° pre
OSM 126.9° pre
OSM 90° TID
OSM 53.1° TID
OSM 126.9° TID
0
VGS(V)
2
4
Fig.2. IDS/(W/L) vs VGS characteristics of the OSM before the
irradiation (filled symbols) and after the irradiation (open
symbols), considering TID equal to 600 krad and VDS=3.0V
and angles equal to 53.1° (red lines), 90° (black lines) and
126.9° (green lines).
Analyzing Figure 2, we can observe that after the
total ionizing dose irradiation the leakage current
(ILEAK,VGS=-2.0V) of the OSM with α=90° and
α=126.9° increased 8.27 times and 2.28 times,
respectively. These results are mainly due to the buildup
of oxide-trapped charge in field oxides that triggers the
parasitic lateral conduction with the same results of the
standard device [3, 10]. On the other hand, the opposite
effect occurs in the OSM with α=53.1°, when the ILEAK
decreased 2.76 times due the Deactivate the Parasitic
MOSFETs in the Bird’s Beak Regions Effect
(DEPAMBBRE). Also was observed that the leakage
current has a perimeter and α angle dependence.
Increasing the angle and consequently the perimeter,
occurs the increase of the I LEAK.
6. Conclusions
This paper focuses to show the octagonal device as a
TID hardening strategy in function of the layout
configuration. On this way, was found that OSM with α
angles higher than 53.1° showed an ILEAK behavior
similar than the standard device, i. e., with the increase
in function of the TID. Nevertheless, the ILEAK of OSM
with α angle equal to 53.1° was decreased in function of
TID due the non-activation of parasitic transistors in the
34
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
Demonstration of a Low Voltage Power Converter with Application to
Photovoltaic Cells
A. C. C. Telles, S. Finco, J. L. Emeri Jr.
Center for Information Technology Renato Archer - CTI
e-mail :{antonio.telles, saulo.finco, jair.emeri}@cti.gov.br
1. Abstract
A. The Low Voltage Oscillator
This work describes a power converter that is able to
operate with the voltage of a single photovoltaic cell or
other source that generates similar voltage. A prototype
was assembled that starts with a minimum supply of
620 mV and can generate an output of 5.6 V into a 1m
W load. The circuit uses a chip in 0.6 µm CMOS
technology from CEITEC.
The low voltage oscillator is based on the inductive
load ring oscillator [1]. For the case in use, when N=2, it
is also known as cross-coupled oscillator [2]. With the
use of inductors, this topology is able to reduce the
minimum supply voltage and to boost the oscillation
amplitude beyond the supply rail [3].
In this work, the circuit operates as astable
multivibrator. All inductors are mutually coupled.
Simulations showed that the power efficiency is higher
in this case than that when the load is coupled with just
one side of the oscillator.
M0 and M1 are large transistors, in order to present
low resistance when conducting and hence to improve
the efficiency. Due to this low resistance, R0, R1 and
R2 were introduced to represent the losses of the
inductors, this way achieving a more realistic model of
the circuit.
L2 feeds the next block, the negative voltage
converter, with an amplified version of the oscillator
waveform, due to the high turns’ ratio.
2. Introduction
Some energy sources, like thermopiles and
photovoltaic cells, generate too low voltages to be
directly connected to electronic circuits. Usually, to
solve this problem these sources are stacked in order to
reach the minimum useful voltage. This approach
however brings some problems. In a group of
photovoltaic cells, the efficiency is demanded by the
weakest. It would be interesting that the power be
extracted from single cells, delivering this power in
parallel to the load and therefore reaching higher overall
efficiency.
This work proposes a circuit dedicated to solve this
problem. It uses a chip constructed in 0.6 µm CMOS
technology from CEITEC and a magnetic circuit.
Section 3 describes the circuit. Each block of the
circuit is explained in details. The prototype and
experimental results are presented in Section 4 and 5
respectively. Section 6 brings the conclusions and
discusses future works.
B. The Negative Voltage Converter
This block has the purpose of converting the
negative half waves into positive ones, thus behaving as
full-wave rectifier. This conversion works as follows: a
high voltage potential at VS+ leads to the conducting
stage of M4 and M3. Thus current can flow from VS+
over M4 to the output and then back to VS- over M3. In
the opposite voltage case M5 and M2 are conductive.
More details of this circuit can be found in [4].
3. The Low Voltage Converter
C. The Voltage Regulator
The circuit is composed by three blocks: a low
voltage oscillator, the negative voltage converter that
behaves as a full-wave rectifier and the voltage
regulator (Fig. 1).
The block above described cannot be used to charge
a storage capacitor, because the current direction is not
controlled and current back flow occurs.
35
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
Fig. 3 shows the main waveforms for this
experiment.
Due to this a second stage is necessary to realize a
useful rectifier [4]. Junction diodes are not available in
standard MOS technology. The solution was the use of a
transistor to control the current flux.
The transistor chain (M6 to M11 in Fig. 1) acts as
Zener diode to M12, with the voltage drop finely
adjusted by R6. M12 only conducts when the input
voltage is higher than the voltage at the load capacitor
by Vth, the threshold voltage of the transistor. Together
with the voltage drop at the transistor chain, this defines
the output voltage.
However, M12 is still a bidirectional device and
reverse conduction can occur with the adequate
situation. This happens when the input is lower than the
output voltage by Vth. Since the original waveform
tends to be a square wave, the rectified waveform is
close to a DC voltage. Thus voltages at the input that
could lead to reverse conduction occur only for a short
time, when they occur.
Fig.3. Experimental waveforms for 600 mV power supply: 1Voltage at VS+ (2 V/div), 2- Voltage at VS- (2 V/div), 3Differential voltage at L2 (5 V/div), 4- Ripple at output (50
mV/div), 5 Voltage at the drain (1 V/div).
6. Conclusions and Future Works
The circuit was able to operate with a voltage
equivalent to that generated by a single photovoltaic cell
and supply levels of voltage and power compatible with
most of electronic circuits. The circuit however can
have its efficiency greatly improved with the
optimization of the dimensions of the transistors,
especially those from the negative voltage converter and
the pass transistor (M12).
It is possible also that the circuit works better at a
lower frequency, when the waveforms get closest to
square waves. This could help to minimize the reverse
conduction, as explained in the description of the
voltage regulator.
Another circuit is being prepared, that could operate
with supply voltages as low as 40 mV.
4. The Prototype
The prototype used the chip tv_devices_05,
constructed in 0.6 µm technology from CEITEC (Fig.
2). Dimensions of the transistor from Fig. 1 are shown
in Table I. Inductors were mounted in an EE type ferrite
core with gap. Values are shown in Table II, for a
frequency of operation of 200 kHz.
Table I. Dimensions of the transistor of tv_devices_05.
M0 and
M2 to
M6 to
Transistor
M12
M1
M5
M11
W/L(µm/µm) 128000/1 500/0.6
10/0.7
100/0.7
Table II. Parameters of the magnetic circuit.
L0 and R0 and
L2
Component
L1
R1
Value
9 µH
200 mΩ
780 µH
April 9 - 10, 2015, São Bernardo do Campo
R2
Acknowledgments
8Ω
The authors would like to thank CNPq by the
scholarship of J. L. Emeri Jr. through CITAR Project
and CEITEC by supplying the chip samples.
References
[1] J. Savoj and B. Razavi, “A 10-Gb/s CMOS clock and data
recovery circuit with a half-rate binary phase/frequency
detector,” IEEE J. Solid-State Circuits, vol. 38, no. 1, pp. 13–
21, Jan. 2003.
[2] G. Li and E. Afshari, “ A low-phase-noise multi-phase
oscillator based on left-handed LC-ring,” IEEE J. Solid-State
Circuits, vol. 45, no. 9,pp. 1822–1833, Sep. 2010.
[3] M. B. Machado, M. C. Schneider and C. Gallup-Montoro,
“On the minimum supply voltage for MOSFET oscillators”,
IEEE Trans. Circ. Systems I: Regular Papers, vol. 61, no. 2,
pp. 347-357, Feb. 2014.
[4] C. Peters, O. S. Kessling, F. Henrici, M. Ortmanns and Y.
Manoli, “CMOS integrated highly efficient full wave
rectifier”, Proc. IEEE International Symposium on Circuits
and Systems, 2007, pp. 2415-2418.
Fig.2. Layout of chip tv_devices_05 (length and width not to
scale).
5. Experimental Results
The circuit was able to start operating with a power
supply of 620 mV. It could deliver 1 mW with an output
of 5.6 V for a 700 mV supply and a load of 30 kΩ in
parallel of 47 nF. After starting, the circuit keeps
working when the supply voltage is lowered to 500 mV.
36
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
Photonic-Integrated Circuit Simulation with Measurement-extracted
Performance for Modulation and Photodetection
S. Tenenbauma, L. Zanvettora, C. Finardib, A. Ponchetb and R. Panepuccib
a
FACTI - Fundação de Apoio a Capacitação em Tecnologia da Informação, Campinas, 13069 - 901
b
CTI – Centro de Tecnologia da Informação Renato Archer, Campinas, 13069 - 901
produced by Lumerical [5]. Fig.1 sketches the
transmitter (TX) and receiver (RX) building blocks.
As fundamental building blocks of the TX (Fig.1a)
we considered a pseudo-random bit sequence generator
(PRBS), a pulse generator set to non-return to zero
modulation (NRZ) format, the laser (in continuouswave configuration), an amplitude modulator and the
measured S-parameter matrix input element.
For the optical RX (Fig.1b), we considered as
building blocks the photodiode, an electrical low-pass
Bessel type filter (LPF) with cut-frequency at the 75%
of the bit-rate and a measured S-parameter input
element for the photodiode. Results were analysed with
the help of a bit-error rate tester with eye-diagram
function.
We considered the complete chain when TX and RX
were connected to generate what we expect to be the
result of an optical link. Additionally, S-parameters
were considered for the transimpedance amplifier
placed immediately after the photodiode.
1. Abstract
We report on the simulation and fast design of
integrated photonic-based structures that are considered
as technological core of the next-generation optical
transmitters and receivers. For a realistic electro-optical
response of the modulator and photodetector we
incorporate measured s-parameter data as a building
block of the transmission and receiver design.
2. Introduction
At chip design level it´s necessary to know in
advance the performance of every single component or
device to be included in the chip project in order to keep
it on the safe-side.
Today several simulation packages can provide the
theoretical models of the most important on-chip
devices and components. These softwares became a
fundamental tool to design photonic integrated circuits
(PICs) and are able to reproduce numerically what
should be expected as optical and electrical response of
the chip to be manufactured.
But once theoretical results and measurements are
ready to be compared they rarely match. The reason for
this mismatch is the fact that the theoretical tools do not
take into account all the imperfections coming from the
CMOS fabrication process, signal optical and electrical
noise and performance limitations of the on-chip
components and devices [1].
More and more PIC-based solutions are getting close
to become the technological core of the optical
subsystems in communication links. One of the most
complex building blocks is the one dedicated to the
modulation and photodetection functions [2-3].
Here we report on the fast design of an integrated
photonic transceiver where the modulator and
photodetector are designed together with the extraction
of S-parameters [4] obtained from experimental
measurements using a vector network analyser (VNA).
The results are analysed in terms of eye-diagrams and
bit-error rate. The results show that although the
simulations are based on a compact and simple model
the method can be used to represent the optical and
electrical response of complex on-chip structures.
Fig.1. Building blocks for the (a) transmitter and (b) receiver.
2. Results
A. Transmitter
Once the binary word is defined, the pulse generator
creates the waveform that drives the modulator to
finally get NRZ format in the optical domain. The onchip modulator is a ring resonator-based modulator able
to set the amplitude of light by changing the
transmission spectrum of the ring [2]. A p-n junction
electrically polarized to inject and extract carriers into
the waveguide modulates the refractive index of the
ring. Fig.2a sketches the modulator built on the chip.
The S-parameters extracted from measurements can
be placed between the pulse generator and the optical
modulator. Once it’s there concatenated as a new
element block (Fig.1), NRZ waveform becomes “preshaped” by the s-parameters element before driving the
modulator. The s-element building block effectively
imposes all the data features from the ring-modulator
measured onto the signal.
2. Method
The software package we used as tool for the chipscale opto-electronic circuit analysis is the Interconnect
37
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
C. Complete Chain
The complete chain includes extracted-data for the
modulator, photodiode and transimpedance amplifier
(TIA) at the post-detection stage [5]. To compare it to
the ideal scenario we analysed the performance of the
complete chain at the same bit-rate (25Gbps). Fig.4
shows the eye-diagrams for both. Although eye-opening
is still observed for the full-extracted s-parameter
system (Fig.4b), the associated bit-error rate (BER) is
rigorously zero for the ideal simulation (fig.4a) but
decreases to ~10-11 for the data-extracted approach.
The data-parameterized system performs worse as
all the on-chip component characteristics is brought to
system design through the experimental measurement.
Fig.2. On-chip (a) Modulator and (b) Photodiode.
In Fig.3 we show the difference in the eye diagram
when the extracted-data is considered. Laser was tuned
to 1550nm and the bit-rate was set to 25Gbps which is
the bandwidth limit of the ring-modulator where 40ps
duration-time is expected. The RX for this calculation is
supposed to be ideal (no s-parameters).
Fig.2. Eye-diagram comparison for the simulated (a) ideal
and (b) data-extracted modulators.
Fig.4. Eye-diagrams for (a) ideal and (b) data-extracted
scenarios.
We can observe that the eye becomes noisy when
experimental data is considered. The fluctuation on the
upper portion of the eye-diagram typically reveals the
presence of noise and a non-ideal transfer function for
the modulation function. No LPF was considered for the
eye-diagrams to show eye-distortion clearly.
4. Conclusions
We have shown a fast and accurate method where
measured data are inserted in the simulation setup as
extracted s-parameters that impose onto the signal the
transfer function and noise levels obtained from those
on-chip components intended to be analysed. With this
technique we can improve the simulation element
library for the PIC design making it more reliable and
able to anticipate the component performance.
B. Receiver
The RX building blocks circuit converts the received
light into an electrical waveform that recovers exactly
the initial binary sequence if transmission is error-free.
Fig.1b shows the building blocks for the RX. Like the
TX, the on-chip PIN photodiode extracted s-parameters
can be implemented in the simulation setup to make
both behave equally.
In Fig.3 we show the difference in the eye diagram
when the extracted-data is considered. Laser was tuned
to 1550nm and bit-rate was set to 25Gbps. The TX for
this calculation is supposed to be ideal (no sparameters).
Acknowledgments
The authors would like to thank the technical staff
of CTI and CNPq. We would also like to thank SMART
Modular Technologies for the sponsorship of the lab
facilities.
References
[1] Q. Xu, V.R. Almeida, R. R. Panepucci, M. Lipson,
Experimental demonstration of guiding and confining light in
nanometer-size low-refractive-index material. Optics Letters,
v. 29, n.14, p. 1626, 2004.
[2] C. A. Barrios, V. Almeida, R. R. Panepucci, M. Lipson,
Electrooptic
modulation
of
silicon-on-insulator
submicrometer-size waveguide devices. Journal of Lightwave
Technology (Print), v. 21, n.10, p. 2332-2339, 2003.
[3] A. Novack, M. Gould, Y. Yang, Z. Xuan, M. Streshinsky,
Y. Liu, G. Capellini, A. E.-J. Lim, G.-Q. Lo, T. Baehr-Jones,
and M. Hochberg, "Germanium photodetector with 60 GHz
bandwidth using inductive gain peaking," Opt. Express 21,
28387-28393 (2013).
[4] Lumerical Solutions, Inc., “Interconnect,” [Online]:
http://www.lumerical.com/tcad-products/interconnect/
[5] A. Ponchet, E. Bastida, R. Panepucci, J. Swart and S.
Tenenbaum, SiGe HBT Mm-Wave DC Coupled Ultra-WideBand Low Noise Monolitic Amplifiers, Proceeding of the 27th
Symposium of Circuit Design, Aracaju-Brazil, SBCCI’ 2014.
Fig.3. Eye-diagram comparison for the simulated (a) ideal (b)
data-extracted photodiodes.
To better understand the effect of the s-parameters at
the RX, we have considered an ideal TX (with no
measured-data inclusion). As the S-matrix modifies the
electrical signal waveform, the LPF was temporarily
taken out, too, in order to analyse the s-parameters
effect in separately. As shown in Fig.3b, eye distortion
can be observed when experimental data is included.
38
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
Process and Electrical 3D Simulations of Fabricated FinFET using Brazilian
Facilities
M. A. Keilera, L. P. B. Limaa, M.V. Puydinger dos Santosa and J. A. Diniza
a
University of Campinas, School of Electrical and Computer Engineering and Center for Semiconductor Components,
P. O. Box 6101, 13083-970 Campinas-SP, Brazil
e-mail: [email protected]
the 3D structure and the electrical characteristics were
extracted from Atlas3D simulations.
The FinFET transistors were simulated on a SOI
(Silicon On Insulator) wafer with a Si (340 nm) and
SiO2 (400nm). Figure 1a shows the simulated SiNW
with 100 nm width, 340 nm height and 40µm length
defined on Devedit3D. A 10-nm-thick dry SiO2 and
300-nm-thick Al layers were used as gate hard mask for
phosphorus ion implantation process, with energy of 30
keV and dose 1016 cm-2. After this process, the Al hard
mask layer was removed. Figure 1b shows the doping
profile of the SiNW after ion implantation and rapid
thermal annealing (RTA) processes. After the RTA
process, the SiO2 layer was removed. For gate
dielectric, a 10-nm-thick dry SiO2 was used. 20-nmthick TiN and 200-nm-thick Al films were used as metal
gate electrode. For source and drain contacts, a 200-nmthick Al layers were used.
1. Abstract
This work present a FinFET (Fin Field Effect
Transistor) device simulation using TCAD Silvaco
software. This simulation was based on the FinFET
device fabricated entirely using Brazilian facilities.
Current-voltage curves were simulated and compared
with experimental results of threshold voltage (VT) and
transconductance (gm). As this FinFET was based on
silicon nanowire (SiNW) obtained by gallium Focused
Ion Beam (FIB), the experimental gm value presented
one order of magnitude lower than simulated result. So
this can be explained by the Ga incorporation into
SiNW during the silicon milling in FIB system. Thus
further simulations will be performed to investigate this
effect.
2. Introduction
3D MOSFET (Metal-Oxide-Semiconductor Field
Effect Transistor) devices, such as FinFET, recently
have gained much attention in nano-technology
industries. The basic advantage of using a FinFET
device is reduced short-channel effects and high output
resistance values [1-6]. Also, FinFET devices are
compatible with the CMOS fabrication process because
of the potential for using high-k dielectrics and metal
gate electrodes [4-6]. Due to their superior properties
including wear resistance, high conductivity, and
favorable melting point and mid-gap work function
values, titanium nitrite (TiN) films have been studied
extensively as gate electrodes in FinFETs and memory
devices for 20 nm technology nodes and beyond [1-6].
In this work, TiN films are used as gate electrodes
FinFETs. To fabricate the FinFET device, a focused ion
beam (FIB) system was used to etch Si on the gate area
in order to obtain width of 100 nm. SiO2 was used as the
gate dielectric, and 20 nm thick TiN and 200 nm thick
Al were used as metal gate, drain and source electrodes.
In addition, TCAD Silvaco simulation was performed
and the electrical characteristics of both devices were
compared.
Figure 1 - a) SiNW with 100 nm width, 340 nm height and
40µm length, and doping level on SiNW; b) 2D schematic
view of doping profile for source, gate and drain.
3. Simulation Details
The FinFET device simulations were performed
using TCAD SILVACO software. The simulation was
done following the fabrication process of the FinFET
reported by Lima et al [7]. Devedit3D was used to build
4. Results and Discussion
Figure 2 shows the schematic view of the simulated
FinFET device with Al/TiN/SiO2/Si as gate structure.
39
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
increases the doping concentration in channel region
[7]. Thus, the channel mobility value is decreased and
consequently, lower Ids, higher VT, lower gmmax and
higher Δgm/gmmax ratio values can be expected.
30µ
a)
Vgs = 2.0V
3µ
b)
Vgs = 2.0 V
Vgs = 1.8 V
Vgs = 1.8V
20µ
2µ
Ids [A]
Ids [A]
Imax = 3 A @ Vds = 2.0V
Imax = 26 A @ Vds = 2.0V
Vgs = 1.4V
10µ
Vgs = 1.4 V
1µ
Vgs = 1.0 V
Vgs = 1.0V
0
1
Vds [V]
2
0
3
0
1
Vds [V]
2
3
Figure 3 - Ids x Vds measurements from a) simulated and b)
fabricated FinFET devices.
a)
4µ
1
gm = 2.0 S
max
2
gm = 1.6 S
2µ
b)
200n
Vgs [V]
200n
100n
100n
VT = 0.5 V
0
1
2
max
gm = 60 nS
VT = 0.4 V
0
0
1
gm = 193 nS
gm [S]
1µ
2µ
Vgs [V]
0
Ids [A] @ V ds = 0.1 V
Vgs [V]
0
gm [S]
Drain-s source current (Ids) by drain-source voltage
(Vds) and Ids by gate-source voltage (Vgs) characteristics
of the simulated and fabricated FinFET are presented in
Figure 3 and 4, respectively.
From Figures 3a and 3b, both drain characteristics
(Ids x Vds) for simulated and fabricated FinFET,
respectively, indicate that the devices are working like a
nMOSFET transistor. For Vds = 2.0 V (saturation
region), the extracted Ids values were 28 µA and 3 µA.
From Figures 4a and 4b, the threshold voltage (VT)
value was extracted from gate characteristics (Ids x Vgs)
measurements (Figure 4), with drain-source (Vds)
voltage of 0.1 V (in triode region). The VT values of 0.4
V and 0.5 V were extracted from Ids x Vgs characteristics
of the simulated and fabricated devices, respectively [7],
and indicate a VT variation of 0.1 V. Furthermore, the
VT values of 0.4 V and 0.5 V correspond to a metal
(Al/TiN) work function value of 4.1 eV and 4.2 eV,
respectively, which are in good agreement with the
work function extracted from Al/TiN/SiO2/Si structure
used on the fabricated FinFET [7]. Also, those work
function values are suitable for nMOS applications. In
addition, Figures 4a and 4b show the transconductance
(gm) by gate-source voltage (Vgs) curves for simulated
and fabricated devices, respectively. The gm can be
extracted from Ids x Vgs measurements, since gm is the
relation between the channel current and the applied
gate voltage: gm=∂Ids/∂Vgs. The maximum gm (gmmax)
values of 2.0 μS and 193 nS were extracted. Also, the
gm values of 1.8 μS and 60 nS were extracted for high
electrical field condition at Vgs = 2 V. The extracted
Δgm/gmmax ratios of 0.10 and 0.69, where Δgm = gmmax gm , for both devices indicate the channel mobility
degradation at high electrical field condition.
Table I presents a summary of all electrical
parameters, which were extracted from current-voltage
curves (Figures 3 and 4) of both devices. Table I
shows:
i) The fabricated devices presented Ids value almost
one order of magnitude lower than the simulated
FinFET;
ii) VT variation of 0.1 V, and;
iii) The maximum Δgm/gmmax ratio of 0.69 for the
fabricated device indicates a high channel degradation.
In general, those results are related to the Ga
incorporation into SiNW during the fabrication process,
because of gallium is a silicon p-type dopant, which
0
Ids [A] @ V ds=0.1V
Figure 2 - Schematic view of the simulated FinFET device.
Vgs = 0.6 V
Vgs = 0.6V
0
2
0
0
1
2
Vgs [V]
Figure 4 - Ids x Vgs – gm x Ids measurements from a) simulated
and b) fabricated FinFET devices.
Table I - Summary of electrical parameters extracted from
simulated (Sim.) and fabricated (Fab.) current-voltage curves
(Figures 3 and 4).
Device
Sim.
Fab.
Ids @
Vds =
2.0 V
28 µA
3 µA
VT @
Vds =
0.1 V
0.4 V
0.5 V
gmmáx
gm @ Vgs =
2.0 V
2.0 µS
193 nS
1.8 µS
60 nS
*
Δgm/gmmax
0.10
0.69
Note: Δgm = gmmax - gm (for Vgs=2.0)
5. Conclusions
In conclusion, new simulations will be carried out to
investigate the Ga+ incorporation on SiNW on the
device electrical properties.
Acknowledgments
The authors would like to thank Center of
Semiconductor Components (CCS). The work is
supported by CNPq, CAPES, Poditrodi and
INCT/Namitec.
References
[1] Y. Liu et al, Jpn. J. Appl. Phys., 47, 4, 2433-2437 (2008).
[2] L.P.B. Lima et al, Microelectron. Eng., 92, 86-90 (2012).
[3] I. Polishchuk et al, IEEE Electr. Device L., 22 (9), 444 446 (2001).
[4] S.H. Hsu et al, IEDM2012, 525-528 (2012).
[5] G.S. Kar et al, IEDM2012, 17-20 (2012).
[6] T. Matsukawa et al, IEDM2012,175-178 (2012).
[7] L.P.B. Lima et al, J. Vac. Sci. Technol. B, 31, 5 (2013).
40
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
Study of Low-Field Mobility on SOI n-FinFETs with Standard and Rotated
Substrate Orientations
T. A. Ribeiroa and M. A. Pavanelloa
a
Centro Universitário da FEI
e-mail: [email protected], [email protected]
Abstract
3. Extraction Method
This work studies the low-field mobility on SOI nFinFETs with standard and 45º rotated substrates using
the Y-Function method that utilize a robust recursive
algorithm that accurately extract the mobility on several
FinFETs with different fin widths, and discuss the
influence of the different crystallographic orientation on
the mobility. It is observed that with the rotation of the
substrate the mobility increase compared to the standard
FinFETs, as well as with the reduction of fin width.
For the study of the low field mobility on both nFinFET structures with standard and rotated substrate
the extraction procedure chosen was the Y-FunctionBased methodology that utilize a robust recursive
algorithm that converge after few iterations and
accurately determine the carrier mobility [3]. The Y
function require only I-V curves for the extraction and
is given by (1) [4].
Y
1. Introduction
I DS
gm
(1)
Where IDS is the drain current and gm the
transconductance.
With the recursive algorithm, the error ε and the
current gain factor β given by (2) can be determinated
with a polynomial regression of ξ as shown in (3) that
fits well the experimental data. Moreover, with an initial
guess of VTH*, a rough estimate of the exact threshold
voltage value (VTH), the algorithm start and as it
converges the error ε tends to zero and the exact value
of VTH can be achieved and β can accurately be
extracted without the influence of the series resistance
[3]. Since the devices measured, have narrow fin width
and therefore increased series resistance.
Vertical device structures with multiple gates like
FinFETs can be fabricated on different surface
orientation depending on the direction of the fin on the
wafer. On a (100) substrate where the fin is parallel or
perpendicular to the wafer flat the top surface is (100)
while the sidewall surface is (110). But with a rotation
of 45º on the substrate the top and sidewalls orientation
becomes (100), as illustrated by Fig. 1 providing better
electric characteristics since electron mobility on (110)
plane is degraded compared with (100) [1, 2].
2. Characterization
WCOX 0
L

1
1  1
2
 2 

 2 

2
3
VDS VGT * VGT *
Y

VDS
VGT *  VG  VTH * 
2

The devices measured were triple gate SOI nFinFETs fabricated on IMEC on both standard and 45º
rotated substrate with 150nm buried oxide. Fin height
(Hfin) of 65nm and Equivalent Oxide Thickness of 2nm.
There is no channel doping keeping the p-type doping
of the order of 1015. Each device consists of 5 parallel
fins. The devices were measured using the
characterization system Keithley 4200SCS with long
integration time.
(2)
(3)
(4)
Where VGT* is the gate voltage overdrive, VDS is the
drain voltage, Θ2 evaluate the θ2 effect (surface
roughness) and ε is the error of the difference between
the estimated VTH and the exact value of VTH. W is the
channel width, L is the channel length and COX is the
dieletric capacitance and µ0 the low field mobility.
4. Experimental results
Using the extraction methodology explained above
applied to the IDS x VGS curves from Fig. 2 the low field
mobility for very long channel length as a function of
fin width (Wfin) can be extracted.
Fig.1. Schematic of FinFETs with standard substrate with
(110) sidewalls and rotated substrate with (100) sidewalls.
41
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
IDS [A]
55
to decrease as the fin width is increased and as the fin
width becomes larger the electron mobility from
standard and rotated devices approaches the same value.
That happens because the current conduction on the top
becomes more significant compared to the sidewalls
current conductions and the FinFET become quasiplanar as the Hfin<<Wfin.
On FinFETs fabricated on standard wafer as the fin
width decreases the current should be more significant
on the (110) sidewalls and consequently the degradation
of the electron mobility should be higher as a lower
mobility that increase with Wfin contrary to what was
extracted. However, this can be explained by assuming
that mobility is controlled by phonon scattering and as
fin width decreases, the phonon scattering is reduced
because of the interaction of the sidewalls inversion
layers in devices with smaller fin width [5].
Standard , L=1m
VDS=50mV
50
Wfin=20nm
45
Wfin=30nm
40
Wfin=40nm
35
Wfin=50nm
30
Wfin=70nm
25
Wfin=120nm
20
Wfin=370nm
15
Wfin=570nm
A
10
5
0
-5
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.0
1.2
VGS [V]
IDS [A]
55
Rotated, L=1m
VDS=50mV
50
Wfin= 20nm
45
Wfin= 30nm
40
Wfin= 40nm
35
Wfin= 50nm
30
Wfin= 70nm
25
Wfin= 120nm
20
Wfin= 370nm
15
Wfin= 570nm
April 9 - 10, 2015, São Bernardo do Campo
B
10
5
5. Conclusions
0
-5
0.0
0.2
0.4
0.6
0.8
In this paper, the low field mobility has been
extracted using a Y-Function based method with a
robust recursive algorithm for FinFETs with different
channel widths. This method is independent of series
resistance, and therefore does not influence the mobility
extracted. The mobility from these FinFETs show that
with small fin width the low field mobility is high and
as the width increases the mobility decrease due to
reduced phonon scattering and on rotated substrate the
mobility is higher than on standard substrates because of
different conduction planes on the sidewalls.
VGS [V]
Fig.2. Drain current as a function of the gate voltage for
FinFETs with channel length of 1µm for standard substrate
(A) and rotated substrate (B)
Fig. 3 shows that the mobility is higher as the fin
width is reduced. In addition, for rotated devices the
electron mobility is better as the majority of the current
goes though the sidewalls (100) plane compared to the
standard where the (110) sidewalls degrade the electron
mobility.
300
,
,
Standard
Rotated
Acknowledgments
VDS=50mV
260
L= 1m
2
Electron Mobility [cm /V.s]
280
The authors T. A. Ribeiro and M. A. Pavanello
would like to acknowledge the research-funding agency
CNPq for the financial support. They also acknowledge
Dr. João Martino (USP) and Dr. Cor Claeys (IMEC) for
providing the measured samples.
240
220
200
180
160
10
100
1000
References
W [nm]
Fig.3. Mobility extracted as a function of Wfin for long channel
length (L=1µm), symbols are the experimental data and lines
are the mean curve of these values.
[1] Colinge, J.P. FinFETs and Other Multi-Gate Transistors.
Springer, p. 218, 2008.
[2] Pavanello, M.A.; Souza, M.; Martino, J.A.; Simoen, E.;
Claeys, C. Analysis of temperature variation influence on the
analog performance of 45° rotated triple-gate nMuGFETs.
Solid-State Electronics, v. 70, p. 39-43, Apr. 2012.
[3] Fleury, D.; Cros, A.; Brut, H.; Ghibaudo, G. New Yfunction-based methodology for accurate extraction of
electrical parameters on nano-scaled MOSFETs. IEEE
International Conference on Microelectronic Test
Structures, 2008. ICMTS 2008, p.160-165, Mar. 2008.
[4] Ghibaudo G. New method for the extraction of MOSFET
parameters. IEEE Eletronics Letters, v. 24, p. 543-545, Apr.
1988.
[5] Rudenko, T.; Kilchytska, V.; Collaert, N.; Jurczak, M.;
Nazarov, A.; Flandre, D. Carrier Mobility in Undoped TripleGate FinFET Structures and Limitations of Its Description in
Terms of Top and Sidewall Channel Mobilities. IEEE
Transactions on Electron Devices, v. 55, n. 12, p. 35323541, Dec. 2008.
250
230
2
Electron Mobility [cm /V.s]
240
220
210
Standard, L=3µm
Standard, L=5µm
Rotated, L=3µm
Rotated, L=5µm
200
190
VDS=50mV
180
20
25
30
35
40
45
50
W [nm]
Fig.4. Mobility Extracted as a function of Wfin for long
channel length (L=3µm and L=5µm).
From Fig. 3 and Fig. 4, we can see that for different
channels lengths the low field mobility has a tendency
42
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
Behavior of Irradiated MOSFETs submitted to
Thermal Annealing
K. H.Cirne1,F. G. Leite1, N. H. Medina2, R. B. B. Santos1 , M. A. G. da Silveira1
1
Centro Universitário FEI, São Bernardo do Campo, Brazil.
Instituto de Física, Universidade de São Paulo, São Paulo, Brazil.
[email protected], [email protected]
2
Two different experiments were performed. In the
first experiment, with rapid thermal treatment, the
device has been exposed to 3 successive doses of
radiation, and its electrical parameters were measured
right after each irradiation stage. Following each stage,
the IC was heated in a FANEM 520 stove during a
period of 1 hour after a cumulative dose of 100 krad
and during 2 hours after a cumulative dose of 250 krad.
After the final stage of irradiation, having accumulated
a total dose of 500 krad, the device remained in the
stove for 2 hours. In the second experiment, with the
usual slow thermal treatment, the device received a total
dose of 500 krad in a single irradiation session, and it
was mantained at 100°C during 168 hours (1 week). The
IC was characterized after each stage of thermal
treatment and also 1 week after the irradiation process.
1. Abstract
Electronic devices exposed to radiation suffer
degradation on their electrical characteristics which can
be recovered by thermal treatment. .The aim of this
work is to characterize MOSFETs and analyze the
behavior of thermal annealing processes, in order to
understand the temperature effects in the electrical
parameters of irradiated circuits.
2. Introduction
Electronic devices are composed by many
components, such as MOSFETs (Metal Oxide
Semiconductor Field Effect Transistor). When a voltage
is applied trhough the gate, charges are attracted to the
channel between source and drain terminals, which
allows an electric current to flow when another voltage
is applied between source and drain.. When MOSFETs
are exposed to ionizing radiation, there is a variation in
the mobility of its electrons and holes, which directly
affects their electrical conductivity. After exposure to
ionizing radiation, charges begin to accumulate at the
semiconductor oxides and interfaces, in what is called
Total Ionizing Dose (TID) [2]. With the build up of
charges typical of TID, changes in the threshold voltage
of the device may be noticeable. Techniques such as
thermal annealing treatment [3] are used to recover the
original electronic behavior,. This technique involves
heating the components to 100oC temperature during a
fixed time interval , which may result in the recovery of
the device initial electrical conditions [4]..
Fig. 1. Detail of the XRD-7000 Difractometer of the Centro
Universitário da FEI.
4. Results
For the first experiment with the rapid thermal
treatment, Fig 2 presents the resulting IDxVGS transistor
characteristics curves. Threshold voltages before and
after the rapid thermal annealing processes are
presented in Table 1. After thermal treatment, the
threshold voltage almost returned to its pre-radiation
value for n-MOSFET. In this case, energy provided to
the trapped charges in the devices oxides and interfaces
increased the rate of recombination, accelerating
recovery. However, on p-MOSFETs the damage due to
irradiation could not be recovered with thermal
annealing. In fact, thermal annealing even worsened the
parametric degradation.
3. Experiment
In order to assess the behavior of irradiated
MOSFETs after thermal annealing, the IC CD4007,
which is composed of 3 n-MOS and 3 p-MOS
transistors, was tested on different conditions. The
X-ray irradiation procedures were performed with a
Shimadzu XRD-7000 Difractometer, with a 96 rad/s
dose rate. The electrical parameters of the transistors
were characterized with an Agilent HP 4156C
semiconductor parameter analyzer. The device was
characterized previously in order to record the device
behavior without radiation degradation.
43
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
Fig.3 - IDSxVGS curves for an accumulated dose of 500 krad
and after 1 week of thermal annealing
Fig.2 - IDSxVGS curves for different accumulated doses and
thermal annealing periods.
Table 2- Threshold Voltage for an accumulated dose of 500
krad and after 1 week of thermal annealing.
Table 1- Threshold Voltage for different accumulated doses
and thermal annealing periods.
Threshold Voltage (V)
Threshold Voltage (V)
N type
Accumulated
Room
Dose (krad)
Temperature
Pre radiation
Before
After
168
Thermal
Thermal
hours
Annealing
Annealing
later
1.480
100
0.780
0.415
1.085
1.105
250
0.400
1.165
1.325
1.315
500
0.980
0.650
1.155
1.200
Room
Dose (krad)
Temperature
Pre radiation
Before
After
168
Thermal
Thermal
hours
Annealing
Annealing
later
-2,815
-3,005
-3,150
-3,035
250
-3,690
-2,980
-3,970
-3,970
500
-4,100
-3,800
-5,000
-5,025
Pre rad
1.480
-1.310
After 500 krad
1.200
-5.025
After treatment
1.030
-3.545
168 hours later
1.030
-3.545
4. Conclusions
N-MOS transistors have a better response to thermal
annealing. The electrical parameters were almost
restored to their pristine values, which means oxide
trapped holes were almost removed or at least
compensated. However, the same result was not
observed for p-MOS transistors. In this case, thermal
annealing was not effective and this treatment even
worsened the threshold voltage of the p-type transistor.
The experiment after 1 week of thermal annealing
recovered some of the threshold voltage of the
transistors. On n-MOS, the threshold voltage reached a
lower value than its pristine value
-1,310
100
P type
.
P type
Accumulated
N type
ACKNOWLEDGEMTS
For the slow thermal treatment with a single stage of
irradiation experiment, Fig 3 presents the resulting
IDxVGS transistor characteristics curves. Threshold
voltages before and after the thermal annealing process
are presented in Table 2. This time, for the n-MOSFET,
threshold voltage shift was much less important than the
shifts observed in the first experiment, with 3 stages of
irradiation followed by rapid thermal treatment.
However, the usual slow thermal treatment appears to
have caused a small further degradation in the threshold
voltage. Although the slow thermal treatment reduced
the degradation in the p-MOSFET case, the resulting
threshold voltage was still very far from the normal
operational values.
This work was supported by Centro Universitário da
FEI and PROJETO CITAR. The authors would like to
thank Luis Eduardo Seixas for discussions and
contribution to thhis research.
REFERENCES
[1] M. BOSCHERINI et al., “Radiation damage of
electronic components in space environment”, Nucl.
Inst. and Met. Res. A, 514, pp. 112-116,2003
[2] T. COUSINS et. al., Defense Research
Establishment Ottawa, report NO. 1030, 1990.
[3]. P. V. DRESSENDORFER, Basic Mechanisms for
the New Millennium, Proc.
[4] US DEPARTMENT OF DEFENSE. Test Method
Standard – Microcircuits – MIL-STD 883E.
Washington: DoD, 1997.
44
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
Analysis of Common-Source Current Mirrors Implemented with Asymmetric
Self-Cascode and Graded-Channel SOI nMOSFETs
R. Assaltia and M. de Souzaa
a
Centro Universitário da FEI
e-mail: [email protected], [email protected]
The S-SC transistor presents both channel regions with
doping concentration of 6×1016 cm-3, whereas in the A-SC
device, MD features 1×1015 cm-3 in its channel region.
(A)
(C)
1. Abstract
This paper presents a comparison of the performance
of asymmetric self-cascode and graded-channel, both
fully depleted SOI nMOSFET structures, in commonsource current mirrors, through experimental results and
two-dimensional numerical simulations. The figures of
merit studied were the mirroring precision, output
resistance and output swing, showing the benefits of
these structures over the uniformly doped and
symmetric self-cascode structures.
(B)
2. Introduction
The self-cascode SOI MOSFET configuration
(hereinafter called symmetric self-cascode (S-SC)) is
composed by two transistors associated in series with
short-circuited gates, and it is extensively discussed as a
way of improving the analog characteristics of MOS
transistors [1]. Recently, it has been proposed the
asymmetric self-cascode (A-SC) structure shown in Fig.
1(A). In this figure, LS and LD are the channel lengths of
individual transistors near the source and the drain,
respectively. The total channel length (L) is given by L S
+ LD. In this configuration, the transistor near the drain
(MD) presents reduced doping concentration in
comparison to the transistor near the source (M S) [2].
This structure is similar to the Graded-Channel (GC)
SOI nMOSFET transistor (Fig. 1(B)), where the channel
has an asymmetrical doping profile of acceptor
impurities in the channel [3]. In Fig. 1(B), LHD and LLD
are the lengths of highly and lightly doped regions,
respectively. Both A-SC and GC structures have shown
improvements on the analog characteristics at transistor
level [2,4,5]. Current mirrors (CM) constitute one of the
most important blocks for analog circuits [6]. In a CM,
the input current (IIN) is mirrored to the output branch,
ideally maintaining the output current (IOUT) constant,
regardless the output voltage (VOUT), i.e. with high
output resistance (ROUT). The mirroring precision
(IOUT/IIN) indicates how well IIN is mirrored to IOUT. Fig.
1(C) presents the current mirror in common-source
configuration formed by SC structures.
Fig.1. Schematic cross-section of A-SC (A) and GC (B) SOI
nMOSFETs. C: Common-source CM using SC configuration.
4. Experimental Results
As the input and output transistors of CMs present
the same W and L, the mirroring precision should be
theoretically equals to one. Fig. 2(A) shows the
(IOUT/IIN) curves as a function of IIN with VIN=VOUT, as a
way to determine the intrinsic mismatching between the
transistors that compose the CM. The A-SC LS=1µm
and LD=3µm has exhibited significant intrinsic
mismatching due to the reduction of the channel length
of MS. The minimum intrinsic mismatching has been
observed to conventional SOI and S-SC CMs. Fig. 2(B)
presents the (IOUT/IIN) curves as a function of IIN
measured at VOUT=1.5V. It is possible to note that the
A-SC LS=3µm and LD=1µm and A-SC LS=LD=2µm
presented the best mirroring precision, which is related
to the improved output conductance (gD) and reduced
impact ionization, which diminishes IOUT dependence on
bias variation. Fig. 2(C) exhibits the IOUT(VOUT) curves
measured at IIN=1µA. From these results, one can verify
that the A-SC CMs have great reliability in mirroring IIN
to IOUT in a wider range of VOUT comparing to S-SC and
conventional SOI CMs. However, the A-SC LS=1µm
and LD=3µm CM showed the worst behaviour among
the A-SC structures due to the larger intrinsic
mismatching. Another manner to evaluate how good the
current mirror is, lies on the analysis of output swing
(VOS) given by the difference between the breakdown
(BVDS) and the saturation (VSAT) voltages. These
parameters have been extracted from Fig. 2(C) and are
exhibited in Table I. The A-SC CMs present the largest
VOS mainly due to the increase of BVDS. Fig. 2(D)
shows the output resistance (ROUT=1/gD) as a function of
IIN with VOUT=1.1V, extracted from IOUT(VOUT) curves.
The improvement of gD is the reason why A-SC CMs
3. Device Characteristics
The CMs with self-cascode transistors analysed in
this work were fabricated in a fully depleted SOI
technology from UCLouvain, Belgium [7]. These CMs
were implemented with conventional SOI and SC SOI
structures, varying LS and LD lengths, maintaining L
equals to 4µm and with channel width (W) of 20µm.
The gate oxide (Toxf), silicon film (TSi) and buried oxide
(Toxb) thicknesses are 31, 80 and 390nm, respectively.
45
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
comparison to A-SC LS=1µm and LD=2µm (GC
LHD=1µm and LLD=2µm). For all configurations with
identical LD/L (LLD/L) relations, it has been noticed a
better mirroring precision for the GC CM. Fig. 3 shows
IOUT as a function of VOUT changing LD (LLD) with LS
(LHD) fixed at 2µm (C), and changing LS (LHD) with LD
(LLD) constant at 2µm (D), extracted at IIN=1µA. It has
been observed an improvement in mirroring I IN to the
output branch with the rise of LS (or LHD) in comparison
to the increment of LD (or LLD), which is related to the
better mirroring precision. ROUT for GC LHD=1µm and
LLD=2µm is 3 times the ROUT for A-SC LS=1µm and
LD=2µm, extracted at VOUT=1.5V. Besides that, VOS is
similar between the GC and A-SC CMs.
present the highest ROUT.
Table I. Output swing, VSAT and BVDS for different CMs.
Current Mirrors
Conv. SOI L=4μm
A-SC LS= 3μm; LD=1μm
A-SC LS= 2μm; LD=2μm
A-SC LS= 1μm; LD=3μm
S-SC LS= 2μm; LD=2μm
VSAT [V]
0.14
0.12
0.10
0.47
0.13
1.6
1.15
Conventional SOI L=4m
S-SC - LS=2m; LD=2m
A
A-SC - LS=2m; LD=2m
A-SC - LS=1m; LD=3m
1.3
IOUT/IIN
1.2
1.00
B
1.1
1.0
0.95
0.90
1E-8
2.5
VIN=VOUT
1E-7
1E-6
1E-5
IIN [A]
1E-4
0.9
1E-3
VOUT=1.5V
0.8
1E-8
1E-7
1E-6
1E-5
IIN [A]
1E-4
1.10
1E-3
1.4
1.05
9
IOUT [A]
A-SC - LS=2m; LD=2m
A-SC - LS=2m; LD=2m
A-SC - LS=1m; LD=3m
ROUT []
1.5
0.95
A-SC - LS=3m; LD=1m
8
10
A-SC - LS=1m; LD=3m
0.90
0.85
7
10
1.0
0.80
D
A-SC LD=1m
A-SC LD=2m
A-SC LD=3m
A-SC LD=4m
A-SC LD=5m
GC LLD=1m
GC LLD=2m
GC LLD=3m
GC LLD=4m
GC LLD=5m
VOUT=1.5V
0.75
10
IIN=1A
0.5
C
0.70
1E-8
VOUT=1.1V
0.0
0.5
1.0
1.5
VOUT
[V]
2.0
2.5
3.0
1E-6
1E-5
IIN [A]
1E-4
1E-6
1E-5
0.9
1E-8
1E-4
B
1E-6
1E-5
1E-4
IIN/(W/L) [A]
1.0
0.9
LS=LHD=2m
0.7
IOUT [A]
1E-7
1.1
IIN=1A
0.8
0.6
A-SC LD=2m
0.5
A-SC LD=3m
0.4
A-SC LD=5m
C
0.8
IIN=1A
0.7
LD=LLD=2m
0.6
A-SC LS=1m
0.5
A-SC LS=2m
GC LLD=2m
0.3
GC LLD=3m
0.2
0.1
GC LLD=4m
0.1
0.0
0.0
0.5
1.0
1.5
VOUT [V]
2.0
2.5
3.0
A-SC LS=5m
0.4
0.2
0.3
In order to make a comparison between the A-SC
and GC CMs and evaluate the influence of LS, LD, LHD
and LLD lengths in the CM performance, twodimensional numerical simulations have been
performed with technological parameters similar to the
experimental devices, using Sentaurus Device software
[8]. The simulations present the advantage of
eliminating the intrinsic mismatching. Fig. 3 shows the
mirroring precision as a function of I IN/(W/L) varying
LD (LLD) with LS (LHD) fixed at 2µm (A), and varying LS
(LHD) with LD (LLD) constant at 2µm (B), extracted at
VOUT=1.5V. As one can see, the increase of LD (or LLD)
has shown small influence in the mirroring precision,
improving it in the moderate inversion. For example, at
IIN/(W/L)=20nA, a maximum difference of 1% (0.3%)
in the mirroring precision has been observed among the
A-SC CMs (GC CMs). Analysing Fig. 3(A) and
comparing the devices which offer the best performance
among the A-SC and GC CMs, it has been noticed, at
IIN/(W/L)=20nA, an improvement of 2% in the
mirroring precision for the GC CM in reason of the
lower series resistance (RS) of GC transistors, since the
A-SC structure presents an intermediate N+ region
between the source and drain of self-cascode
configuration. On the other hand, from Fig. 3(B), it has
been noted a significant improvement in the mirroring
precision with the increase of LS (or LHD), especially in
moderate inversion, indicating that the behaviour of the
input and output transistors of A-SC structure (GC) is
governed by MS transistor (highly doped region). At
IIN/(W/L)=20nA, an improvement of 24% (10%) has
been verified in the mirroring precision for A-SC
LS=5µm and LD=2µm (GC LHD=5µm and LLD=2µm) in
LD=LLD=2m
1.0
IIN/(W/L) [A]
0.9
5. Two-Dimensional Numerical Simulations
GC LHD=5m
VOUT=1.5V
1.1
1.0
Fig.2. A: (IOUT/IIN) vs IIN for VOUT=VIN. B: (IOUT/IIN) vs IIN for
VOUT=1.5V. C: IOUT vs VOUT for IIN=1µA. D: ROUT vs IIN for
VOUT=1.1V.
GC LHD=1m
1.2
1.1
5
10
0.0
1E-7
A-SC LS=3m
A-SC LS=5m
A
LS=LHD=2m
6
A-SC LS=1m
GC LHD=3m
1.00
IOUT/IIN
A-SC - LS=3m; LD=1m
2.0
1.3
Conventional SOI L=4m
S-SC - LS=2m; LD=2m
IOUT/IIN
10
Conventional SOI L=4m
S-SC - LS=2m; LD=2m
IOUT [A]
IOUT/IIN
A-SC - LS=1m; LD=3m
A-SC - LS=3m; LD=1m
1.4
A-SC - LS=2m; LD=2m
VOS [V]
1.26
> 2.88
> 2.90
1.83
1.16
Conventional SOI L=4m
S-SC - LS=2m; LD=2m
1.5
A-SC - LS=3m; LD=1m
1.10
1.05
BVDS [V]
1.40
> 3.00
> 3.00
2.30
1.29
April 9 - 10, 2015, São Bernardo do Campo
0.0
0.0
D
GC LHD=1m
GC LHD=2m
GC LHD=5m
0.5
1.0
1.5
VOUT [V]
2.0
2.5
3.0
Fig.3. A: (IOUT/IIN) vs IIN/(W/L) varying LD (LLD) with LS (LHD)
fixed at 2µm. B: (IOUT/IIN) vs IIN/(W/L) changing LS (LHD) with
LD (LLD) fixed at 2µm. C: IOUT vs VOUT varying LD (LLD) with LS
(LHD) constant at 2µm. D: IOUT vs VOUT changing LS (LHD) with
LD (LLD) constant at 2µm.
6. Conclusions
This work compared the performance of A-SC and
GC current mirrors in common-source architecture.
Experimental results showed that the A-SC structures
promotes an increase of ROUT and VOS, and better
mirroring precision in comparison with S-SC and
conventional SOI CMs, which is related to the reduced
gD and higher BVDS. By simulations, it has been
observed higher ROUT and better mirroring precision for
GC CM in comparison to A-SC CM, which is related to
the lower RS of GC transistors.
Acknowledgments
To FAPESP and CNPQ for the financial support.
References
[1] Galup-Montoro, C. et al. IEEE JSSC, v. 29, n. 9, p. 10941101, 1994.
[2] Souza, M. de et al. 8th ICCDCS, 2012.
[3] Pavanello, M.A. et al. SSE, v. 44, p. 917-922, 2000.
[4] Pavanello, M.A. et al. SSE, v. 44, p. 1219-1222, 2000.
[5] Souza, M. de et al. IEEE International SOI Conference,
2011.
[6] Laker, K.R, Sansen, W.M.C. Design of analog integrated
circuits and systems. McGraw-Hill, 1994.
[7] Flandre, D. et al. Solid-State Electronics, v. 45, p. 541-549,
2001.
[8] Sentaurus Device User Guide, Version C-2009.06, 2009.
46
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
Effects of High Temperature on the Harmonic Distortion of the Asymmetric
Self-Cascode of SOI nMOSFETs
L. M. d’Oliveira, R. T. Doria and M. de Souza
Centro Universitário da FEI
e-mail: [email protected]
it operates in strong inversion and is saturated when the
gate bias reaches the threshold voltage of MS. As a
result, MD will work as an extension of the drain [4]
and the effective channel length of the structure will be
close to MS. The benefits provided by this structure are
an improved output conductance, as well as the voltage
gain and breakthrough voltage [4].
One important analog parameter that must be
analysed is the harmonic distortion of a device. It
quantifies the non-linearities inherently present on MOS
transistors, as the relation between the input signal at the
gate and the output signal at the drain is not linear, adding
several harmonics additional to the fundamental [5]. This
work will focus on the harmonic of second order (HD2),
which is the main harmonic that will affect the total
harmonic distortion the most, and the harmonic of third
order (HD3), which is the first odd harmonic and can be
very significant depending on the application [6].
The study of the effects of the temperature on the
behaviour of the devices is important for several
applications, since it is not only very influent on most of
its characteristics, but also is a factor common in several
applications, from control systems of a car to sensors for
nuclear energy generation. Therefore, this work intends
to perform a study of the high temperature effects on the
A-SC association harmonic distortion.
1. Abstract
This work aims to perform an analysis of the effect of
the high temperature on the harmonic distortion of fully
depleted SOI nMOSFETs, associated in an asymmetric
self-cascode. The experimental results show a
dependence of the behaviour with the temperature and the
devices bias, higher temperatures providing worse results
at lower gm/IDS, while it provided better harmonic
distortion at higher gm/IDS. The results at 500K were
degraded due the critical temperature being reached.
2. Introduction
Although the SOI technology improves several
aspects of the analog behaviour of conventional
nMOSFETs, such as mobility, capacitance coupling and
integration scale [1], there is still room for
improvement, especially when analysing the output
conductance (gD) of the devices. Due to its dependence
on the channel modulation effect [1], which is more
significant the shorter the channel is, a higher g D is
obtained in longer devices, reflecting on a better voltage
gain (AV). Still, other analog parameters, such as the
unit gain frequency (fT), are degraded with longer
channel devices.
A way to approach this problem is with the
Symmetric Self-Cascode [2], composed by a series
association of transistors of shorter channels, connected
by their gates and therefore working as one single
device, as displayed on Fig. 1. Since the charges of the
channel controlled by the drain when the device
operates in saturation are limited to the transistor where
the drain bias is applied (MD), the transistor near the
source (MS) is able to provide a good output swing,
better than what could be obtained with single devices,
without compromising fT as much [3].
3. Device Characteristics and Methodology
The A-SC association used in this work are
composed by transistors fabricated at Université
Catholique de Louvan-la-Neuve (UCLouvain) [7] of
size ranging from 0.75 μm and 6 μm, with channel
doping concentrations of 1015 cm-3 for MD and 6×1016
cm-3 for MS.
The results for the harmonic distortion were
obtained by applying the Integral Function Method
(IFM) [8] on the extracted DC characteristic curves,
such as the drain current as a function of gate bias and
the drain current as a function of the drain bias. The
results obtained for the transconductance, output
conductance and voltage gain for these devices are
presented at reference [9].
Fig.1.Schematic of a self-cascode association.
4. Experimental Results
To further improve gD, ref. [4] proposes to keep the
channel of MD with the natural wafer doping
concentration , in order to lower the high electric field
near the drain. This structure is known as the
Asymmetric Self-Cascode (A-SC). The channel of MS
is kept standardly doped to avoid lowering of the
threshold voltage (VT). Since MD presents negative VT,
The results for the second and third order harmonic
distortions as a function of the gm/IDS ratio, for the A-SC
composed by SOI nMOSFETs of channel length of
0.75μm, with a constant input signal amplitude (Va) of
50 mV and drain bias (VDS) of 1.5 V, are displayed on
47
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
Fig. 2 (A) and (B).
the polarization applied to the device. It can be seen on
(a) that HD2 is higher with the temperature at lower
gm/IDS, but there is a cross point between 3 V-1 and 4 V-1,
and the higher HD2 will be found at smaller
temperatures. It is interesting to notice that, although
HD2 at 450K is about 15 dB better than the other
temperatures after this point, the results of 500K are
worsened and mix with the rest of the temperatures. As
the temperature increase and there is a higher carrier
concentration, the maximum depletion thickness
decreases and a fully depleted SOI device can start to
work as a partially depleted one. This is due the critical
temperature for this technology being reached [10],
causing this degradation.
-20 (A)
HD2 [dB]
-40
VDS = 1.5 V
-60
LMS = LMD = 0.75 m
-80
Va = 50 mV
0
5
10
gm/IDS [V-1]
Temperaturas
300 K
350 K
400 K
450 K
500 K
15
20
-40 LMS = LMD = 0,75 m
HD3 [dB]
-60
Temperaturas
300 K
350 K
400 K
VDS = 1,5 V
450 K
Va = 50 mV
500 K
-80
-100
-120
(B)
-140
0
5
10
gm/IDS [V-1]
15
5. Conclusions
This work provided an analysis of the second and
third order harmonics obtained from asymmetric selfcascodes of fully depleted SOI nMOSFETs. The results
were obtained from experimental DC characterizations
by applying the IFM, considering constant input signal
amplitude. The results showed high (worse) HD values
for high temperatures depending on the bias applied.
For the normalized results, which provide a more clear
way to notice the effects of the temperature on HD2 and
HD3, it could be seen that there is a degradation at
500K, due to the critical temperature being reached.
20
Fig.2.Harmonic distortion of second (A) and third (B) order
as a function of gm/IDS for different temperatures.
The negative peak observed at HD2 is a result of the
inflexion point of the drain current, marking the
transition between the saturation and triode operation
regimen. Since the IFM calculates HD by applying a
polynomial approximation, there are maximum and
minimum peaks that are transferred to HD3 in the form
of negative peaks. Although some conclusions can be
taken from the fact that the two highest temperatures
present shifted HD curves in comparison to the others, a
better analysis is made if the harmonics of second and
third order are normalized by the voltage gain. The
results are exhibited at Fig. 3.
HD2 /AV[dB]
Acknowledgements
The authors of this work would like to thank CAPES
for the financial support and Prof. Denis Flandre, for
supplying the devices.
References
[1] J. P. Colinge, “Silicon-On-Insulator Technology: Materials to
VLSI”. 3rd ed. Massachusetts: Kluwer Academic Publishers, 2004.
[2] M. Gao et al. Solid-State Electronics, v.35, p.505-512, 1992.
[3] A. Gerosa and A. Neviani, Electronics Letters, v.39, n.8, p.6389, 2003.
[4] M. de Souza, D. Flandre and M. A. Pavanello. Proceedings of
the IEEE International SOI Conference, 2011.
[5] J. E. França and Y. Tsividis, “Design of Analog-Digital VLSI
Circuits for Telecommunications and Signal Processing”. Prentice
Hall, 1994.
[6] G. Groenewold and W. J. Lubbers. IEEE Transactions on
Circuits and Systems II: Analog and Digital Signal Processing, v.
41, p. 569-580, 1994.
[7] D. Flandre. Solid-State Electronics, v. 45, p. 541-549, 2001.
[8] A. Cerdeira et al. Solid-State Electronics, v. 48, p. 2225-2234,
2004.
[9] L. M. d’Oliveira, M. A. Pavanello, D. Flandre and M. de Souza.
SBMicro, 2014.
[10] M. Galeti, M. A. Pavanello and J. A. Martino. Microelectronic
Journal, v. 37, p. 601-607, 2006.
450 K
500 K
Temperaturas
300 K
350 K
400 K
-70 (A)
-80
VDS = 1,5 V
-90 Va = 50 mV
LMS = LMD = 0,75 m
0
HD3 /Av [dB]
-100
2
4
6
8
gm/IDS [V-1]
10
12
14
LMS = LMD = 0,75 m
(B)
-120
-140
Temperaturas
300 K
350 K
400 K
-160 V = 1,5 V
DS
Va = 50 mV
-180
0
2
4
6
8
gm/IDS [V-1]
10
450 K
500 K
12
April 9 - 10, 2015, São Bernardo do Campo
14
Fig.3.Harmonic distortion of second (A) and third (B) order
normalized by AV as a function of gm/IDS for different
temperatures.
One can notice that the results for both harmonics
have behaviour with the temperature that is dependent to
48
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
Drain Current Analysis in Planar MOS Magnetic Field Sensor with Asymmetric
Contacts
R.A.Silvaa, A.L.Perina,b and R.C.Giacominia
Department of Electrical Enginnering, Centro Universitário da Fei, S.B do Campo, Brazil
b
College of Exact Sciences and Technology, Universidade Metodista de São Paulo, S.B do Campo, Brazil
e-mail: [email protected]; [email protected]; [email protected]
a
The Lorenz force changes the carrier density distribution to
the channel sides, which leads to a potential difference known
as Hall effect [3,5].
1. Abstract
This work analyses the drain current behavior under the
influence of a magnetic field, which is perpendicular to the
drain current direction and to the channel plane, for devices
with different dimensions of drain and source extensions. The
magnetic field applied to the device drive a force, called the
Lorentz force, which causes variation in the distribution of
current density, changing the path of carriers and thereby
altering the concentration in the region between the contacts
(drain/source). This effect causes variations in drain current
when exposed to different directions and intensities of
magnetic fields.
3. Methods and Materials
The characteristics of measured devices are the following:
channel length(L) of 21.0 µm, channel width (W) of 12.6
µm, gate oxide thickness of 13.8 nm, substrate type p with
concentration of 6x1016 cm-3and source/drain n type
concentration of 1020 cm-3, source/drain extension length (Ext)
of 7.0 µm, 10.0 µm and 14.0 µm. The transistors topology is
shown in Fig. 2.
2. Introduction
The MOSFET (Metal-Oxide-Semiconductor Field-EffectTransistor) have pulled the development of the electronics
industry [1,2] so new applications became possible, bringing
with them new environmental operating conditions. An
applied magnetic field in a direction different of electrical
current direction in a conductive medium, such as silicon,
generates a force perpendicular to both directions and
proportional to the magnetic field intensity and the average
electron drift and can be expressed as in (1) in its scalar form.
There resultant force is known as Lorentz force (FL). Some
devices use this effect to operate as sensors [3,4].
𝐹𝐿 = 𝑞. 𝑣𝑑 . 𝐵. 𝑠𝑖𝑛 ∅
Fig.2. 3D view of the measured NMOS transistor.
(1)
The nMOS transistors were built through the MOSIS
Educational Project with the foundry AMI05 (0.35 µm)
ON Semiconductor and an instance is shown in Fig. 3.
where: q is the elementary electron charge (1.6x1019C), vd is
average electron drift velocity, B is the magnetic field
intensity, sin ∅ is the sin of the angle between the directions of
vd and B.
In a planar MOSFET, the magnetic field perpendicular to
both, the channel plane and the drain current, generates the
Lorentz force in a direction parallel to the channel plane and
perpendicular to the drain current direction, as shown in Fig. 1,
which drives a variation in current density in the channel.
Fig.3. NMOS Transistor fabricatedby MOSIS project.
The measured devices were biased with 100 mV
between source and drain (VDS) and the gate voltage
(VGS) varying from 0 to 5.0 V. The magnetic field was
applied perpendicular to the transistor plane, so also
perpendicular to the drain current direction (x axis in
Fig.1. Variation in current density distribution due to Lorentz force.
49
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
centered, as is usual (Fig. 2). The asymmetrical shape
allows the average path covered by the drain current
differs depending on the direction of the magnetic field
applied and the highest concentration of current density
is at the side of the device next to the contacts.
Regarding the variation of the length of the source and
drain extension is noted that the current level decreases
as the length of the extension increases due to the
increased series resistance of the device, even with
differences in current levels as a function of the
magnetic field applied in both directions.
Fig. 2), with the following intensities: 100, 135 and 146
mT, positive and negative.
4. Results and Discussion
It was noticed that the absolute values of the magnetic
field intensity are barely different. This phenomenon
can be explained because of the hysteresis of the core
material used to induce the magnetic field. So, the
defined values are the average value of ten measures for
each level, as shown in Table 1.
Table 1. Average magnetic field and standard deviation used
to characterize the MOS devices.
Average Magnetic Field
(mT)
+146
+135
+100
-100
-125
-145
April 9 - 10, 2015, São Bernardo do Campo
5. Conclusion
It was noted that the applied magnetic field changes the
distribution of current density. This change increases the
average path traversed by electrical current, which on
the other hand, causes the decrease of the drain current
level. The variation of the average current path is not
symmetrical to the magnetic fields applied in positive
and negative directions because of the geometry of the
asymmetric transistor of the study. The positioning of
the contacts favors higher current density on one side of
the transistor. The magnetic field applied changed the
current drain levels for all transistors studied. Since the
current level undergo different changes depending on
the direction of the magnetic field applied to the device,
this device can be used in a differential circuit for
detecting the direction of the applied magnetic field.
The current intensity decreases with the increase in the
intensity of the magnetic field and also due to the
increased extension of the source and drain, the first
because it changes the distribution of the current density
and second because it increases the series resistance of
the device.
2(mT)
3,48
5,21
1,37
2,27
3,16
4,05
The drain current (ID) measurements were used to
verify the effects generated by the magnetic fields on
the transistors. There are small changes in drain current
induced the magnetic field intensities defined, even
though different extension dimensions.
As its intensity increases, the drain current decreases,
regardless of the direction, positive or negative, of the
magnetic field. In addition, the asymmetric positioning
of source and drain contacts contributes for major
decreases in drain current for negative values of
magnetic field. For negative values of the applied
magnetic field is found that the current level is lower
than for positive values as shown in Fig. 4.
6. Acknowledgements
The authors would like to thank the research-funding
agencies CAPES, CNPq and Centro Universitário da
FEI for the financial support, and the MOSIS Integrated
Circuit Fabrication Service for the fabricated devices.
7. References
[1] COLINGE, J. P. FinFETs and Other Multi-Gate Transistors. New
York: Springer, 2008.
[2]COLINGE, J. P. Silicon-On-Insulator Technology: Materials to
VLSI. 3ª Edição. ed. Boston: Kluwer Academic Publishers, 2004.
[3] REZENDE, Sergio Machado, Materiais e Dispositivos
Eletrônicos, 2º ed. Livraria da Física.
[4] BRATLAND, T.; CARUSO, J.M.; SCHNEIDER,W,R.;
ELETRONICS, N.; Tamara Bratland, Michael J. Caruso, Robert W.
Schneider, SMITG.H.C, A New Perspective on Magnetic Field
Sensing, December 1,1998.
[5] ETTELT, D.; REY, P.; JOURDAN, G.; 3D Magnetic Field
Sensor Concept for Use in Inertial Measurement Units (IMUs),
Journal of Microelectromechanical systems, vol.23, No.2, April 2014.
Fig. 4. Maximum values of drain current (IDMAX) as function of
magnetic field for different extension dimensions.
This behavior is due to the asymmetric geometry of the
transistor, since the region of source and drain contacts
are positioned near the side of the transistor and not
50
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
The influence of the mobility in JNT and FinFET devices with Self Heating
Effect
G. Mariniello and M. A. Pavanello
Departament of Electrical Engineering, Centro Universitário da FEI, São Bernardo do Campo, Brazil
e-mail: [email protected]; [email protected]
device alternatives can suffer from the difficulty of
dissipating the heating of the silicon film caused by the
Joule effect thanks to the current conduction, the socalled self-heating effect (SHE). This paper aims at
comparing the self-heating effects (SHE) between
FinFET and JNT focused on the behavior of the
mobility in devices using three-dimensional simulation.
1. Abstract
This paper aims at comparing the behavior of the
mobility in Junctionless Nanowire Transistors (JNT)
and FinFET devices with self-heating effects based on
three-dimensional numerical simulations. The results
show lower variation of the mobility and consequently,
lower SHE impact in JNT compared to FinFETs.
3. Devices Characteristics
2. Introduction
The comparison of SHE between JNT and FinFET
devices by means of three-dimensional numerical
simulations has been performed with Synopsys
Sentaurus Device simulator [10]. Both JNT and FinFET
devices have been simulated with gate oxide thickness
of 2nm, channel length (L) of 0.5 µm, fin width (Wfin) of
10 nm and fin height (Hfin) of 10nm. For the JNT P+
polysilicon was used as gate material. The JNT has been
doped uniformly with 2x1019 cm-3 with n-type
impurities, while the channel region of FinFET has been
doped with 1x1015 cm-3 with p-type impurities. In order
to avoid the series resistance, the drain and source
extensions were simulated with 5nm. The buried oxide
thickness is 100 nm. The simulations have been done
with isothermal grid at 300K where there is no selfheating effect (hereafter mentioned as without SHE) as
well as with thermal contact at the buried oxide
allowing the thermal generation to be accounted in the
several grid points (hereafter mentioned as with SHE).
Junctionless nanowire transistors (JNT) can be a
very interesting option once it avoids the lateral
diffusion of impurities from source and drain regions to
the channel. In addition, it facilitates the reduction of
the short channel effects. Also, as they are a multiple
gate devices it is possible to improve the electrostatic
control over the channel charges [1-4].
JNT have a uniform heavy concentration of donor
impurities from source to drain, which simplifies the
device fabrication, once it dispenses complicated
annealing techniques, while the channel in state-of-art
nFinFET devices is undoped or lightly doped with ptype impurities, n-type [5-6]. A schematic view and a
longitudinal-section of n-type JNT and FinFET devices
are shown on Fig. 1.
4. Results and Analysis
Fig.2 present the behavior of the drain current as a
function of gate voltage for FinFET and JNT. It is
possible to compare the simulations with and without
SHE, which present the same behavior i.e., there is no
clear SHE due to the lower VD (50mV) resulting in
lower static power (P = VD.ID). According to the results
obtained for lower VD, it is possible to confirm that
those simulations are calibrated for analysis with higher
VD values since their behavior are the same,
independently if accounting or not the silicon film
heating. On the other hand, when the VD increased to
1.5V, it is clearly visible the presence of the SHE in
both JNT and FinFET as the current with nonisothermal grid is smaller than with isothermal one,
thanks to the mobility degradation due to temperature
rise.
Fig.1. (a) A 3D view of a multiple gate device. (b) Longitudinal
section of FinFET device. (c) Longitudinal section of a JNT.
JNT and FinFET are made using Silicon-OnInsulator (SOI) substrates, as demonstrated in Fig. 1.
The thermal resistance associated to the buried oxide is
in order of 100 times larger than silicon. Thus, both
51
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
100
90
80
70
60
50
40
30
20
10
0
1E-6
Wfin=10nm;
Hfin=10nm;
1E-8
L=500nm;
tox=2nm;
1E-9
VD=50mV
1E-10
1E-11
FinFET (M=4,7V)
JNT (M=5,25V): ND=2.1019cm-3
1E-12
0.0
0.5
1.0
1.5
2.0
VG[V]
(a)
30
0.0
FinFET (M=4,7V)
ID[A]
JNT (M=5,25V): ND=2.1019cm-3
20
VD=1.5V
Center
Lateral
Wfin=10nm;
Hfin=10nm;
L=500nm;
tox=2nm
0.5
1.0
1.5
VG[V]
Symbol: With SHE
Line: Without SHE
Wfin=10nm;
10
Black: FinFET
Red: JNT (ND=2.1019cm-3)
e[cm2/(V.s)]
ID[A]
1E-7
April 9 - 10, 2015, São Bernardo do Campo
Fig.4. Δµe as a function of VG @ VD = 1.5V on JNT and
FinFET devices.
Hfin=10nm;
L=500nm;
tox=2nm;
VD=1.5V.
4. Conclusions
0
0.0
0.5
1.0
1.5
2.0
VG[V]
According to the results simulated, JNT suffer less
self-heating effect when compared with similar FinFET
devices due to the decreasing of the mobility variation
with temperature.
(b)
Fig.2. ID as function of VG for JNT and FinFET devices with
and without SHE in devices with Wfin=Hfin=10nm (a)VD =
50m.V (b)VD = 1.5V.
Acknowledgments
The authors acknowledge CAPES, FAPESP and
CNPq for the financial support.
The cause of the lower SH effect on JNT is
associated to the fact that, while the mobility in these
devices increases for higher VG values, FinFET devices
have the decrease of the mobility, according to the
graph present on Fig. 3. Also, according to Fig. 4, is
possible to see that the variation of the electron mobility
in isothermal and no isothermal grid is higher on
FinFETs than JNT devices.
e[cm2/(V.s)]
1800
1600
Wfin=10nm;
Hfin=10nm;
L=500nm;
tox=2nm.
500
Opened: Without SHE
Closed: With SHE
Center
Corner
450
400
1400
350
FinFET
1200
300
1000
250
800
200
600
400
150
VD=1.5V
100
JNT
200
0.0
[1] D. Hisamoto et al., IEEE Transactions on Electron
Devices, vol.47 , pp. 2320-2325, 2000.
[2] J. T. Park et al., IEEE Electron Device Letters, vol.22, pp.
405-406, 2001.
[3] J. P. Colinge et al., IEEE Electron Device Letters, vol.24,
pp. 515-517, 2003.
[4] J. P. Colinge et al., Proceeding of IEEE International SOI
Conference, pp. 1, 2009.
[5] C. W. Lee et al., Appl. Phys. Lett., vol. 94, no. 5, p. 053
511, Feb. 2009.
[6] J. P. Colinge et al., Nat. Nanotechnol., vol. 5, no. 3, pp.
225–229, Mar. 2010.
[7] G. Mariniello et al., Symposium on Microelectronics
Technology and Devices (SBMICRO) 2013 v.1 p1-4.
[8] A. Kranti et al., Solid-State Electronics, vol. 65-66, pp. 3337, Dec. 2011.
[9] S. Zimin et al., Proc. ICSICT, 1998, pp. 572-574.
[10] Sentaurus Device User’s Manual, Synopsys, 2013.
e[cm2/(V.s)]
2000
References
50
0.5
1.0
1.5
2.0
VG[V]
Fig.3. Center and lateral mobility as a function of VG @ VD =
1.5V on JNT and FinFET devices.
52
2.0
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
Project and Development of Submicron pMOSFET Junctionless Nanowire
Transistor
J. P. Nemer 1 and M. A. Pavanello1
1
Electrical Engineering Department, Centro Universitário da FEI – São Bernardo do Campo, Brazil
e-mail: [email protected] , [email protected]
By presenting more than one gate, JNT shows a
reduction of short channel effect. However, this device
provides a reduction in the subthreshold slope, low leakage
current, and a high ratio of current on/off [2]. The objective
of this work is to project and manufacture this transistor on a
SOI wafer with thickness of silicon layer equal to 14nm.
Despite of channel no present difference between the
doping concentration,wich facilitates the process, this project
is a major challenge regarding the small size of the silicone
film.
3. Devices Characteristics
1. Abstract
This work aims to project, fabricate and characterize a
transistor without juction (Junctionless Nanowire Transistor
- JNT) silicone-on-insulator technology (SOI-Silicon on
Insulator) with thin layer in Brazil. This transistor was
proposed because it has a simpler manufacturing process
than tradidicional CMOS, besides that several works in the
literature show JNT as a viable alternative to replace planar
transistors.
2. Introduction
Currently, a number of works reported in the world
literature point to the transistor without junction as an
importante replacement for planar transistors.The transistor
without junction Fig 1.This device presents a constant
doping concentration profile in the channel region, the drain
to source as shown in Fig.2, thus its manufacture becomes
simpler [1].
The SOI wafers used to manufacturing have the
following parameters: diameter of 300mm, thickness of
silicon film tSi=14 nm, buried oxide thickness toxb=20 nm.
To simulate this device we used the simulators: ATHENA
[3],ATLAS [4] by Silvaco and Sentaurus by Synopsys [5].
4. Results and Discussions
The process of manufacturing an integrated circuit
consisting of a series of steps which have been prepared in a
specific order . Below the steps that required greater attention
to be project are listed and presented in Fig.4. The sequence
of the JNT process has fewer steps when compared to SOI
MOSFET transistor due to ion implantation, since it has a
symmetrical profile in the drain to source channel, and thus
only one type impurity is implanted, simplifying the process
At first, it was used a p-type SOI wafer,with orietation
(100) for the manufacture of JNT deices. A chemical
cleaning is performed, and then the first deposition of SiO2,
used as sacrificial oxide to the first implantation. After
deposition the gallium implantation is performed. The graph
of dopant concetration as function os dose implantarion is
shown in Fig.3 in order to adjust the threshold voltage value.
To set a value of approximately VT=-0.5V was used dose=
2x1012 cm-2 and energy10KeV reaching Na= 1.5x1018cm-3.
Fig.1. – Schematic view of Nanowire Juncionless Transistor JNT
Fig.2 – Longitudinal section of transistor without junction JNT.
53
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
After the finalization of the device, DC characteristics
simulations were performed.. And as a result, curves of the
drain current and transconductance as a function of gate
voltage are shon in Fig.5. According to Fig. 5 it’s clear that
the projected transistor presented VTH=-0,5V and gmmáx=
0,89 µS .
1E20
)
Ga Concentration of JNT
Energy=10KeV
-3
Ga Concentration(cm
April 9 - 10, 2015, São Bernardo do Campo
1E19
1E18
Junctionless Transistor
0.6
1E17 1E12
1E13
1E14
0.5
1.0
L=0.5m toxf=7nm Hfin=10nm 0.9
VDS=50mV
0.8
0.7
-2
IDS(A)
0.4
Then the first mask is used to define the active region
of the device, as shown in Fig.4-A . In order to get 7 nm gate
oxide , it should take into account the thickness os silicon
film, 14nm, SiO2 is about twice the volume of Si , then
oxidation process consumes much silicon. Thus, the
oxidation time was set at 15min at 850ºC. The polysilicon
deposition and gate photolithography are performed and
presented in Fig.4-B. Then an oxidation is performed to
passivate the junctions and SiO2 is deposited in order to
increase the thickness of the insulating oxide on the
source/drain regions and gate. Contacts cuts made,
metalization applied and etched using the last metal mask
are presented in Fig 4-C.
After that in Fig. 4-D and F are presented the thermal
annealing of Al-Si contacts, and passivation of the SiO2/Si
interfaces and therefore the finished structure.
0.6
0.5
0.3
0.4
0.2
gm(S)
) dose as function of
Fig 3 – Simulated curve ofDose(cm
implantation
Gallium concentration in the channel , with energy 10KeV.
0.3
0.2
0.1
0.1
0.0
0.0
-1.4 -1.3 -1.2 -1.1 -1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0 0.1
VGF(V)
Fig.5 – JNT curves of the drain current and transconductance as
function of gate voltage with L=0,5µm and VDS=50mV.
4. Conclusions
This work proposed a project of a JNT
pMOSFET transistor to be manufactured in Brazil.
Simulations were performed for each step of the process
besides that temperature and time parameters were defined
for oxidation equal to toxf=7nm and tSi= 10nm. As well as
implantation dose to the channel region with gallium doping
to achieve VT= -0,5V. Finally simulations were done in
order to present DC characteristics as maximum
transconductance egual to gmmáx= 0,89 µS.
Acknowledgments
J.P.Nemer and M. A. Pavanello acknowledge
FAPESP, CNPq and CAPES for the financial support.
References
[1] COLINGE, J. P. et al. Junctionless Nanowire Transistor (JNT):
Properties and design guidelines. Solid-State Electronics, v. 65, p.
33-37, 2011.
[2] COLINGE, J. P. et al. SOI Gated Resistor: CMOS without
Junctions. IEEE SOI Conference Proceedings, 1-2, 2009.
[3] ATHENA User’s Manual, SILVACO Inc., 2010.
[4] ATLAS User’s Manual, SILVACO Inc., 2011.
[5] SENTAURUS Process User's Manual. SYNOPSYS, 2010.
Fig 4 – Figures simulated in Sentaurus. A- active region; BGate defined; C- SiO2 deposition and contacts definition; DMetalization; E- Longituginal section of final device.
54
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
Study of the Low-frequency noise in Submicron Graded-Channel Silicon on
Insulator nMOSFETS at room temperature
A. R. Molto, R. T. Doria, M. de Souza and M. A. Pavanello
Department of Electrical Engineering, Centro Universitário da FEI, Av. Humberto de Alencar Castelo Branco, 3972,
CEP 09850-901 São Bernardo do Campo, Brazil
e-mail: [email protected], [email protected], [email protected], [email protected]
1/f γ noise at high temperatures[5].
Abstract
This paper deals with the Low-frequency
noise behavior in Submicron GC SOI MOSFETs
fabricated using the commercial FD SOI 150 nm
technology OKI Semiconductors working at room
temperature..
1. Introduction
SOI MOSFETs have been first proposed
by reducing the short channel effects existing in
traditional bulk MOSFETs. However, SOI
MOSFETs have a floating channel region that
originates several undesired parasitic bipolar
effects (PBEs), affecting the device performance.
Due to the high electric field at the drain, it was
been proposed and demonstrated the Graded
Channel SOI MOSFET [1], by having a lightly
doped region near to the drain, reducing the
electric field and minimizing the occurrence of
PBEs.
The 1/fγ and 1/f2 noise are the most
important figures of noise in a MOS transistor.
They occur at the device interface, due to some
imperfections at the oxide during the process and
can be described by equation (1) [ref.]:
S ID 
K F  gm 2
2
Cox
W  L  f
[5]
Figure 1.: Typical input-referred low-frequency noise voltage
spectrum (This Picture was extracted in [5]).
2. Device Structure and Measurements
Figure 2 presents the cross section of the
device used in the measurements, where toxf is the
front gate oxide thickness, tsi is the silicon
thickness, toxb is the buried oxide thickness. In this
case toxf = 2.5nm, tsi = 40nm, toxb = 145nm. The Pregion is the Lightly doped region (LD) and P+ is
the Highly doped region (HD) near to source. This
device has a channel length of L=500nm and
channel width of W=5um and the relation
LLD
L
 0.5 .
(1)
where, KF is an empirical process characteristic,
gm is the transcondutance, Cox is the gate
capacitance per unit of area, W and L are the
channel width and length, respectively.
These imperfections induce the electron
trapping and detrapping at interface that makes the
current level wave. At low-frequencies the noise
reaches the highest values.
At the figure 1 is possible to seen the 1/fγ
contribution at the frequencies spectrum. The
Lorentizians have relation to Generation and
Recombination noise and can been overcome the
Figure 2.: GC SOI Structure.
55
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
The first measure was the IDS x VGS and Gm x VGS
curve (figure 3), where it was used the Agilent
4156C (Precision Semiconductor Parameter
Analyzer).
Figure 5.: Current Spectral Density
4. Conclusions
Figure 3.: IDS x VGS and gm x VGS .
This work has the objective of measuring,
and verifying the GC submicron SOI Mosfet DC
characteristics and noise comportment.
The IDS x VGS and gm x VGS measured at
figure 3, was very similar with the device
simulated in a TCAD at [2].
In the figure 5 the noise Spectrum
describes a classical 1/fγ with γ nearly 0.6. The
spectrum current density from figure 6 shows a
good oxide characteristic as can see in [6] page 7.
With the curve above at the figure 3, it was
possible determinate the Threshold Voltage (Vth=
0.66V) and the subthreshold slope of S=76mV/dec.
2. Noise Measurements
For noise measurements it was used the set-up
bellow at Figure 4, where the Agilent 5156 was
used to bias the DUT (Device Under Test), the
LNA is a Low Noise Amplifier and the Agilent
4395A is a Spectrum Analyzer:
References
[1] M.A. Pavanello, J. A. Martino, V. Dessard, D. Flandre,
Sollid-State Electronics, 44, 2000, p. 1219, in press
[2] Rodrigo Trevisoli Doria, João Antonio Martino, Eddy
Simoen, Cor Claeys, Marcelo Antonio Pavanello, Lowfrequency noise of n-type triple gate FinFETs fabricated on
standard and 45 rotated substrates Solid-State Electronics, v.
90, p. 121-126, 2013, in press
[3] J.P. Nemer, M. de Souza, D. Flandre, and M. A. Pavanello,
Analog Behavior of Submicron Graded-Channel SOI
MOSFETs Varying the Channel Length, Doping
Concentration and Temperature.
[4] J.P. Nemer, M. de Souza, D. Flandre, and M. A. Pavanello,
Low Frequency Noise in Submicron Graded-Channel SOI
MOSFETS.
[5] Vicent Dessard, Benjamin Iñíguez, Stéphane Adriaensen,
and Denis Flandre, SOI n-MOSFET Low-Frequency Noise
Measurement and Modeling From Room Temperature Up to
250 oC, IEEE TRANSACTOINS ON ELECTRON DEVICES,
VOL. 49, NO. 7, JULY 2002.
[6] Chia-Yu Chen, Low Frequency Noise in Advanced MOS
Transistor, UC Berkeley EE298-12 Solid State Technology
and Device Seminar, 2010-11-19, page 7.
Figure 4.: Noise configuration Set-up
The GC SOI at the figure 4 was biased in
linear linear region with Id=790uA, Vg=800mV,
obtained a Vd ~ 25mV.
In figure 6, it was been obtained the noise
Spectral density, where is possible to seem the
Low-Frequency noise (LFN) as showed at figure 1.
56
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
MOS-Bipolar Pseudo-resistor Characterization – Circuit and Extraction
Method
P. L. Benkoa and R. C. Giacominib
a
b
Centro Universitário da FEI - IED
Centro Universitário da FEI - IED
e-mail: [email protected]
corresponding to a deeply sub-threshold operation.
Harrison [2] was one of the first researchers to use the
MOS-bipolar pseudo-resistor for Neural Recording
Amplifier and reported the difficulty to measure its
ohmic value, because the measured current was below
the limits of the instruments capabilities. Despite this
fact, several bio-amplifier solutions have been proposed
using the MOS-bipolar pseudo-resistor with different
technologies and circuit solutions, and ranging from 109
to 1016 Ω have been published, [3], [4] but no one
presents a method for the resistance evaluation. Other
works, [5] and [6], with focus on the pseudo-resistor
were published, for different technologies (1.5µm,
0.5µm, 0.18µm), showing that applications are still
being researched.
1. Abstract
A MOS-bipolar pseudo-resistor (MBPR) study, as
well as the circuit for its characterization, is presented.
This device is mainly useful for very-low-frequency
filter designs, like bio-amplifier circuits, because it can
reach very high ohmic resistance, providing high RC
constants. Due to such high values that can be reached
(≈1012Ω), the measurements must be made indirectly.
This paper presents a method, which allows the
evaluation of pseudo-resistor topologies, using a low
pass filter and two one-stage source-follower amplifiers.
The behavior was evaluated using, as reference, the 8HP
IBM 0.13µm PMOS technology, offered by MOSIS
multiuser program. The results were obtained using
circuits and parasitic elements extracted from the
implemented layout, using Mentor Graphics CalibreTM.
Simulations were performed using PSP 103.1 models on
EldoTM SPICE analog simulator and experimental
measured values were shown.
2. Curve Response
Initially, a study of the device behavior by SPICE
simulation with 8HP BiCMOS 0.13µm technology [7],
was performed using electrical parameters extracted
from layout through the CalibreTM software [8]. The
purpose of this step was to identify the range and best
regions of operation, with focus on linearity, high value
and voltage swing. Fig.3 shows the ID x VAB curve for
two pMOS transistors connected in one back-to-back
solution, Fig.2.
2. Introduction
The pseudo-resistor was introduced by T. Delbruck
in [1] as an "adaptive element". Delbruck explains that
its effective resistance is huge for small signals and
small for large signals. The pMOS-Bipolar pseudoresistor uses the transistor body connected to the source,
and the gate connected to the drain, acting like a pMOS
diode for positive Vsg and a BJT diode for negative
Vsg. Fig.1 shows the structure profile and the equivalent
circuits for these two bias conditions.
Source ID
B
pMOS
Emitter Fig.2. The pseudo-resistor in pMOS back-to-back.
Base Bulk Gate A
16p
Drain VSG<0 S N G P ID x VAB
LINEAR FIT
5p
D ID(A)
VSG>0 11p
Collector P Well -­‐ N P 0
-5p
-11p
Fig.1. Schematic of pseudo-resistor behavior when the
Vsg is positive or negative biased.
-16p
-100m
Indeed, the MOS transistor configured as pseudoresistor, presents very low current for |ΔVds|< 0.1Volts,
-50m
0
50m
100m
VAB(V)
Fig.3. The pseudo-resistor curve response.
157
SEMINATEC 2015 - X Workshop on Semiconductors and Micro & Nanotechnology
April 9 - 10, 2015, São Bernardo do Campo
The red line represents the linear fit. It is possible
to see the linear tendency of the drain current behavior
in the ±100mV drain voltage range, with a residual sum
of squares about 10-23A2 of magnitude, and standard
error of about 10-13Ω-1 and linear intercept standard
error of about 10-14A.
capacitance of the transistor M4. The total capacitance
value obtained (370fF), by (1), was used to evaluate the
MOS pseudo-resistor, with 1x, 2x and 3x back-to-back
transistors circuit, with several width (W) and length (L)
channels. Were performed practical measurements,
exhibited on table 1.
3. Resistance Evaluation Circuit
4. Experimental results
Due to the high values involved, the evaluation of
the obtained resistances must be made indirectly.
Therefore, a low pass first order filter is proposed to
make the evaluation by the transient response. To
achieve external impedance isolation, the low pass filter
is assembled between source follower amplifiers with
voltage gain close to unit, Fig.4.
Table I. Simulation SPICE and practical results
W
L
Back-to-back
Practical
(µm)
(µm)
(TΩ)
Transistors
1
0.36
0.24
1.73
2
0.36
0.24
2.07
3
0.36
0.24
3.73
1
0.72
0.48
0.48
2
0.72
0.48
1,14
3
0.72
0.48
1,96
1
1.08
0.72
----2
1.08
0.72
0,73
3
1.08
0.72
1,10
4. Conclusions
A new method for the pMOS pseudo-resistor
evaluation was proposed. The measured values were
successfully obtained and showed an effective way to
evaluate the pseudo-resistor ohmic value. This method
can help in designs using this circuit topology.
Fig.4. Circuit for pseudo-resistor evaluation.
One step of 100mVpp (V2) is added to a DC bias
polarization (V1), and the voltage Vo(t) by the time
response, allows to find the pseudo-resistor value, once
that, the total capacitance on the M4 gate is knowledge
(370fF). Fig.5 exhibits the detail.
Acknowledgments
The authors would like to thank the financial support
provided by research agency FAPESP and Centro
Universitário da FEI.
References
[1] T. Delbrück and C. A. Mead, “Analog VLSI adaptive,
logarithmic widedynamic-range photoreceptor,” in Proc. IEEE
Int. Symp. Circuits and Systems, vol. 4, 1994, pp. 339–342.
[2] R. R. Harrison and C. Charles. “A Low-Power, Low-Noise
CMOS Amplifier for Neural Recording Applications” – IEEE
Journal of Solid State Circuits, Vol. 38 No. 6 June, 2003.
[3] J. Parthasarathy, A. G. Erdman, A. D. Redish, and B. Ziaie
“A Integrated CMOS Bio-potential amplifier with a feedforward DC cancellation Topology” - EMBS Annual
International Conference- Procedings of 28thIEEE, Aug 30 to
September, 2006.
[4] B. Gosselin, M. Sawan and C. A. Chapman. “A Low
Power Integrated Bio-potential Amplifier With Active Low
Frequency Suppressor” –IEEE Transactions, vol 1, NO. 3
September 2007.
[5]H. Kassiri, K. Abdelhalim, R. Genov. “Low-distortion
Super-Gohm Subthreshold-MOS Resistors for CMOS Neural
Amplifiers”. IEEE Biomedical Circuits and Systems,
Rotterdam, 2013.
[6] C.C. Tu, T.H. Lin. “Measurement and Parameter
Characterization of Pseudo-Resistor Based CCIA for
Biomedical Applications”. International Symposium on
Bioelectronics and Bioinformatics- IEEE ISBB 2014.
[7] BiCMOS8HP Design Manual, IBM Corporation, 2013.
[8]Calibre xRC™ User’s Manual, Mentor Graphics
Corporation, 2014.
Fig.5. Detail of the voltage on terminal 3 (Vo) of Fig.4.
Equation (1) gives the pseudo-resistor (Rp) value, by
output voltage data from transient response on circuit,
Fig. 4, terminal 3 (Vo).
∆!
𝑅𝑝 =
!∙!"
!!"#$ !!!"#$
(1)
!!"#$ !!"(!)
The calibration was performed by the evaluation of
the SPICE circuit parameters, extracted from the circuit
layout implementation by CALIBRE on PSP 103.1
models, replacing the MOS pseudo-resistor by a
resistance Rp=125KΩ to perform the total input
58
SEMINATEC 2015
Author Index
Author Index
Abrantes, A.
Alandia, B´
arbara
Assalti, Rafael
7
29
45
Bastida, Ezio
Batista, Jo˜
ao
Bortolucci, E.
B´eron, Fanny
3
23
7
17
Cabezas, D.P.
Cassiano, M.M.
Christiano, Verˆ
onica
Cirne, Karlheinz
D’Oliveira, L´ıgia
de Souza, Michelly
de Souza, R.V.
Diniz, J. A.
Diniz, Jose A.
Diniz, Jos´e
Doria, Rodrigo
Doria, Rodrigo T.
Dos Santos, M. V. P.
Dos Santos, Sebasti˜
ao
Emeri Jr., Jair Lins De
Fernandes, L.
Fernandes, L.O.T.
Finardi, C´elio
Finco, Saulo
Fino, Leonardo
Flandre, Denis
Fonseca, Leonardo R. C.
G. Dos Santos Filho, Sebasti˜
ao
Giacomini, Renato
Gimenez, Salvador
Guazzelli Da Silveira, Marcilei Aparecida
Hidalgo Ramirez, R.F.
Kaufmann, P.
Keiler, M. A.
Kudaka, A.
Kudaka, A.S.
1, 19
1
15, 29
43
47
45, 47, 55
1
39
5
17
47
55
39
29
35
7
1
37
35
33
23, 33
5
17
21, 23, 25, 49
9, 33
31, 33, 43
1
1, 7, 19
39
7
1
SEMINATEC 2015
Leite, Felipe
Lima, L. P. B.
Lima, Lucas
Machado, N.
Manera, L.T.
Marcon, R.
Mariniello, Genaro
Martucci, Renan
Mayer, Rafael
Medina, Nilberto
Molto, Allan
Moshkalev, Stanislav
Navarenho de Souza, Rafael
Nemer, Juliana
Novo, Carla
O. Silva, Danilo
Panepucci, Roberto
Pascon, Aline M.
Pavanello, Marcelo Antonio
Paz, Bruna
Perin, Andr´e
Pirota, Kleber
Ponchet, Andre
Ponchet, Andr´e
Puydinger Dos Santos, Marcos Vinicius
Renaux, Christian
Ribeiro, Thales Augusto
Rodrigues Da Silva, Ana Neilde
Rufino, F.C.
S. N. Pereira, Arianne
Santos, Roberto Baginski Batista
Saraiva Gomes, Dem´etrius
Silva, Cecilia C. C.
Silva, Rodrigo
Silveira, Marcilei
Souza, Jair F.
Souza, R.V.
Swart, Jacobus
Author Index
31, 43
39
17
7
19
1, 7
51
11
17
43
55
17
9
53
23, 25
21
2 37
5
27, 41, 51, 53, 55
27
49
17
3
37
17
33
41
13
7
21
31, 43
13
5
49
9
5
19
3
Telles, Antonio
Tenenbaum, Stefan
35
37
Zanvettor, Leandro
Zapata Lusni, Renato
37
25
SEMINATEC 2015
Keyword Index
Keyword Index
30 THz continuum
30 THz telescope
3D Simulation
1
1
39
astable multivibrator
Asymmetric Self-Cascode
Asymmetric Self-Cascode SOI nMOSFET
asymmetric transistor
37
47
45
49
bias
31
capacitor less
chemical vapour deposition (CVD)
CMOS
Common-Source Current Mirrors
11
5
31
45
dark
deep depletion
DEPAMBBRE efects
dfc
dielectrophoretic manipulation
double gate
23
29
33
11
17
27
electrical characterization
Electrical characterization
electrospinning
15
17
13
field effect transistor (FET)
FinFET
FinFETs
Focused Ion Beam
Focused ion beam
freecap
Fully depleted silicon on insulator FDSOI
5
21, 39
41
39
17
11
33
Gate
Gated device
GC SOI MOSFET
Graded-Channel SOI nMOSFET
graphene
ground-based THz transmission
25
25
55
45
5
7
Harmonic Distortion
High Temperatures
47
47
SEMINATEC 2015
Image filtering
intrinsic
Intrinsic concentration
junctionless
Junctionless
ldo regulator
leakage current
Lorentz Force
Low Noise Amplifiers
low voltage
low-field Mobility
Magnetic Field Sensor
membranes
Mirroring Precision
Mobility
MOS capacitor
MOS tunnel diodes
MOSFET
MOSFETs
Keyword Index
19
23
25
27
51, 53
11
29
49
3
35
41
49
13
45
21, 51
15
15, 29
53
42
nanofibers
Nanowire
Nanowires
Noise
13
53
17
55
Octagonal layout style
Off-State Leakage Current
Optical Receivers
Optical Transmission
Output Resistance
Output Swing
33
9
3
37
45
45
Photodiode
photodiode
Photonic-Integrated-Circuit Design
Photosensor
PIN
power conversion
25
23
37
25
25
37
Radiation
radiation effects
Retrieve weak THz sources
rotated substrates
9, 43
31
19
41
SEMINATEC 2015
S-parameters
Self Heating
sensors
short channel
Simulation
SOI MOSFET
Solar flare radiation
Solar flares
TCAD Simulation
temperature
Thermal Annealing
thin oxide
thin silicon oxynitrides
THz continuum detectors
THz imaging
THz telescope
TID
Total ionizing dose
Total Ionizing Dose (TID)
Transimpedance Amplifiers
triple gate
Keyword Index
37
51
13
27
21
55
1
7
39
23
43
29
15
7
19
7
9, 31
9
33
3
27
Wave layout
Weak sources
Wide band Amplifiers
9
19
3
Y-Function
41