Simulation and Debugging Techniques in Vivado IP Integrator
This Tutorial will demonstrate how to create a custom pulse IP that can be used to reset the
Microblaze via Software in Vivado by utilising the IP packager. This IP will then be simulated using
the VSIM simulator. The IP will be added to a Microblaze design, and exported to SDK. In SDK, a
simple application will be created that will reset the Microblaze via the pulse IP. This whole system
will be again simulated. We shall then add an ILA to the pulse IP and preform a cross trigger
debugging using the SDK application. Finally, this will be run on Hardware.
Requirements:
This tutorial requires at least Vivado 2014.4. For hardware test, a KC705 is needed. However, the
board is only needed for the last two steps.
Note: There is a Zip file that accompanies this tutorial. Please download this first before continuing.
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Step 1: Create the Pulse IP.
First we need to create a mechanism to reset the Microblaze. Here, we need a reset pulse that we
can control. To achieve this, we can use a simple counter in HDL that when enabled will toggle the
pulse, count to 16 ticks, toggle again. The HDL code is seen below on the right, and the
corresponding wave diagram on the left.
This IP will sit between the mb_reset on the reset IP, and a generated pulse from the GPIO. These
two reset’s, are OR’ed together. This will allow the Microblaze to be reset as normal via the reset IP,
and will allow the user the ability to reset via the software.
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To create the pulse_ip, open Vivado, right click on Design Sources -> Add Sources. Select Add, and
navigate to the pulse_ip_hdl folder and add all the sources here.
Once the HDL is added, select Tools -> Create and Package New IP. Select Package your current
project:
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Select an IP location. Select “my_ip” in the project directory. This will create a my_ip folder and
place the newly created IP into this folder. Select Include IP generated files:
Select Finish to exit:
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In the Package IP GUI, select Ports and Interfaces. Here, you will see a list of all the interfaces for
your IP. We will be setting the POLARITY of the reset to Active High to match our HDL code. To do
this, right click on the signal_reset -> Edit Interface:
Under the Parameters tab, change the Value to ACTIVE_HIGH:
Repeat this for all the reset signals (inp, and outp)
Once you are happy with the settings, select Review and Package -> Package IP
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Step 2: Simulate the newly created IP
Here, we will be creating a Testbench to test our newly created pulse IP. To add/create the
Testbench right click on Simulation Sources -> Add Sources:
Navigate to the pulse_ip_testbench folder and add the Testbench.
The Testbench sets up the clocks, and the reset, and will simulate a reset on the mb_reset, and an
input pulse.
Once the Testbench is added, run the simulation. The results will look something similar to below:
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Step3: Create Microblaze system
Now that the pulse IP is created and verified in step 1, and 2. We can now proceed to create the
Microblaze system In Vivado IP Integrator. To create the Microblaze system, follow the steps below:
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Create BD (IP Integrator -> Create Block Design), and name it “mb_system”
Add Microblaze from IP Catalog
o Run Block Automation
 Increase Local memory from 8KB to 32KB
 Double Click on Microblaze, and Enable Trace Bus Interface
Run Connection Automation
o Connect the Clock, and Reset
Add AXI GPIO from IP catalog
o Double Click on AXI GPIO
 Under the IP Configuration -> GPIO
 Tick All Outputs
 GPIO Width = 1
o Run Block Automation -> S_AXI
o Un-tick the GPIO box
Add AXI UART
o Run Block Automation
Add Pulse IP
Make the connections as shown below:
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Step 4: Create application
Once the HW is built in step 3, we can now export to SDK. Firstly, we need to Generate the output
Products, and Generate HDL wrapper:
The Export to SDK, File ->Export Hardware -> OK:
File -> Launch SDK
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In SDK, create a hello world application that we can use as a base application
File -> New -> Application Project
Select the Hello World Template:
Click Finish to continue
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Open the helloworld.c file, and modify it with the code below. This simple code will initialise the
GPIO output to 0. In the soft_reset function, the GPIO is set to 1. Also, the Microblaze is placed in
sleep.
Navigate to the application folder to reference the code below.
Note: The print is commented out here, as we shall be simulating this. In the HW test, this will be readded
Once the application is built (the SDK will build automatically. If not, go to project -> build all)
Exit SDK
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Step 5: Build test application
Add the ELF created in step 4 to the Vivado project simulation sources. To Associate the ELF, right
click on the ELF -> Associate ELF files…
Add the mb_sys_reset.elf as the associated ELF for the simulation Microblaze
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Next, we will be creating a Testbench for the top level. Right click on the simulation sources, and add
a new Testbench. This is similar to how this was done in step 2.
Navigate to the top_level_testbench folder and add the Testbench.
Once the testbench is created, you need to set this as top module. To do this, right click on the
Testbench -> Set as Top
Run Simulation
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Let’s investigate…
What should happen?
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Application code should be executing
This will set GPIO to 0, then 1
The GPIO input is fed into the inp_pulse port on the pulse IP
Once a input is detected on the inp_pulse this will cause a 16 tick pulse
inp_reset is fed to the mb_reset on the proc reset IP
pulse and inp_reset are OR’ed together
Is this what we are seeing in the simulation?
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If we zoom in on the Trace port, we can see that the code is executing on the Microblaze after
coming out of reset. We can verify the code by opening the ELF in SDK:
The GPIO goes to 1, then back to 0. The application is effectively looping as it is continuously getting
reset. This GPIO set to 1 is creating a pulse on the pulse IP, and it is this that is resetting the
Microblaze.
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Step 6: Cross trigger debugging
Here, we shall use the Vivado logic analyser, and the SDK software debugger to perform a cross tool
debugging. We will be debugging the pulse IP to verify that the system is working as expected.
To add a net for debug, open the block design, and mark the outp_reset net. To do this, highlight the
net -> right click -> Mark Debug
You will see a green bug symbol on the net:
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Validate the Design, Generate Output Products, and synthesise the design. Once this is completed,
open the syntheses design.
Here, we shall be adding the ILA Core. Open the Debug Layout in the drop down in Vivado:
In the Debug window, you will see a list of nets in Unassigned Debug nets folder. These nets
correspond to the various signals that make up the interface connection that you marked for debug
(in our case the outp_reset):
Use the Set up Debug wizard to add the ILA debug core to the design. Here, the unassigned nets will
be assigned and connected to the ILA.
Click on the Set Up Debug wizard:
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This will launch the GUI.
Select Next to Continue.
Verify that the Clock Domain is set. This will be set to undefined if not set.
Select Next to Continue.
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Select Next to continue.
Verify the summary, and select Finish to Exit:
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Here, you will see that the ILA core has been added. Save the project.
Save the project. This will update the XDC file with the commands to add and configure the ILA.
Now that the debug logic has been added, we can continue to implement the project (Generate
Bitstream)
Once the bitstream is complete, Re-export to SDK. This time tick the “Include Bitstream” box
We will be using the same application that was created in step 5.
Configure the FPGA. Xilinx Tools -> Program FPGA -> Program
Highlight the application under Project Explorer and right click -> Debug As -> Debug Configurations.
Double click on Xilinx C/C++ application (System Debugger) to create a debug configuration. Select
Debug to continue. This will open the debug perspective.
By default, the debugger will place a breakpoint at main().
Return to Vivado, without exiting the SDK in debug perspective. In the Flow Navigator in Vivado,
under the Program -> Open Hardware Manager -> Open Target -> Open New Target to open the GUI.
Select Next -> Finish to continue.
This procedure will open a logic analyser waveform window and initialise the analyser triggering
mechanisms.
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Select the Hardware window and select the hw_ila_1 core:
Note: the Status of the ILA core is Idle
In the Debug Probes window, select the outp_reset and drag and drop this into the Basic Trigger
Setup window. Set the Compare Value to 1. Also, set the Trigger position to be in the middle of the
1024 sample window by setting this to 512:
Finally, arm the ILA core by select the Run Trigger in the hardware window:
Note: the Status of the ILA core is Waiting
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Go back to SDK, without closing the hardware manager. In the debug perspective which is still at the
breakpoint at main. In SDK, we have a list of options:
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Step to
Step Over
Step into
Resume
Use the step over
step into
icon until we reach the software_reset function. Once we reach this, use the
icon to step into this function:
Once, we are at the line highlighted above, use the step over
icon. This will set the GPIO to 1,
and will cause the outp_reset to go to 1. Once this is done, you will see the trigger was hit in Vivado:
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Step 7: Testing on hardware
We have verified both the IP, and how this IP operated in the Microblaze system in the previous
steps. It is now time to test on Hardware.
We should still have the FPGA configured from the last step. However, if not go to Xilinx Tools ->
Program FPGA -> Program.
Highlight the application under Project Explorer and right click -> Run As -> Run Configurations.
Open a serial console, and set the BAUD to 9600.
Double click on Xilinx C/C++ application (System Debugger) to create a run configuration. Select Run
to continue.
You will see the print statement “We expect and endless loop…” printed on the console.
This is expected, as we are constantly resetting the Microblaze, which will re-run the app, which will
reset, ect..
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