1. No category

How to add a Netlist as a submodule into ISE.
The recommended to flow to adding submodules into ISE is to add the XPS
Submodule using the xmp file. The xmp file describes the location of the ucf file, the location
Of the implementation folder which contains the netlists and BMM file. Also, the xmp file may
contain application information (elf file) amongst other things. When adding the netlists, then all
these things have to be handled by the user.
To start off, we can generate the XPS project. For this example I chose the KC705 board. I used the
14.4 tools. I have used basic IP for simplicity:
© Copyright 2013 Xilinx
Once this is created create the Netlist. Hardware -> Generate List
The project directory should be populated as shown below:
© Copyright 2013 Xilinx
Next, create the ISE project with the settings below:
Next add the HDL top-level HDL file from the hdl folder in the XPS project directory:
© Copyright 2013 Xilinx
Select the system_stub.vhd:
© Copyright 2013 Xilinx
Next, add all the netlists. To do this we can simply source the directory where all the netlist are
contained. To do this right click in Synthesis in ISE:
Here, the SD option can point to the implementation folder:
© Copyright 2013 Xilinx
Now we can link to the BMM file. To do this right click on Implement Design and select Process
Properties:
Then add the –bm switch to point to the BMM file as shown below:
© Copyright 2013 Xilinx
Finally, the UCF file is added as a source file. This UCF file is contained in the data folder in the XPS
project directory.
The UCF file assumes that the XPS is the top level so the user will have to add the added hierarchy.
I have simply added a wildcard here for ease of use:
NET "*/CLK" TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 200000 kHz;
Once this is all done, the user can generate the bitstream.
© Copyright 2013 Xilinx