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Design, Simulation and Measurement
Ben Chia of Signal Integrity
The Importance
Signal Integrity Consultant
GRL Company Confidential
Power Integrity Measurement Demo
Overview
• Introduction of power distribution network
• Power noise sources and data patterns
• Power noise measurements in time
domain and frequency domain
• Power plane impedance measurements
• latest on-chip power noise measurements
and correlation examples
Current Change at Different Rate
• Processor wakes up in 0.2 clock cycle
• Memory operation starts in 5 clock cycle
• Memory read/write turn-around operation
in 2 cycles
• Power supply can not provide energy fast
enough, what is the reason?
Voltage Regulator 50A/uSec – too slow
Fundamental
• How fast the circuit needs energy?
– Determined by Intel/Altera.. Specification
• Circuit Operations  determine test patterns
– System wakeup from sleep mode
– Memory transaction
• Idle Read  Idle  Write
• Idle  Read  Write
• Idle  DRAM Refresh
– IO activities
• Test pattern frequency ≠ System resonance
frequency
What is system resonance frequency ?
Typical Power Delivery System
Power Delivery System View
VDD
Board
Decap
Voltage
Regulator
Module
Package
and on-chip
PCB
Power
planes
GND
Vmax
Vnom
Tolerance
Low-Freq.
Mid-Freq.
Regulator
Board
Package
Hi-Freq.
Vmin
On-Chip PDN
Device
Supply noise is added on several levels of the design hierarchy
PDN at Medium and Low Frequency
PDN impedance seen from the chip at low/medium
frequencies: ZPDN
VRM
Board
On-Chip
Package
 ZPDN
Simplified on-chip
PDN model
ZPDN has to be small over the entire frequency range
of interest to minimize supply noise due to current
variations
Target Impedance Concept
Analyzing Self-Induced Supply Noise:
- The Supply Impedance Profile (ZPDN) concept
ZPDN
(log)
Vnoise(f) = ZPDN(f) ∙ Inoise(f)
Typical Profile of
Supply Impedance
Frequency
VRM
PCB
x0 … x00 MHz
(log)
Vnoise
ZPDN
Package
On-chip
Inoise(f)
Typical PDN Impedance Profile
VRM
Board Caps
PCB Board
Package
On-chip Decaps
• Impedance profile formed by the interaction of various
PDN components
• Impedance peak at package/chip resonance
• Peak impedance dependent on package, PCB, and onchip parameters
Example PDN Impedance Profile - cont
Ztarget
ZPDN > Ztarget at package/chip resonance
Possible solution:
• Reduce package inductance
But other solutions possible as well
• Design trade-offs possible
Supply Noise Generation
•
Supply noise is dependent on INoise frequency profile relative to ZPDN
– Current components at frequencies of high ZPDN amplitude create large noise
fresonance = 100…300MHz
data
clock
edges
ZPDN
Frequency
•
In existing designs (e.g. 800MHz), already fresonance < (data rate) / 2
• Largest impedance can be excited by worst-case data pattern
• Increasing data rate does not increase supply noise amplitudes
But:
• Increasing data rate reduces timing budget available for supply noise
induced jitter
Supply Noise for Ltot = 2nH … 20nH
- 6.25GB/s Data Rate, Frequency Domain
• For high frequencies, noise is independent of Ltot
• Determined by on-chip decaps
DDR3 Power Supply System Overview
(WRITE Access)
Board
PCB
Controller Supply
Network
VRM
Controller
Package
DRAM
Signaling Channel
Package
Circuits
VddA
VddIO
Vss
•
Output drivers will generate noise on (VddIO-Vss)
– Especially during SSO events
•
Common practice: Sensitive circuits moved to ‘quiet’ supply (e.g. VddA)
Power Integrity analysis has to address
• Supply noise on (VddIO-Vss) - (self-induced noise during SSO event)
• Supply noise on (VddA-Vss) – (coupled noise during SSO event)
Supply Noise during SSO Event
- Output Driver Supply Noise
VddIO
Package
Synchronous Switching Outputs:
• Superposition of individual
driver switching currents
• Large current changes in
package supply
• Voltage changes on package
inductance
Vss
Impact:
• Voltage Margin reduction
• Timing jitter
• Waveform distortion
Supply Noise during SSO Event
- Supply Noise on Internal Supplies (Shared Vss)
VddA
Package
VddIO
PLL
Clock
Signal Path
Vss
Sources of Supply Noise Coupling:
• Ground Bounce
• Supply-to-supply coupling in package and circuits
• Signal-to-supply coupling in package
Impact of Supply Noise on Output Jitter
Ideal Supply
Eye
opening
Supply Noise
at Internal Circuits
Supply Noise
at Output Drivers
Eye
opening
Eye
opening
Total Supply Noise
Eye
opening
Outline
• Introduction
• Overview of Supply Noise in DDR3 Systems
• Analyzing Self-Induced Noise on Output
Driver Supply
• Analyzing Noise Coupling into Internal
Sensitive Supply
• Design Examples and Correlations
• Summary and Conclusions
Supply Noise Modeling Correlation with
DDR3 Test System
• Intention:
• Correlate supply noise prediction on DDR3 system
DDR3
DDR3
controller
DDR3
• DDR3 system for data rate up to 1600MHz
• 6-layer PCB board
• Controller in wire-bond package
– 32 data lines, 21 control lines
• Single rank of two x16 DDR3 devices
DDR3 Test System:
- Combined Power and Channel Model (DQ)
Controller
DDR3 Devices
Pkg
PCB
DQ[0:31]
DQ[0:31]
PCB
DQ[0:31]
Pkg
DQ[0:31]
CCCS
CCCS
CCCS
CCCS
• Final combined power and signal model consisted of:
– 32 DQ signals
– 21 Address and Control signals
DDR3 Test System:
- Output Driver Supply Noise Correlation
• Simulating supply noise waveform for two different data
pattern:
Pattern 2
Supply Noise
Supply Noise
Pattern 1
Good correlation of noise amplitude and waveform
DDR3 Test System:
- Measuring Jitter Sensitivity to VDDA Noise
• Measuring jitter on one signal line due to switching of other signal
line(s)
• Correlate to amplitude of coupled noise on internal supply VDDA
(simulated)
Scope
Controller
BA3
Procedure:
• Transmitting clock pattern on signal ‘BA3’ (victim)
• All but one of the other signals kept quiet
• One other signal (aggressor) transmitting clock pattern
•
Measuring jitter on ‘BA3’ for different aggressor lines
DDR3 Test System:
- Jitter Measurement Results
Voltage (mV)
Aggressor Pin Location (Relative to pin BA3)
A12
12.3
A12
BA0
A11
21
BA1
BA1
9.6
BA2
BA2
BA3
BA3
(BA3)
25
20
15
5
0
VDDA Noise Amplitude
10
90
80
70
60
50
40
30
20
10
0
BA0
13.3
A0
A0
22.7
21.7
A3
A3
15.5
A4
Pin
A4
Pin
CKjitter
A2
A2
14.5
A5
A5
Vdd_pp Comparison
12
A1
A1
13.5
A6
A6
A7
A7
9.2
A8
A8
7.8
A9
A9
8.9
A10
A10
9.2
Aggressor Pin Location (Relative to pin BA3)
ps
Jitter on Pin BA3
A11
• Strong correlation between jitter and VDDA noise amplitude
• VDDA amplitude dependent on local signal-to-supply coupling
Time Domain Power Noise Measurement
• Place probe close to the receiver end
• Use short ground leads to reduce probing
inductance
• Excite system with power sensitive
patterns and frequency
• Move trigger to min/max voltage setting
VNA and Impedance Measurement
• VNA is a sine-wave generator with a source
impedance of 50 Ohms.
• Measure reflected wave S11 to estimate
impedance
• When power impedance is less than 1 ohm,
VNA can not provide accurate results with one
port measurement
2-Port Low Impedance
Measurement
• The 2-Port VNA technique is the RF equivalent
of the Kelvin DC technique
• Both ports of of the VNA are connected to the
same pads of the DUT.
• Port 1 is used to drive the current through the
DUT
• Port 2 is used to measure the voltage generated
across the DUT.
• very small voltages can easily be measured by
port 2.
Two Port VNA Setup
Two Port Measurement Model
Probing directly on Bypass Caps
VRM Power Impedance
Measurement
When off, the RLC of the passive elements that make up the regulator
system is measured.
When powered on, the low frequency impedance is pulled dramatically
lower by the regulation feedback circuitry.
Recommendations
• Keep the phase length of the connections
from the ports to the DUT as short as
possible
• it should be within 1/20 of a wavelength of
the highest frequency measured.
• The microprobes, calibrated right to the
tips, can enable accurate frequencies well
above the GHz range.
Services and Products by Ben Chia
•
•
•
•
•
•
•
Signal integrity consulting
Power integrity consulting
Fixture design
LPDDR2 package model
Thermal consulting
Phase noise measurement
Durable PCB probes and probing solutions
- Contact www.packetmicro.com for details