Dragon-32 DDR FPGA Module
Features
Altera Cyclone III FPGA in 484-pin FBGA 23 x 23 mm
package. Many configuration options.
32-bit DDR2 interface capable of providing 1.2 Giga Bytes/sec Bandwidth between FPGA and DDR2 Memory.
Small form factor. 55.88 x 40.64 mm
Two (3.3 V / 2.5 V) I2C interfaces extended to the I/O connectors,
UART, SPI Programmable Ports
160+ I/Os & diff pairs available through five 50-pin Hirose connectors.
128 M-Bit SPI Flash Memory for non-volatile storage
1.8 V/2.5 V/3.3 V VCCIO levels supported
ADC chips that can take 2 input analog channels at 1 MSPS each
32 MB DDR2 SDRAM (32M x 32) memory
Separate EPROM to store FPGA configuration data
Maxim EEPROM chip for IP and clone protection
JTAG access through I/O connectors
Overview
The MRA Dragon Board is based on Altera Cyclone III EP3C40U484 FPGA. The MRA Dragon board provides low cost and high
performance solution using FPGA in a very small form factor. It is ideally suited for applications which require high performance, low
power consumption in a small form factor. The 5 Hirose connectors on the board provide easy interface to connect more than 160
signals to the FPGA. The connectors are placed so that the Dragon module can be easily sandwiched between two boards providing
very small form factor. Alternatively, it can be mounted as a daughter module on any other bigger PCB and provides ready-to-go
interface to the mother board to leverage the FPGA processing power.
Altera EP3C40 FPGA is a right mix between high performance and low cost. It provides 40,000 LEs, 126 multipliers, 4 PLLs and
1134 Kbits of embedded memory. The 32-bit interface between FPGA and DDR2 memory provides an effective bandwidth of 1.2
GB/s ideal for applications that requires data buffering along with high speed parallel processing. The Dragon board is also configured with the 16,40,55,80K LE FPGA. The MRA Dragon module reduce development effort and improves time-to-market.
Block Diagram
IP Support
Target Application
Altera DDR2 Controller IP
Digital Signal Processing
Altera Video and Image Processing Pipeline
Video Processing
MRA Camera Interface pixel processing pipeline
Data Buffering
MRA BT656-2-HD Video Bridge
Motion Control
MRA Frame Buffer / Frame Reader IP
Automotive Applications
MRA I2C Master
Low Power Applications
MRA I2C Slave
Embedded Processing and control
MRA ADC Interface
Video Up/Down Scaling
Top Side Photo
Top Side Photo
FPGA Configuration Options
EP3C16
EP3C40 (Standard Configuration)
EP3C55
EP3C80
Related Products
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MRA Dragon test board for prototyping
MRA Camera Interface Board
MRA HDMI video receiver Board
MRA OMAP board
More Information—Detailed datasheet is available on request. For detailed datasheet and pricing please contact MRA
Digital support.
www.mradigital.com - [email protected] 443-224-8955
MRA Digital, LLC, All Rights Reserved. This document is for planning purposes only, and is not intended to
modify or supplement any specifications or warranties relating to products of MRA Digital, LLC. MRA Digital
may make changes to specifications and descriptions at any time without prior notice.