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IRISA / Inria – Cairn Team
Energy-Efficient Reconfigurable Computing Architectures
University of Rennes 1 – IRISA / Inria
Campus de Beaulieu – 35042 Rennes
ENSSAT – 6 rue de kerampont – 22300 Lannion
France
http://www.irisa.fr/cairn
Design Flow and Run-Time Management
for Compressed FPGA Configurations
Christophe Huriaux, Antoine Courtay, Olivier Sentieys
Abstract
Partially and dynamically reconfigurable hardware provides an increased flexibility through the load of multiple
applications on the same reconfigurable fabric at the same time. However, a configuration bit-stream loaded at
runtime should be created offline for each task of the application. Moreover, the use of specialized hardware blocks
tends to cancel the single bit-stream for a single application paradigm, as the logic content for different locations of the
reconfigurable fabric may be different. We propose a design flow for generating compressed configuration bit-streams
abstracted from their final position on the logic fabric. Those configurations are then decoded and finalized in real-time
and at run-time by a dedicated reconfiguration controller to be placed at a given physical location. The generated
configurations moreover benefit also from a compression factor up to 10×, without using memory-costly algorithms
(LZSS) used in the literature [1,2].
Overview of the CAD Flow
Virtual Bit-Stream Concept
The VTR (Verilog To Routing) tool
flow [3] is used to synthesize an HDL
description up to the placement and
routing steps using VPR (Versatile
Place-and-Route).
Our custom back-end vbsgen uses
the placement data generated by
VPR to create a bitstream suitable to
the target reconfigurable architecture.
This bitstream is a Virtual BitStream, containing all the
routing data in an abstracted
representation. This allows to
achieve:
- An independence of the VBS
from its relative placement on
the reconfigurable fabric
- A compression of the bitstream
The repeatable pattern of
an FPGA is a Logic Block
(LB) surrounded by its
interconnection network.
Each dot is a 3 or 4-way
routing element.
A full bit-stream of this In sparsely routed areas,
pattern needs to describe the compression gain is
the state of each switch ! huge since little data gets
encoded.
Results
Bit-stream size comparison
Size (min/max)
Size (avg)
Compression (avg)
80 %
60 %
1000
40 %
VBS size (Kbit)
Size (Kbit)
BS
VBS
Ratio VBS/BS
800
80 %
600
60 %
400
40 %
200
20 %
20 %
100
0%
tseng
spla
seq
s38584.1
s38417
s298
pdc
misex3
frisc
ex5p
ex1010
elliptic
dsip
diffeq
des
clma
bigkey
apex4
apex2
Circuit
The complexity of this controller is low
since the routing is made on the local
interconnection network and has been
proved possible offline.
100 %
100 %
Compression ratio
10000
1000
Compression ratio
Target Architecture
The generated Virtual Bit-Streams are
stored in a memory on the target
platform and loaded at runtime by a
reconfiguration controller.
The Virtual Bit-Stream
describes the routing as
a list of connections from
one I/O of the local
interconnection network
to another.
Our results on the 20 biggest MCNC
designs shows an average
compression ratio of 40%. The most
dense designs get the highest ratios.
0
0%
1
2
3
4
5
6
7
8
9
10
Cluster size
Clustering multiple basic patterns
together leads to compression
factors up to 10×, at the cost of more
operations needed at run-time.
[1] J. H. Pan, T. Mitra, and W.-F. Wong, “Configuration bitstream compression for dynamically reconfigurable FPGAs,” in the Int. Conf. on Computer Aided Design. IEEE, 2004, pp. 766–773.
[2] Z. Li and S. Hauck, “Configuration compression for Virtex FPGAs,” in the Symp. on Field-Programmable Custom Computing Machines. IEEE, 2001, pp. 147–159.
[3] J. Rose et al., “The VTR project: Architecture and CAD for FPGAs from Verilog to Routing,” in the Int. Symp. on Field Programmable Gate Arrays. ACM, 2012, pp. 77–86.
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