ENCM 369 Winter 2015 Tutorial for March 19: Pipelined processor Author: Steve Norman. Electronic copies of handouts for this course can be found at http://people.ucalgary.ca/People/~norman/encm369winter2015/ This is Figure 7.47 from Harris and Harris: Digital Design and Computer Architecture, 2nd edition, c 2013, Elsevier Inc. . . . copyright CLK 5:0 RegWriteD RegWriteW MemtoRegD MemtoRegE MemtoRegM MemtoRegW MemWriteD MemWriteE MemWriteM BranchD BranchE BranchM Op ALUControlD ALUControlE2:0 Funct ALUSrcD ALUSrcE RegDstD RegDstE CLK 0 PC' PCF 1 A RD PCSrcM ALUOutW CLK InstrD Instruction Memory + 25:21 20:16 WE3 A2 RD2 A3 Register WD3 File 0 SrcBE 1 20:16 15:11 RdE Sign Extend 0 1 SignImmE PCPlus4D ALUOutM WriteDataE WriteDataM WriteRegE4:0 WriteRegM4:0 A RD Data Memory WD ReadDataW 0 1 WriteRegW4:0 <<2 + PCPlus4F WE ZeroM SrcAE RD1 RtE 15:0 4 A1 CLK ALU CLK CLK RegWriteM Control Unit 31:26 CLK RegWriteE PCBranchM PCPlus4E ResultW Problem 1. Consider the following sequence of instructions: nop nop nop add sw nop slt nop nop nop $10, $8, $9 $11, 36($29) $12, $4, $10 Will the add, sw, and slt instructions all work correctly, or will there be some incorrect results due to the lack of forwarding hardware in the processor of Figure 7.47? Notes for Problems 2–8. These problems all consider the sequence of instructions from Problem 1, running in the Figure 7.47 processor with a clock period of 1.0 nanoseconds. The problems all suppose that that clock cycle for the IF stage for the add instruction begins at t = 20.0 ns after a program starts running. Problem 2. Throughout the entire instruction sequence, the MemWriteD signal coming directly out of the main control unit will have a value of 1 during only one clock cycle. When does that occur? Problem 3. When does MemWriteD=1 get written into the D/E pipeline register? Problem 4. When does MemWriteE=1 get written into the E/M pipeline register? Problem 5. When does the sum of 36 and $29 get written into the E/M pipeline register? Problem 6. When does the value of $11 get written into the E/M pipeline register? Problem 7. When does the value of $10 get updated within the Register File? Problem 8. When does the value of $10 get written into the D/E pipeline register as part of handling the slt instruction? Problem 9. Suppose you know tpd for each of the combinational elements in the Execute stage in Figure 7.47, and you know tpcq and tsetup for the pipeline registers. For safe operation of the Execute stage, what do all of those numbers tell you about the clock period TC ? Problem 10. (Not a good midterm problem because the description is too vague.) Consider the following sequence of instructions: nop nop nop add lw add sw nop nop nop $t0, $t2, $s2, $t2, $s1, $t1 ($t0) $s2, $t2 ($s4) The processor of Figure 7.47 would fail very badly with this sequence because of all the data hazards. Draw an “abstract pipeline diagram” to show all the stalls and forwarding that would be used by a better processor to correctly handle all the data hazards.
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