UNIVERSITI MALAYSIA PERLIS
SCHOOL OF COMPUTER &
COMMUNICATIONS ENGINEERING
EKT303/4
PRINCIPLES OF COMPUTER ARCHITECTURE
LAB 4 : MEMORY DESIGNS IN VHDL
Lab4
EKT303 Principles of Computer Architecture
LAB 4: Memory design
OUTCOME:
1)
2)
3)
4)
Ability to identify the sequential operation techniques
Ability to describe the operation of sequential synthesis
Ability to demonstrate the use of architecture types
Ability to develop a simple VHDL program in Altera Quartus II software
INTRODUCTION
In computer architecture terms, memories are actually a form of data
storage (registers) and are usually referred to as a part of computer
components that have the ability to retain digital data. Computer data
storage provides one of the core functions of the modern computer, that of
information retention. It is one of the fundamental components of all modern
computers, and coupled with a central processing unit (CPU, a processor),
implements the basic computer model used since the 1940s known as the
stored-program concept.
A memory can either be non-volatile (as seen in a read-only memory)
or volatile (used in random-access memory).
Read-Only Memory (ROM)
Read-only memory (usually known by its acronym, ROM) is a class of
storage media used in computers and other electronic devices that is nonvolatile (non-changeable). Because data stored in ROM cannot be modified
(at least not very quickly or easily), it is mainly used to distribute firmware
(software that is very closely tied to specific hardware, and unlikely to require
frequent updates). Figure 4.1 below depicts a ROM block diagram which
have k-bit address and an n-bit data.
Figure 4.1 : ROM block diagram
The contents of a ROM chip are defined once. Hence, we can use a
constant array to model a ROM in VHDL. Basically, to name the size of a ROM
is by stating ROM k x n, which represents ROM with k-bit address and n-bit
data size. For example, ROM 4x8 (16 address location with each location
containing 8-bit data).
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The following Figure 4.2 illustrates an example of ROM4x7 which
contains the seven-segment decoder data.
Figure 4.2 : VHDL code for a ROM4x7
containing seven segment data codes.
Base in the example in Figure 4.2, the operation of this ROM will output the
concerned data based on the address issued.
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Random Access Memory (RAM)
Random Access Memory (commonly known acronym RAM) is a class
of storage media used in computers and other electronic devices that is
volatile (changeable). The operation of a RAM is slightly different to a Readonly Memory (ROM) where RAMs can perform read and write data
operations based on the address whereas the latter can only read.
In VHDL, RAM may be modeled in much the same way as a ROM.
Because of data may be stored in the RAM as well as read from it,
declaration of the data signal must have ‘in’ mode and ‘out’ mode. Figure
4.3 below shows the VHDL description of a Static RAM.
Like the ROM, the memory array is modeled as an array, this time as a
signal (or a variable inside a process) not as a constant. The default initial
value of a signal or variable std_logic should be ‘U’ (unknown logic) when
synthesized, because no initial value was defined inside the array locations.
As was done in ROM, again, the example provided does not include timing
which could be easily done.
Figure 4.3 : VHDL code for a Static RAM 16x8
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Lab4
EKT303 Principles of Computer Architecture
Simulate this RAM example in Altera Quartus II software with the following time
parameters and waveform:
End time
:= 1.0 us
Grid size
:= 50.0 ns & snap to grid
Waveform and values as in Figure 4.4 below :=
Figure 4.4 : Static RAM waveform editor
Observe the operation’s behavior every time the chip select (cs) is forced
high.
EXERCISE
1. Figure 4.2 above show the ROM operation without any synchronization.
Rewrite the code to allow the ROM operation to work in snyc only
when a read enable is asserted.
2. Figure 4.3 above show the RAM operation without any synchronization.
Rewrite the code to allow the RAM operation to work in sync only
when a read enable is asserted.
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EKT303 Principles of Computer Architecture
3. Create a Synchronous RAM with the following block diagram :
In_clk
write
8
Data_in
4
Data_out
8
Address
Out_clk
read
Block diagram of a dual clock RAM
Where :
In_clk
write
Data_in
Address
Out_clk
read
Data_out
: timing for data to be written
: write control signal
: 8 bit data to be stored
: 4 bit address location
: timing for data to be read
: read control signal
: 8 bit data to be read
Simulate the RAM using the following timing parameters :
End time
Grid size
In_clk
Out_clk
: 1.0 ms
: 50.0 us
: count every 5.0 us
: count every 20.0 us
Generate and simulate the VHDL codes in Altera Quartus II for the
above exercise.
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