1. business and industrial
2. manufacturing

JCET Low Cost High Density
Packaging
g g Solution
March 2015
Jiangsu Changjiang Elec. Tech.
$1 000
$1,000
SJsemi
$850
National
N
ti
l High
Hi h Density
D
it
Packaging Lab
China IC Packaging
Alliance
Chuzhou C9
$714
Suqian C8
$545
SSE IPO
C3 (IC)
C5 (SiP)
JCET
JCAP
(Bumping
(B
i
& WLP)
Cu Pillar
Jiangyin Transistor
Factory
1972
1995
$611
$54
$82 $133
2000
2002
2003
$338
$356
$350
WW OSAT Ranking
NO.6
NO.7
NO.8
MIS
2007
NO.4
2008
2
2009
2010
2011
2012
2013
2014
Snapshot of Factory
JCET C3
JCET HQ
C8(Suqian)
C9 (Chuzhou)
3
Production Line
4
Factory Expansion in 2015
5
Contents
Desire for Low Cost
PKG Interconnection - Bump
PKG Interconnection - Wire
PKG Base - Substrate
Low Cost Solutions
JCET Turnkeyy Services
6
Desire for Low Cost
Wh d
Why
do we select
l t “l
“low cost”
t” as the
th topic
t i ?
•Desire for “lower cost” is stronger and stronger in semiconductor packaging though market driven
force was shifted from computer to communications, and now IoT and wearables.
•“Advanced technology” doesn’t mean “high volume”
•To provide premium packaging service in competitive cost to our customers is our mission.
What is the definition of “low
low cost”
cost in this industry?
•We have known the definition of Low cost well but we may not think it right. Low cost should be
thought as a relative concept instead of absolute concept.
•“Low
•
Low cost”
cost doesn’t
doesn t mean “ low
low-end
end technology
technology”
How should we calculate cost?
•We should calculate cost at the level of system instead of the level of package.
7
Back to Basics
8
PKG Interconnection - Bump
Solder Bump
Cu Pillar Bump
Bump on Pad
Bump on Trace
Bump Type
Solder Bump
Cu Pillar Bump
Min. Bump Pitch
>150um
> 50um and 110um in Mass Prod.
Substrate Layer #
4
2
Surface Finish
SOP
OSP
Cost Factor
1
0.5
9
PKG Interconnection - Bump
10
PKG Interconnection - Wire
Wire Material Cost Saving Comparing to Au Wire
Price (USD per OZ)
G ld
Gold
C
Copper
PdCuAu Wire
Electrical Conductivity
(10E6 Simens/m)
Alloy (Silver)
0 95
0.95
Sil
Silver
Gold
0.9
1170
0.85
Gold
0.164
16
0.8
Copper
Silver
0.75
44.2
0.7
Electrical Resistivity
((10E-8 Ohm.m))
Gold
2.3
Gold
Copper
0.8
0.9
1
Thermal Conductivity
(W/m.k)
Silver
Gold
Copper
Gold
Silver
58.5
62.1
Copper
Silver
Thermal Expansion Coef.
Coef
(10E-6 k-1 from 0 to 100C)
Silver
1.7
1.6
317
401
420
Copper
Silver
Gold
Copper
Silver
11
1.2
Copper
Gold
14.1
Gold
Copper
17
Copper
Silver
19
Silver
PKG Interconnection - Wire
 JCET SiP Center ships more than 60Mu/month
WB p
products to our customers at p
present, including
g
BGA and LGA.
 80% of FBGA are using Alloy (Ag) wire, the 15%
are Cu wire (PdCu & PdCuAu) product , the rest
5% are Au wire product.
p
 80% of WB LGA are Cu wire (PdCu & PdCuAu)
product and the rest are Au wire product.
 Assembly yield of WB product is above 99.9%.
 Cu wire bonding
g on 28nm wafer was qualified and
brought into mass production at 1H of 2014.
12
Substrate Selection
Wafer Node
60nm and above
40nm
28nm
16nm
Die Size
7x7~9x9mm
5x5~7x7mm
5x5~7x7mm
~5x5mm
Bump Pitch
150um
110um
95um
80um
Higher
Cost
Fan-out/eWLB
SAP
ETS
Coreless
MSAP
Finer
Pitch
MIS
Tenting
50/50
40/40
35/35
30/30
13
25/25
20/20
15/15
10/10um
Substrate Selection
2L MSAP Substrate
2L MIS Substrate
(Film Mold + Cu)
14
Substrate Selection
Key Cost Points:
 4L SAP Substrate
 Low CTE Core
 CUF
15
Substrate Selection
Key Cost
K
C t Points:
P i t
 3L Coreless Substrate
 Low CTE PP
 CUF
Note: Crack shown on above SEM was caused by Ion milling.
16
Substrate Selection
Key Cost
K
C t Points:
P i t
 3L ETS Substrate
 Low CTE PP
 MUF
17
Substrate Selection
Key Cost Points:
 3L MIS Substrate
 ((Film mold + Cu)) Only
y
 MUF
18
Substrate Selection
Key Cost Points:
 4L Hybrid Package
 Low CTE PP
 MUF
19
Low Cost Solution for FC
Low Cost Package Solution
•Low Cost Design & Technology
•Low Cost Supply Chain
•Economy of Scale
 BOL(BOT)
 Mass Reflow
 MUF













Low Cost Technology




12 inch silicon wafer
Chip probe before bumping
Without PI ReP (Non-PI)
Electroplated Bump: Cu Pillar
• Chi
Chip + PKG + PCB C
Co-design
d i
• Low Cost doesn’t mean low
performance, system level simulation is
essential for insurance of performance
• “Low cost + Stable Performance” may be
better than “Higher
cost + High
g
g
performance” in emerging market
considering smartphone is cheaper and
cheaper plus life time is shorter and
shorter.
1L or 2L Substrate
Standard core/preprag material
Wider Trace Pitch
Mechanical Drill
Plated Through Hole
Liquid Type Solder Mask
Solder Mask Registration
OSP
Tenting or MSAP Substrate
Coreless Substrate
UHD Strip (Wider Strip)
SiP/St k Die
SiP/Stack
Di
Optimized Ball Layout for 4 or 6
layer PCB Design
Low Cost Supply Chain
•Wafer Fab: SMIC
•Wafer Bumping: JCAP, SJsemi
•Assembly
A
bl and
d Test:
T t JCET




Capable of supporting all type of devices (Good for Customer Centralized management)
Turnkey Service from design to ship (Plenty experiences of on-site design support )
Low cost solution (p
(playy major
j role in low cost supply
pp y chain))
Sufficient capacity (economy of scale)
20
Realize Low Cost Solutions
Low Cost
Co-Design
Engineers
C lt
Culture
System
S t
21
Turnkey Services
Project Phases
Process Characterization
and Verification
Focus
Data Collection/Verification
(Test Vehicle)
Turnkey Services
•
•
•
•
•
Qual. Assurance
• Simulation Model Set Up
• Simulation Model Verification
• Failure Analysis
Design &
Simulation
Functionality and Reliability
(Engineering Prototype)
Solution Proposal and Planning
Test Vehicle Design
Process Characterization
Test Vehicle Measurement
Reliability Test
Engineering
Prototype
Functionality Verification and
Reliability Test
Product and Process
Optimization in LVM
Production Yield,
Process Cycle Time
Production Cost, Yield, CT
•
•
•
•
Cost Reduction Proposal
Yield Improvement
CT Improvement
Test Time Optimization
•
•
•
•
O/S Test
Final Test
Lead Scan
Failure Analysis
•
•
•
•
•
•
•
•
•
AP RDL/Bump Design
Package Design
Test Board Design
1st Silicon Characterization
Wafer Bumping
Wafer Probing after bump
Assembly
Test program development
Marking, Packing, Shipping
• Design Optimization
• Process Optimization
• Test Program Optimization
•
•
•
•
•
•
Lead Scan
O/S Test
Final Test
Reliability Test
Failure Analysis
Support on System Level Test
•
•
•
•
Wafer
Bumping &
Probing
Assembly
22
HVM Production and
Cost Reduction
O/S Test
Final Test
Lead Scan
Failure Analysis
Final Test
Failure
Analysis
Material
(MIS Substrate)
Summary - We Are Ready
Customer Centric
Low Cost Solution
Time to Market
Turnkey Services
Strive to Be
The Best
 Our professional team has truly heart of customer centric and plenty experiences of customer services
 We
W propose llow cost solution
l i and
d play
l major
j role
l iin llow cost semiconductor
i
d
supply
l chain
h i
 We are close to both wafer fab and product end users, and we deliver services in short cycle time
 We provide turnkey services from design to drop shipment
 We are capable of supporting a broad range of processors, modules and controllers, which is for customer
customer’ss centralized management
 We have sufficient capacity for large volume production orders
 We have automated process control and monitoring system to minimize human interference in production
 We have mature QA system across all sites for error proof
 We are young, we have dreams to realize and we strive to be the best in our customer’s supply chain
23
谢 谢！
Thank you
y