System-to-Silicon Verification Summit – September 26, 2013 How to make sure that energy and performance envelopes are met and what's the cost of missing them? Jim Hogan Gartner's 2013: Emerging Technologies Augmenting humans with technology Technologies : bioacoustics sensing, quantified self, 3D bio printing, brain-computer interface, human augmentation, speech-to-speech translation, neurobusiness, wearable user interfaces, augmented reality and gesture control. Machines replacing humans Technologies: volumetric and holographic displays, autonomous vehicles, mobile robots and virtual assistants. Humans and machines working alongside each other Technologies: autonomous vehicles, mobile robots, natural language question and answering, and virtual assistants. Los Gatos, CA September 20, 2013 Aggregation vs. Disaggregation Networks Operators Operators AT&T AT&T, Verizon Chrome Web Store HTML Apps Device Apps System Nokia Ericsson Nokia, Ericsson, Palm, Samsung … Middleware Operating System Symbian, Palm OS Drivers Nokia Firmware Chip Sub-System IP Operators Operators Symbian, Palm OS TI, TI, Qualcomm, Qualcomm, Freescale Motorola Apple Apps Store Apple Apps Store Apple iPhone Google Play Chrome Book Chrome Web Store Chrome Web Store Google Play Google Play Google Nexus 10 Google + Motorola Acer Samsung Google Android Google Chrome OS on Linux Google Android Intel Atom N570 Samsung Exynos 5250 Samsung System Houses Google Android & ChromeOS Apple iPhone 3GS All Semis Samsung ARM big.LITTLE, Imagination, MIPS, Tensilica ARC All Semis ARM big.LITTLE +Mali, Nvidia Kepler, IMG+MIPS, Tensilica, ARC 4 Consumer technology has split into three primary battlegrounds Source http://www.fool.com/free-report/stock-advisor/5-biggest-tech-stocks/print The problem USB Ctrl. Apps Proc. Fabrics Packet Proc. DSP DPI today Disk Drive WiFi USB Hub DDR Switch Internet Smart Home Phone Alarm IPTV Semiconductors OEM/ODM Applications Chip Power System Power Application Power Sub-optimal performance and energy efficiency 6 Chip Design in 2015 • • • • • Every increasingly complex designs Overall less design starts, increase at <90nm More than 110 IP Blocks More than 70% re-use, majority are third party commercial More than 60% of effort in software – Software Complexity – Multi-core – Distribution across cores • Always on: Low power, IoT • Sensors: Mixed signal content IoT • Application Specificity 7 Integration & Verification Challenges Multi-core SW development & HW/SW verification ARM CPU Subsystem A7 A15 A15 Customer’s Application Specific Components SoC SW & IP integration with 10’s to 100’s of IPs A7 AES 3D Graphics Core L2 cache L2 cache Modem Application Accelerator s … … Cache Coherent Fabric SoC Interconnect becoming more AXI Coherency Extension (ACE) protocol introduces new complex SoC Interconnect Fabric complexity HDMI DDR3 USB3.0 PCIe Gen 2,3 Ether net SATA MIPI PHY 3. 0 2. 0 PH Y PH Y PHY PHY WLAN High speed, wired interface peripherals Other peripherals UART Display INTC PMU I2C MIPI SPI Analog-Mixed Signal Low-speed peripheral JTAG subsystem Timer LTE Complex low power design features need to be verified at SoC level spanning HW/SW GPIO Low speed peripherals Timing, CDC, clk/reset (x-propagation), Gate Level Simulation Requires many development environments on different platforms Nearly five million lines of code executing in parallel to enable residential gateway Source ARM Software Needs to be considered Source: IBS July 2013 10 Verification in an Example Project Project data from real measured projects (IBS) Spec to GDSII: 49 - 83 wks 8-12 wks Design & Integration & Verification: 35 – 63 wks Netlist to GDSII: 21 - 32 wks 14 wks 11 - 17 wks 14 - 18 wks System on Chip Sub-System Idea to spec IP Spec RTL Becomes stable Only small gate level changes and ECO’s RTL-Design & IP Integration & Verification Netlist to GDSII IP Qualification Production Post silicon Validation Fab Post Si Find System Environment related bugs! Project data from real measured projects (IBS) Time for critical bugs in System Environment to be removed SoC in System System on Chip Sub-System Idea to spec IP Spec RTL Becomes stable Only small gate level changes and ECO’s RTL-Design & IP Integration & Verification Netlist to GDSII IP Qualification Production Post silicon Validation Fab Post Si Software is key to verification Project data from real measured projects (IBS) Applications (Basic to Angry Birds) May hold final tape out if bug too critical Middleware (Graphics, Audio) OS & Drivers (Linux, Android) Bare metal SW Time for critical bugs in System Environment to be removed SoC in System System on Chip Sub-System SW Development on Chip Idea to spec IP Spec RTL Becomes stable Only small gate level changes and ECO’s RTL-Design & IP Integration & Verification Netlist to GDSII IP Qualification Production Post silicon Validation Fab Post Si System Software extend platform life but OMG the Verification is a nightmare SDK OS Sim Virtual Platform RTL Simulation •Highest speed •Earliest in the flow •Ignore hardware •Almost at speed •Less accurate (or slower) •Before RTL •Great to debug (but less detail) •Easy replication •KHz range •Accurate •Excellent HW debug •Little SW execution Acceleration Emulation •MHz Range •RTL accurate •After RTL is available •Good to debug with full detail •Expensive to replicate FPGA Prototype Prototyping Board •10’s of MHz •RTL accurate •After stable RTL is available •OK to debug •More expensive than software to replicate •Real time speed •Fully accurate •Post Silicon •Difficult to debug •Sometimes hard to replicate There is no “One Size Fits All” 14 Energy proportional systems HOW WE DESIGN SYSTEMS … HOW NATURE DESIGNS SYSTEMS … … FOR MAXIMUM PERFORMANCE … FOR MAXIMUM EFFICIENCY 15 Energy proportional management of residential gateway 16 Residential gateway (HW reference design) (out of the box OS) + (power consumption) = 8.1W + + AGGIOS™ SW IP and tools 17 = 3.5W Every watt matters … # of households in Japan 51,950,504 51,950,504 # of residential gateways per household * 0.75 * 0.75 # of Watts per device * 8.1 = 315,599,311W * 3.5 = 136,370,073W Δ = 179,229,238W (compare to) 825,000,000W Namie-Odaka Nuclear Power Plant (Fukushima prefecture – exp. 2017) Sources: wikipedia.org 18 Summary • SOC makers must : – Develop ‘richer’ eSW stacks – Extend and master their “many core+” architecture HW and SW – Rethink their virtual prototyping strategy • Traditional EDA does provide solutions for two main reasons – HW centric …. it is a SW issue – RTL centric …. it is a System issue Thank you