Download Report

November 2008
Hands-on Workshop: How to Use Ultra-Low Cost
RS08 Processors in Real-Time Applications
PZ113
Kenny Ji
Systems and Applications Engineering
TM
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Curta Calculator
►Curta
• a small, hand-cranked mechanical
calculator introduced in 1948
►Features
• Addition
• Subtraction
• Multiplication
• Division
• Square roots
►Advantages
• Easy to use
• Portable
• No battery needed!
• ...
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TM
RS08 Core – Curta in Silicon
►RS08 Core
• Optimized Memory Organization
High code density for 16-KB
Memory size
High efficient access to first 256
bytes

•
Optimized instruction set
Compact instruction set for high
code density
Simplified HCS08 Instruction set for
code porting

•
Simplified stacking and calling
mechanism
•
Polling Interrupt Mechanism
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TM
RS08 Target Applications
¾ Target Applications
¾ Ultra-bright LED Application –
MR16 Bulb
¾ Low End Thermal Controlled BLDC
Fan – KA2 Replacing Analog Driver
¾ Low End Remote Control in Light
Dimmer, Light Switch, Electric Fan
-- KA2 Replacing ASIC / 4-bit MCU
¾ Toaster Oven Application – KA2
Replacing ASIC
¾ AC Voltage Line Monitor
¾ Low End Microwave Oven
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TM
First EETimes China ACE (Awards for Creativity in Electronics)
Best Product of the Year in Microcontrollers (MCUs) Category
- MC9RS08KA family
•Finalist in EE Times America ACE Award
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TM
Objective and Agenda
►Objectives:
Address field concerns on the RS08 MCU in Real-time applications.
• Provide RS08 Real-time solutions.
•
►Agenda:
RS08 Architecture
• Interrupt Mechanism used in RS08 CPU
•

•
Real-time solutions for RS08 MCU

•
Nested Interrupt VS non-Nested Interrupt
Event Based scheduling
High efficient scheduling
Examples
FAQ
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TM
Small but Powerful
RS08 Architecture
TM
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RS08 Core CPU Model
► CPU
• Central Processing Unit
• Processing most algorithm & logic
operations
► BDC
• Background Debug Controller
• Providing background debug capability
for RS08 CPU
► MMC
• Memory Mapping Controller
• Providing memory accessing capability
in RS08 core
► IMU
• Integration Management Unit
• Interfacing RS08 core to external logic
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CPU
CPU
BDC
BDC
MMC
MMC
IMU
IMU
BUS
TM
RS08 Core CPU Model
►CPU Registers
• A – Accumulator
• PC – Program Counter
• SPC – Shadow Program Counter
• CCR – Condition Code Register
►Memory Mapped Registers
• D[X] – Indexed Data Register
@0x000E
• X – Index Register @0x000F
• PAGESEL – Page Select Register
@0x001F
Accumulator (A)
Program Counter (PC)
Shadow Program Counter (SPC)
Condition Code Register (CCR)
ZZ CC
Indexed Data Register (D[X])
Index Register (X)
Page Select Register (PAGESEL)
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TM
Memory Map and Addressing Mode
►Memory Map
• Direct Page
Fast Access RAM
Paging Window
Short Addressing
High Page Registers
Nonvolatile Memory
Direct Addressing

•
•
Fast Access RAM
Tiny Addressing
D[X]
X
Frequently Used Registers
PAGESEL
RAM
Unimplemented
►Addressing Mode
• Inherent Addressing Mode (INH)
• Relative Addressing Mode (REL)
• Immediate Addressing Mode (IMM)
• Tiny Addressing Mode (TNY)
• Short Addressing Mode (SRT)
• Direct Addressing Mode (DIR)
• Extended Addressing Mode (EXT)
• Indexed Addressing Mode
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Paging Window
Unimplemented
High Page Registers
Unimplemented
Nonvolatile Memory
TM
Optimized Instruction Set
►Optimized
Instructions
•
•
Most Opcode are
encoded in Tiny and
Short Addressing
Modes
Tiny and Short
Addressing Modes
saving at least 1 bytes
per instruction which
maximizes code density
and is quite suitable for
small applications
= Tiny Addressing
= Short Addressing
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TM
Stacking and Calling
►Stacking
• No hardware stack management to
simplify stacking maintain
• No special registers needed for
stack operations
• Software stack management as
alternate method if necessary
►Calling
• Shadow Program Counter (SPC)
• Register-based instead of RAMbased calling stack operation for
quick calling
• SHA and SLA instruction used for
more than nested calling
Accumulator (A)
SHA instruction
SLA instruction
Program Counter (PC)
return from calling
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Jump to calling
Shadow Program Counter (SPC)
TM
Polling Mode Interrupt Schedule
RS08 Interrupt Mechanism
TM
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RS08 Interrupts Model
►RS08 Application Model
• The time based event model allows software sorts interrupt priorities and selects
the top one to execute.
• Time based event model does not use interrupt vector table as it will prevent the
interrupt priorities sort.
• Time based event model can maximize the usage of code and minimize RAM
size.
Executing ISR
Executing ISR
ISR
Return from ISR
Interrupted
Interrupted
Return from ISR
Background
Background
Background
Running
Wait/Stop
Go to Wait or Stop
ISR
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Background
Time Direction
TM
How does RS08 CPU service interrupts
►Polling
mode interrupt
CPU will be waked up from wait and stop modes when an interrupt
occurs.
• The corresponding interrupt bit in system interrupt pending register (SIP)
will be set.
• The program flow is scheduled by polling SIP register.
• ISR priority is software defined.
•
►Target
Applications
State machine
• Time based event applications
• Event base applications
•
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TM
Traditional Interrupts Operation
►
►
►
►
►
/* This column shows a typical
background program for a
interrupt-based schedule */
►
/* background program */
►
►
►
void main(void)
{
/* do any initialization here */
ng
ri
te
En
R
IS
►
►
►
►
►
/* enter the background,
loop forever */
while(1)
{
/* do lowest priority tasks
here*/
...
}
}
/* interrupt service routine */
►
►
►
interrupt void ISR1(void)
{
/* do interrupt triggered
tasks
►
here */
►
...
►}
R
IS
/* enable interrupts */
►
ng
ti
ci
Ex
►
►
►
►
/* This column shows a typical
interrupt service loop
program
►
for a interrupt-based
schedule */
►
►
►
interrupt void ISR2(void)
{ As main program can be interrupted at
any
anywhere unmasked,
a
/*time
doand
interrupt
triggered
lot of
stacking
tasks
here
*/operation is made to
save
►
...the status, which will take much
time and many memories.
►}
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TM
RS08 Interrupts Operation
/* This column shows an RS08
background program for a
interrupt-based schedule */
►
►
►
/* This column shows a typical
interrupt service loop program
for a interrupt-based schedule */
►
/* background program */
►
/* interrupt service routine */
►
►
►
►
►
►
void main(void)
{
...
while(1)
{
stop(); // stop until arise
►
►
►
void ISR1(void)
{
/* do interrupt triggered tasks
here */
...
}
R
IS
►
►
ng
ti
ci
Ex
if (interrupt 1 triggered)
{
ISR1();
continue;
}
if (interrupt 2 triggered)
{
ISR2();
continue;
}
...
►
►
►
►
►
void ISR2(void)
{
/* do interrupt triggered tasks
here */
...
}
RS08 polling mode controls the
program stream wholly so that no
stacking operation is needed and
minimal latency is required.
R
IS
►
►
►
►
►
►
►
►
►
►
►
►
►
ng
ri
te
En
►
►
►
}
}
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TM
Benefits of RS08 Interrupt Mechanism
►More
•
available code space
As no vector table needed, RS08 core can utilize 32 bytes reserved for
HC08 vector table.
►Minimized
•
As no stacking operation, RS08 core need no hardware stack and no
big memory support.
►Minimized
•
interrupt latency
As no stacking operation, RS08 core need few cycles to enter and exit
from interrupt service routine (ISR).
►Increased
•
•
RAM size
performance
10-MHz BUS
Reduced cycle count for RAM access
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TM
Target Real-time Applications
A Timing-base RS08 schedule example
TM
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Timing Base RS08 Core Schedule
►Timing Based RS08 Core Schedule
• The main idea is intended to split big tasks into small fragment so that it can be
schedule in a timing slot.
• The timing is handled by hardware timer.
• As far as the ISR is small enough, the total time period can be occupied by a
scheduled task.
• All tasks pended are prioritized so that the pended task will always be serviced
firstly
Timing Period = T
T
T
T
Time Direction
Task A
Task B
Background
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ISR + Scheduler
TM
Timing Base RS08 Core Schedule
Set Hardware Timing Source
1.
•
•
Select a hardware timer as timing source
Keep Timing ISR as short as possible
Tasks Allocation
2.
•
•
Split big task into small fragment
Prioritize Tasks
Schedule Tasks after timing ISR
3.
•
•
Schedule task when timing ISR is completed
Schedule the pended task with top priority to execute
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TM
Set Hardware Timing Source
►Select a hardware timer as timing source
• Hardware timer has more accuracy than software
• Hardware timer is standard peripheral of MCU
►Keep Timing ISR as short as possible
• Timing is only a source to execute split tasks
• Keep ISR short means more time for task execution
MTIM: 8-bit Modulo
RTI: Fixed Modulo, 1, 2, 4, 8, ..., 1024
CLK
CLK
INT
INT
FLAG
FLAG
TPM: 16-bit Modulo
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TM
Task Allocation
►Split big task into small fragment
• Most tasks are big and difficult to handle
• Make sure each split task can completed execution within a timing period
►Prioritize Tasks
• Only one task can be executed in one timing period
• The scheduler need input to arbiter the right task to execute while more than
one tasks are pended
High
Priority
AA
BB
EE
FF
CC
GG
3 Tasks:
2 big and 1 small
EE
FF
AA
BB
GG
6 Tasks:
All small
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Low
Priority
CC
6 prioritized Tasks:
3 Level
Green: high Priority
Yellow: middle Priority
Blue: Low Priority
TM
Schedule Tasks after timing ISR
►Schedule task when timing ISR
• ISR is the trigger of every schedule
is completed
►Schedule the pended task with high priority to execute
• The pended task with high priority must be service prior to the one with low
priority
• The tasks with same priority will be scheduled by time order
• No task is scheduled if there is no pended task
High
Priority
EE
FF
AA
BB
EE
FF
AA
BB
CC
GG
CC
GG
Low
Priority
Time Direction
Background
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ISR + Scheduler
TM
An Example of Timing-Based Schedule
►Preliminary Requirements
• To get RMS value of utility power
• 64 times sampling each cycle
• Report Final result to host via UART
110V 60Hz/220V 50Hz
RS08 CPU
10 ms
Trigger/Sample
Timer
CPU
ADC
To host
ADC Sample 50Hz/60Hz × 128
SCI
PMC
Internal Clock
10-MHz BUS
Vaverage =
63
∑V
i =0
2
i
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TM
An Example of Timing-Based Schedule
►Basic
Analysis
60 x 64 = 3840 times ADC samplings per second
• 60 x 64 = 3840 times square and accumulation operations per second
• One square root operation per second
• One UART operation
•
►System
Design
7680Hz (130.2us) Timing
• Start ADC every two timings in timing ISR
• Get ADC value and perform square and accumulation operations in the
next period to the one starting ADC
• For the periods not performing square operation are allocated to
perform square root operation and UART operation
•
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TM
An Example of Timing-Based Schedule
Timing Period =
130.2us
T = 130.2us
T = 130.2us
T = 130.2us
Time Direction
Task to perform square root
and send data via UART
Background
Task to perform square and
accumulation operations
ISR staring ADC sampling
ISR not staring ADC sampling
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TM
Performance
¾ Performance
¾ BUS Frequency: 8-MHz
¾ Base time period: 130us
¾ Scheduler code (Flash): 57 bytes
¾ Scheduler data (RAM): 4 bytes
¾ ISR code (Flash): 16 bytes
¾ ISR data (RAM): 1 byte
¾ Scheduler + ISR execution time: 9us*
¾ Scheduler + ISR execution time:
12.5us
¾ Scheduler + ISR CPU load: 9.6%
¾ Conclusion
¾ Over 90% MIPS are used for
calculation
¾ RS08 core did a real-time schedule
successfully
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TM
Conclusions & FAQ
Select best MCU for your applications
TM
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Select Best MCU for Your Applications
►What best MCU?
• Meeting requirements

•
Never over requirements
Never under requirements
Exact meeting always
Cost acceptable
Never being asked why it costs so
much
Minimized development and
manufacture cost

•
Least development cycle time

•
Always speeding your prototype to
markets
The best MCU always most
suitable to Applications
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TM
What applications does RS08 target
►Applications
Small code density < 12K Bytes
• RAM < 256 Bytes
• No nested interrupt requirement
• A small or empty background loop
•
►Scheduling
State machine
• Time based event applications
• Event base applications
•
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TM
FAQ
►Q
: Why do we need RS08 core when polling mode looks to be able
to be implemented in a traditional CPU?
►A : RS08 core can wake CPU from stop mode but release the
program stream handle to software. A traditional CPU can not use
polling mode as they can not be waken up from stop without
interrupt vector support. And, if vector table is not used, why do you
spend money on it?
►Q
: Does RS08 core have any limitations?
►A : Of course. RS08 has a strong capability to deal with less tasks
(<=6) program. But the polling mode will not always work when the
task becomes more.
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TM
Related Session Resources
Session Location – Online Literature Library
http://www.freescale.com/webapp/sps/site/homepage.jsp?nodeId=052577903644CB
Sessions
Session ID
Title
Demos
Pedestal ID
Demo Title
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TM
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TM
BACKUP
S08 VS RS08
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TM
RS08 Advantages
►Reduced
Code Size
Every S08 vector occupies 2 bytes to store address. S08 uses a fixed
interrupt vector table, 32 × 2 = 64 bytes. At least 6 bytes are needed to
stack current registers when an interrupt occurs.
• Every RS08 polling occupies 3 bytes to store opcode. RS08 supports up
to 16 interrupts, which means up to 16 × 3 = 48 bytes will be used. No
stacking operation is needed in RS08 interrupt mechanism.
•
►Conclusion
•
RS08 uses LESS space than traditional interrupt vector.
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TM
RS08 Advantages
Size for Interrupt
Vector
S08 VS RS08 Size performance
80
60
64
64
64
64
64
64
15
18
40
20
0
3
0
6
9
1
2
12
3
4
5
64
48
16
Interrupt Number
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TM
RS08 Advantages
►Time
Performance
S08 takes at least 11 cycles before entering ISR and at least 9 cycles
after ISR. S08 takes 20 cycles at least to process ISR associated action.
• RS08 takes 5 cycles before entering ISR and 3 cycles after ISR. RS08
takes 5 × Priority + 8 cycles to process ISR associated action.
•
►Conclusion
•
For RS08 uses a software scheduling interrupt vector,

Priority #0, Priority #1, and #2 ISR executions are FASTER than S08 ISR.
Priority #3 or higher ISR executions is SLOWER than S08 ISR.
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TM
RS08 Advantage
S08 VS RS08 Interrupt Latency
BUS cycles
40
30
20
10
20
8
20
13
0
1
20
18
23
20
2
3
33
28
20
20
0
4
5
Number of Interrupt Sources
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TM
Use Cases
►Consider
two cases
Case 1: High priority interrupt with high frequency, Low priority interrupt
with low frequency. Assuming high priority interrupt has double
frequency of adjacent low priority interrupt.
• Case 2: Low priority interrupt with high frequency, High priority interrupt
with low frequency. Assuming high priority interrupt has half frequency
of adjacent low priority interrupt in Case 2. The maximum frequency is
10kHz.
•
►Other
assumption
Assuming there are up to 6 major interrupts used.
Assuming the maximum frequency is 10kHz.
Assuming there are no redundancy in background program except the
scheduler.
• Assuming 10-MHz BUS used for schedule consumption calculation
•
•
•
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TM
Use Cases
RS08 Case 1
RS08 Case 2
S08
Freq
Cycle
Sum
Freq
Cycle
Sum
Freq
Cycle
Sum
Priority #0
10000
8
80000
312.5
8
2500
10000
20
200000
Priority #1
5000
13
65000
625
13
8125
5000
20
100000
Priority #2
2500
21
45000
1250
21
22500
2500
20
50000
Priority #3
1250
26
28750
2500
26
57500
1250
20
25000
Priority #4
625
31
17500
5000
31
140000
625
20
12500
Priority #5
312.5
36
10312.5
10000
36
330000
312.5
20
6250
Total
Percentage
of 10-MHz
BUS
246562.5
2.5%
(37.4%
faster
than
S08)
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560625
5.6%
(42.4%
slower
than
S08)
393750
3.9%
TM
Use Cases
►Conclusion
In the case that high priority interrupt with high frequency, the RS08 gets
MORE efficient than S08 (37.4% faster in the example).
• In the case that high priority interrupt with low frequency, the RS08 gets
LESS efficient than S08 (42.4% slower in the example).
• Less interrupts MORE efficient in RS08
• The only assumption is,
•

No big task executed in background program
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Timebase Event
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Timebase Event
Constant
Time
t
► InfLoop:
►
wait
►
brset SIP1_RTI, MAP_ADDR_6(SIP1), TimeTick
►
brset SIP1_LVD, MAP_ADDR_6(SIP1), Brownout
►
► TimeTick:
►
; ... Code here ...
►
jmp InfLoop
►
► Brownout:
►
; ... Code here ...
►
jmp InfLoop
Wait takes 3 bus cycles to wake up at most
Brset takes 5 bus cycles
At most 8 bus cycles software overhead
At 10MHz bus, 0.8us required.
Application Example
Sensor applications, Low end
power meter
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Timebase with additional Interrupt Handling
Constant
Time
► InfLoop: wait
►
brset SIP1_IIC, MAP_ADDR_6(SIP1), _IIC_ISR
►
brset SIP1_SCI, MAP_ADDR_6(SIP1),
►
►
_SCI_ISR
brset SIP1_RTI, MAP_ADDR_6(SIP1),
_TimeTick
brset SIP1_LVD, MAP_ADDR_6(SIP1),
Brownout
_IIC_ISR: jmp IIC_ISR
_SCI_ISR: jmp SCI_ISR
_TimeTick: jmp TimeTick
Brownout:
; ... Code here ...
jmp InfLoop
►
►
►
►
►
►
►
► IIC_ISR:
►
; ... Code here ...
►
jmp InfLoop
► _SCI_ISR:
►
; ... Code here ...
►
jmp InfLoop
►
► _TimeTick:
►
; ... Code here ...
►
jmp InfLoop
Asynchronous
Interrupt
t
Software defines interrupt priority
At 10MHz,
IIC_SIR takes 1.2us to response (including JMP)
SCI_ISR takes 1.7us to response (including JMP)
Application Example
Sensor applications, Low end power
meter, mouse, home applicants,
remote control
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Linear Coding
Constant
Time
ISR execution
t
►If
you are forced to use linear code, i.e. CPU bandwidth is reaching
100%, pending interrupt can be checked in regular manner.
Int_Check: MACRO
tst
beq
jsr
ENDM
SIP1
*+5
Handle_interrupt
Handle_Interrupt:
brset SIP1_IIC, MAP_ADDR_6(SIP1), IIC_ISR
brset SIP1_SCI, MAP_ADDR_6(SIP1), SCI_ISR
brset SIP1_LVD, MAP_ADDR_6(SIP1), Brownout
rts
Brownout:
; ... Code here ...
bra Handle_Interrupt
IIC_ISR:
; ... Code here ...
bra Handle_Interrupt
SCI_ISR:
; ... Code here ...
bra Handle_Interrupt
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Skills used in Demo
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Programming Skills in The Demo
►Inline
•
Technology
Inline ISR makes the RS08 program smaller and more efficient.
►Software
•
Software defined ISR priorities make RS08 program more flexible.
Hardware defined ISR priorities are inhibited by the IC maker.
►Quick
•
defined ISR priorities
Polling Mode
Quick polling mode ensure that the interrupt with highest priority will be
responded prior to the others.
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MISC
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9RS08KA2
• Supply Voltage / Performance
• 1.8-5.5V
1K/2K
SIM
Flash
Analog
• Core
Comp
• Memory
BDC
8-bit
63
bytes
RAM
ICS
KBI
RS08
Core
COP
Modulo
Timer
• RS08 Core
• 1K / 2K bytes Flash
• 63 bytes RAM
• Analog Comparator
• Full rail-to-rail supply operation, can operate in STOP mode
• Features/ Benefits
• Computer operating properly feature (COP)
• Integrated Clock Source (ICS) up to 10MHz internal bus operation with
2% deviation over full temperature and voltage range
• 8-bit Modulo Timer
• 3 / 5 channel keyboard interrupt (KBI)
• LVD (low voltage detect) with reset or stop wakeup
• External Vpp required for Flash programming
• Auto wakeup
• Target Package
• 6 pin DFN, 8 pin narrow body SOIC, 8PDIP
• Development Tools/ Documentation
• Similar to existing S08 platform
• Target Applications:
• Small appliance, toys, simple analog comparator / simple logic
replacement, HB-LED
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A Typical Scheme of Timing Based Schedule
Tasks
Prioritized Tasks
Status
Next Status
Next 2nd Status
Dotted tasks will not be
executed in current
available interval
Interrupt
Interrupt
Service
Routine
Task
Priority
Schedule
Task
schedule
being
executed
Time
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of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners. © Freescale Semiconductor, Inc. 2008.
TM