Workshop How to Design a XILINX Connectivity System in 1 Day

Workshop How to Design a XILINX
Connectivity System in 1 Day
This workshop is an introduction to the concepts and
techniques used for high bit rate communication channels
and how these can be implemented in a XILINX FPGA.
In particular, the basic behaviour of Gigabit-Transceiver
channels will be discussed as well as PCI Express techno­
logy (PCIe), memory interfaces and the Ethernet MAC.
The goal of this workshop is to teach the fundamental
knowledge of the above concepts. Consequently, the
theory is kept to its strict minimum necessary. For further
and complementing in-depth information, please see the
­relevant specialty classes.
The design examples and exercises are taken from the target reference design (TRD). Moreover, an IBERT (Integrated Bit Error Ratio Tester) based exercise is provided
to demonstrate the usage of MultiGigabit-Transceiver
(MGT) technology.
Applicable technologies
Current FPGA families
Knowledge in VHDL/ Verilog (see “Compact VHDL/
Verilog” or “Professional VHDL”)
Experience in implementing FPGAs using XILINX tools
Basic understanding of analog and digital design
Duration and Cost
1 day, € 650,- net per person including detailed
training material, drinks in the breaks and lunch
Transceiver Overview
nn Introduction
nn Transceiver Basics
nn GTP Transceiver Overview
nn GTX Transceiver Differences
nn Transceiver Block Usage
Ethernet MAC Overview
nn Introduction
nn Ethernet Basics
nn Ethernet MAC Core Usage
nn Further Ethernet IP Cores
PCI Express Technology Overview
nn Introduction
nn PCIe Technology Basics
nn PCIe Block
nn PCIe Block Usage
AXI IP Interface Overview
nn Introduction
nn AXI Details
nn AXI Usage
nn Example AXI Systems and Subsystems
Memory ­Interfaces Overview
nn Introduction
nn Memory Devices Overview
nn Memory Interface Design
nn Memory Interface Usage
Connectivity Targeted ­Reference Design (TRD)
nn Introduction
nn Connectivity in XILINX FPGAs
nn TRD Overview
nn Usage Options
nn ChipScope Pro Serial I/O Toolkit