Layouts
...Or How to Become an Electronic Artist...
Anurup Mitra
BITS Pilani
January 2007
Anurup Mitra
Layouts
Blackboard Demo
Read the Title!
Anurup Mitra
Layouts
Cross-Section Versus Layout
Anurup Mitra
Layouts
A Better Inverter Layout
Anurup Mitra
Layouts
A D–Flip-Flop Layout
Anurup Mitra
Layouts
A Microprocessor Layout
Anurup Mitra
Layouts
DRC
DRC is a Design Rule Check.
Anurup Mitra
Layouts
DRC
DRC is a Design Rule Check.
There are various tolerances involved in each step of processing
during the course of fabrication of a chip.
Anurup Mitra
Layouts
DRC
DRC is a Design Rule Check.
There are various tolerances involved in each step of processing
during the course of fabrication of a chip.
To avoid catastrophic failures in the layout, a set of rules need to
be met. These rules minimise improper device and interconnect
fabrication, thus potentially increasing the yield.
Anurup Mitra
Layouts
DRC
DRC is a Design Rule Check.
There are various tolerances involved in each step of processing
during the course of fabrication of a chip.
To avoid catastrophic failures in the layout, a set of rules need to
be met. These rules minimise improper device and interconnect
fabrication, thus potentially increasing the yield.
Analog layouts demand many more layout precautions not required
by DRC, to minimise factors like noise and mismatch.
Anurup Mitra
Layouts
Categories of Design Rules
Most design rules can be classified under one of 4 Minimum
Condition categories:
Anurup Mitra
Layouts
Categories of Design Rules
Most design rules can be classified under one of 4 Minimum
Condition categories:
Width A minimum width constraint on geometries is
imposed by lithographic and processing capabilities.
Anurup Mitra
Layouts
Categories of Design Rules
Most design rules can be classified under one of 4 Minimum
Condition categories:
Width A minimum width constraint on geometries is
imposed by lithographic and processing capabilities.
Spacing Two lines too close together might cause an
inadvertent short.
Anurup Mitra
Layouts
Categories of Design Rules
Most design rules can be classified under one of 4 Minimum
Condition categories:
Width A minimum width constraint on geometries is
imposed by lithographic and processing capabilities.
Spacing Two lines too close together might cause an
inadvertent short.
Enclosure To ensure that contacts remain within the layers they
are joining, or that an n-well or n+/p+ implant
completely surrounds a device.
Anurup Mitra
Layouts
Categories of Design Rules
Most design rules can be classified under one of 4 Minimum
Condition categories:
Width A minimum width constraint on geometries is
imposed by lithographic and processing capabilities.
Spacing Two lines too close together might cause an
inadvertent short.
Enclosure To ensure that contacts remain within the layers they
are joining, or that an n-well or n+/p+ implant
completely surrounds a device.
Extension Some geometries need to extend beyond the edge of
others to provide margin for error, e.g. poly overhang
of diffusion/active.
Anurup Mitra
Layouts
Device Capacitances
Blackboard Digression again!
Anurup Mitra
Layouts
Summary of Gate Device Caps
Capacitance
Cgb
Cgs
Cgd
Cg
Cutoff
Cox WL
0
0
Cox WL
Linear
0
1
2 Cox WL
1
2 Cox WL
Cox WL
Anurup Mitra
Saturation
0
2
3 Cox WL
0
2
3 Cox WL
Layouts
Summary of Device Junction Caps
φ0 = VT ln NAnN2 D
i
−mj
Cj = Cj0 1 + Vφxb0
−mjsw
Cjsw = Cjsw 0 1 + Vφxb0
mj and mjsw are called junction grading coefficients and are in the
range 0.33 and 0.5 depending upon the junction profile. Also note
that Vxb can refer to either the source-bulk or drain-bulk junction.
Anurup Mitra
Layouts
Summary of Device Junction Caps
φ0 = VT ln NAnN2 D
i
−mj
Cj = Cj0 1 + Vφxb0
−mjsw
Cjsw = Cjsw 0 1 + Vφxb0
mj and mjsw are called junction grading coefficients and are in the
range 0.33 and 0.5 depending upon the junction profile. Also note
that Vxb can refer to either the source-bulk or drain-bulk junction.
The total junction capacitance for each active pocket is thus given
by:
Cjunction = AX .Cj + PX .Cjsw
where Cj has units of capacitance/area and Cjsw has that of
capacitance/length.
Anurup Mitra
Layouts
LVS
LVS stands for Layout versus Schematic
Anurup Mitra
Layouts
LVS
LVS stands for Layout versus Schematic
The layout editor aids the drawing of multicoloured polygons.
These remain merely geometric patterns unless specifically
translated into an equivalent circuit.
Anurup Mitra
Layouts
LVS
LVS stands for Layout versus Schematic
The layout editor aids the drawing of multicoloured polygons.
These remain merely geometric patterns unless specifically
translated into an equivalent circuit.
A CAD tool can convert these geometric patterns into the electrical
devices that they signify. This process is known as extraction.
Anurup Mitra
Layouts
LVS
LVS stands for Layout versus Schematic
The layout editor aids the drawing of multicoloured polygons.
These remain merely geometric patterns unless specifically
translated into an equivalent circuit.
A CAD tool can convert these geometric patterns into the electrical
devices that they signify. This process is known as extraction.
Along with device extraction, the tool also extracts parasitic
capacitances and resistances due to interconnects and device
geometries. This also implies that in general a circuit becomes
slower on layout, and a correction for this needs to be made at the
schematic design stage.
Anurup Mitra
Layouts
LVS
LVS stands for Layout versus Schematic
The layout editor aids the drawing of multicoloured polygons.
These remain merely geometric patterns unless specifically
translated into an equivalent circuit.
A CAD tool can convert these geometric patterns into the electrical
devices that they signify. This process is known as extraction.
Along with device extraction, the tool also extracts parasitic
capacitances and resistances due to interconnects and device
geometries. This also implies that in general a circuit becomes
slower on layout, and a correction for this needs to be made at the
schematic design stage.
Once the CAD tool has extracted the electrical equivalent of the
polygons, it compares the circuits got from schematic and layout to
check that they are electrically equivalent. This is known as LVS.
Anurup Mitra
Layouts
Analog Layout Requirements
Multifingered transistors reduce the parasitic capacitance of
the device with the substrate. This can be a critical issue
when speed (read bandwidth) is a crucial parameter in the
design.
Anurup Mitra
Layouts
Analog Layout Requirements
Multifingered transistors reduce the parasitic capacitance of
the device with the substrate. This can be a critical issue
when speed (read bandwidth) is a crucial parameter in the
design.
Common Centroid Geometry is important to reduce mismatch
in circuits resulting out of process variations.
Anurup Mitra
Layouts
Analog Layout Requirements
Multifingered transistors reduce the parasitic capacitance of
the device with the substrate. This can be a critical issue
when speed (read bandwidth) is a crucial parameter in the
design.
Common Centroid Geometry is important to reduce mismatch
in circuits resulting out of process variations.
Adequate vias and substrate contacts need to be used to
ensure good connectivity and reduce resistance and junctions
of different layers.
Anurup Mitra
Layouts
Analog Layout Requirements
Multifingered transistors reduce the parasitic capacitance of
the device with the substrate. This can be a critical issue
when speed (read bandwidth) is a crucial parameter in the
design.
Common Centroid Geometry is important to reduce mismatch
in circuits resulting out of process variations.
Adequate vias and substrate contacts need to be used to
ensure good connectivity and reduce resistance and junctions
of different layers.
Supply and ground rails should be made to run parallel as far
as possible.
Anurup Mitra
Layouts
Analog Layout Requirements
Multifingered transistors reduce the parasitic capacitance of
the device with the substrate. This can be a critical issue
when speed (read bandwidth) is a crucial parameter in the
design.
Common Centroid Geometry is important to reduce mismatch
in circuits resulting out of process variations.
Adequate vias and substrate contacts need to be used to
ensure good connectivity and reduce resistance and junctions
of different layers.
Supply and ground rails should be made to run parallel as far
as possible.
Sensitive signal nodes have to be shielded against interference.
Anurup Mitra
Layouts
Analog Layout Requirements
Multifingered transistors reduce the parasitic capacitance of
the device with the substrate. This can be a critical issue
when speed (read bandwidth) is a crucial parameter in the
design.
Common Centroid Geometry is important to reduce mismatch
in circuits resulting out of process variations.
Adequate vias and substrate contacts need to be used to
ensure good connectivity and reduce resistance and junctions
of different layers.
Supply and ground rails should be made to run parallel as far
as possible.
Sensitive signal nodes have to be shielded against interference.
Sensitive circuitry needs to be shielded with guard rings
consisting of substrate ties and n-well.
Anurup Mitra
Layouts
Multifingered Transistors
Given above are examples where a single transistor is broken up
into multiple fingers. This provides a convenient aspect ratio and
saves area.
Anurup Mitra
Layouts
Multifingered Transistors
Given above are examples where a single transistor is broken up
into multiple fingers. This provides a convenient aspect ratio and
saves area.
Most importantly however, this form of layout reduces junction
capacitance by upto 50%.
Calculate the junction caps for each of the above configurations
and compare.
Anurup Mitra
Layouts
Even Number of Digits
As a general rule, the drain cap has more effect on circuit
performance than does the source cap. So an effort should be
made to reduce the former.
Anurup Mitra
Layouts
Common Centroid Geometry
Similar environments have to be created for matched transistors to
prevent mismatch between them. Common centroid geometry is
used to do this.
Anurup Mitra
Layouts
Common Centroid Geometry
Similar environments have to be created for matched transistors to
prevent mismatch between them. Common centroid geometry is
used to do this.
Process gradients during fabrication can occur in any direction or
orientation. Matched transistors should be laid out in a manner
such that both transistors are affected equally by any process
gradient.
Anurup Mitra
Layouts
Passives in CMOS Technology
The implementation of passive devices poses a challenge because
modern CMOS technology is almost exclusively tailored to improve
digital processing.
Anurup Mitra
Layouts
Passives in CMOS Technology
The implementation of passive devices poses a challenge because
modern CMOS technology is almost exclusively tailored to improve
digital processing.
It takes approximately two years for a process to mature enough to
be able to build high quality passives.
Anurup Mitra
Layouts
Passives in CMOS Technology
The implementation of passive devices poses a challenge because
modern CMOS technology is almost exclusively tailored to improve
digital processing.
It takes approximately two years for a process to mature enough to
be able to build high quality passives.
This is significant because by that time Moore’s Law ushers in the
next generation of digital process!
Anurup Mitra
Layouts
Resistors
The resistance of any conductor is given by
L
R = ρ Wt
Anurup Mitra
Layouts
Resistors
The resistance of any conductor is given by
L
R = ρ Wt
Since the thickness of the conductor for a given process is not
under the designer’s control, it is absorbed into the resistivity and
a new standard factor called sheet resistance is used to define the
intrinsic resistance of conductor.
Anurup Mitra
Layouts
Resistors
The resistance of any conductor is given by
L
R = ρ Wt
Since the thickness of the conductor for a given process is not
under the designer’s control, it is absorbed into the resistivity and
a new standard factor called sheet resistance is used to define the
intrinsic resistance of conductor.
L
R = RS W
where RS =
ρ
t
Anurup Mitra
Layouts
Resistors
The resistance of any conductor is given by
L
R = ρ Wt
Since the thickness of the conductor for a given process is not
under the designer’s control, it is absorbed into the resistivity and
a new standard factor called sheet resistance is used to define the
intrinsic resistance of conductor.
L
R = RS W
where RS =
ρ
t
Although L/W is dimensionless, it is given the fictitous unit of
squares, denoted by .
Anurup Mitra
Layouts
Resistors
The resistance of any conductor is given by
L
R = ρ Wt
Since the thickness of the conductor for a given process is not
under the designer’s control, it is absorbed into the resistivity and
a new standard factor called sheet resistance is used to define the
intrinsic resistance of conductor.
L
R = RS W
where RS =
ρ
t
Although L/W is dimensionless, it is given the fictitous unit of
squares, denoted by . Thus sheet resistance has the unit of
ohms/square or Ω/.
Anurup Mitra
Layouts
Resistors
The resistance of any conductor is given by
L
R = ρ Wt
Since the thickness of the conductor for a given process is not
under the designer’s control, it is absorbed into the resistivity and
a new standard factor called sheet resistance is used to define the
intrinsic resistance of conductor.
L
R = RS W
where RS =
ρ
t
Although L/W is dimensionless, it is given the fictitous unit of
squares, denoted by . Thus sheet resistance has the unit of
ohms/square or Ω/.
Due to photolithographic and etching imperfections, lateral
diffusions and variations in film thickness, integrated resistors show
as much as ±20% tolerance.
Anurup Mitra
Layouts
Capacitors
Capacitors are even more real-estate intensive than resistors and it
is not possible to fabricate more than a few hundred picofarads on
chip.
Anurup Mitra
Layouts
Capacitors
Capacitors are even more real-estate intensive than resistors and it
is not possible to fabricate more than a few hundred picofarads on
chip.
A few of the ways in which caps can be made are:
Using a MOS device (with careful biasing!)
Anurup Mitra
Layouts
Capacitors
Capacitors are even more real-estate intensive than resistors and it
is not possible to fabricate more than a few hundred picofarads on
chip.
A few of the ways in which caps can be made are:
Using a MOS device (with careful biasing!)
Spreading thinox over heavily doped diffusion (with ONO as
the dielectric)
Anurup Mitra
Layouts
Capacitors
Capacitors are even more real-estate intensive than resistors and it
is not possible to fabricate more than a few hundred picofarads on
chip.
A few of the ways in which caps can be made are:
Using a MOS device (with careful biasing!)
Spreading thinox over heavily doped diffusion (with ONO as
the dielectric)
Employing a poly-poly sandwich
Anurup Mitra
Layouts
Latchup
CMOS circuits are subject to a phenomenon called latchup.
Anurup Mitra
Layouts
Latchup
CMOS circuits are subject to a phenomenon called latchup.
A parasitic bipolar circuit is formed as shown in the figure above.
Note that the base of each transistor is tied to the collector of the
other.
Anurup Mitra
Layouts
Latchup
CMOS circuits are subject to a phenomenon called latchup.
A parasitic bipolar circuit is formed as shown in the figure above.
Note that the base of each transistor is tied to the collector of the
other. R1 and R2 are the resistances associated with the n-well and
substrate.
Anurup Mitra
Layouts
Latchup
CMOS circuits are subject to a phenomenon called latchup.
A parasitic bipolar circuit is formed as shown in the figure above.
Note that the base of each transistor is tied to the collector of the
other. R1 and R2 are the resistances associated with the n-well and
substrate.
This is a positive feedback circuit. At latchup this circuit will draw
a tremendous amount of current from VDD on account of both
transistors being on.
Anurup Mitra
Layouts
Latchup
CMOS circuits are subject to a phenomenon called latchup.
A parasitic bipolar circuit is formed as shown in the figure above.
Note that the base of each transistor is tied to the collector of the
other. R1 and R2 are the resistances associated with the n-well and
substrate.
This is a positive feedback circuit. At latchup this circuit will draw
a tremendous amount of current from VDD on account of both
transistors being on. Both circuit designers and process engineers
need to take care to see that the loop gain if this circuit stays
below unity.
Anurup Mitra
Layouts