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PCB POWER
How to power motherboards
under ACPI control
By Reno Rossetti
Director of IC Group Strategy
Fairchild Semiconductor
At the highest level of powermanagement techniques is Advanced Configuration and Power
Interface (ACPI), an open-industry
specification jointly developed by
Compaq, Intel, Microsoft, Phoenix
and Toshiba. ACPI establishes
industry-standard interfaces for
OS-directed configurations and
power management for laptops,
desktops and servers. ACPI power
ICs take the available voltages
from the “silver box” or AC adapter
and, under specific OS commands
received via logic inputs, translate
them into useful system voltages
on the motherboard.
This specification enables
new power-management technologies to evolve independently in operating systems
and hardware, ensuring that
they continue to work together.
While the PC silver box provides
5-, 3.3- and 12V, the motherboards necessitate additional
voltages beyond the popular
VRM/VRD CPU voltage regulators. This article discusses how
to efficiently provide most motherboard voltages, such, as 3.3V
dual, 5V dual, DDR memory voltages (V ddq and V tt -DDR2) and
Vtt-CPU/IO under ACPI control.
Table 1 shows the main ACPI
commands. In the working state
S0 (PWR_OK=1) all the voltages,
mains (3.3-, 5- and 12V) and 5V
standby provided by the silver
box, as well as the rest of the
voltages generated locally on the
Power OK
S3#
S5#
Main
5&3.3V
Dual
DRAM
State
0
0
0
Off
On
Off
S5:soft off
0
0
1
Off
On
On
S3: suspend to
RAM
1
x
x
On
On
On
S0: working state
Table 1: In the working state S0 (POWER_OK=1) all the voltages, mains (3.3-, 5- and 12V) and 5V standby provided by
the silver box, as well as the rest of the voltages generated locally on the motherboard, are present.
12Vmain
SW1
1.2V VCPU
FAN5019
SW2
Graphics VCPU 1.25V
FAN6520A
3.3Vmain
SS1
5Vstandby
SL1
PCI Express, ICH8: (3.3Vdual)
SL
SL
SS2
SW3
0.9V DDR VTT
1.9V DDR Vddq
5Vmain
SS3
DDR Vin (5Vdual)
Controller
FAN5068
1.2V VTT for CPU, I/O
S3#
S5# (EN)
SS = Switch
SL = Linear regulator
SW = Switching
Figure 1: While the CPU and the graphics receive power only during the working state, the rest of the functions are
powered by voltages obtained by means of the best combinations of main and standby power sources.
motherboard are present.
S3 (S3# is the “negate” of S3)
or suspend to RAM is a sleeping
state in which the mains are off
and the memory is placed in a
low-power autorefresh or selfrefresh state. In this state, the
residual voltages alive on the
motherboard draw power from
the 5V standby power supply line
coming from the silver box.
S5 or Soft Off is a virtually off
state in which no system contest
is maintained, but some residual
power is still available to allow for
transition to the working state S0.
Powering motherboard
Figure 1 shows the strategy for
powering the motherboard. While
the CPU and the graphics receive
power only during the working
state, the rest of the functions,
like PCI Express, I/O channel hub
(ICH8) and DDR memory, are
powered by voltages obtained
by means of the best combinations of main and standby power
sources that assure functionality
under ACPI with minimum power
dissipation.
The switch symbols in Figure
1’s stick diagram represent either
a true MOSFET switch (SSx) or a
linear regulator (SLx) or a switching regulator (SWx).
In S3 state, the 5V standby provides power to the DDR memory
via the switch SS1 (a p-channel
MOSFET transistor) while SS2 is
open, cutting off the 5V main.
Accordingly, this intermediate
voltage is called 5V dual. Subsequently, the buck converter SW1
will convert the 5V down to 1.8V,
with the necessary voltage powering the DDR memory module.
This 1.8V will also be used via the
linear regulators SL1 and SL2 to
produce the termination voltages
for the DDR memory (0.9V) and
the CPU (1.2V).
In S5 states, the buck converter SW1 will be powered off, withdrawing auxiliary power from the
Electronic Engineering Times-Asia | September 1-15, 2006 | eetasia.com
ations over power consumption
minimization.
The FAN5068 has all the circuits necessary for powering
DDRx memory systems. Integrated in this single IC are both
the switcher controller for Vddq
and a linear controller for V tt
termination voltage. The switcher
for Vddq runs off 5V dual, while
the linear regulator for Vtt runs
from the Vddq power.
The FAN5068 also provides
the control logic necessary for
the two external switches, SS2
and SS3, which implement the
5V dual supply voltage, as well
as a linear regulator used for the
implementation of 1.2V termination for the CPU.
Finally, Figure 3 shows the
motherboard real estate corresponding to the FAN5068
ACPI/DDR power supply. The
controller IC, characteristically
square-shaped (24-pin, 5 x 5 MLP
package), is highlighted in the
white ring. Around the controller
IC, the discrete transistors and
passive components, particularly
the bulky 1.8µH inductor and the
output electrolytic capacitors, are
noticeable.
Figure 2: All the voltages under ACPI can be generated and controlled by a single multifunction controller chip, such
as Fairchild’s FAN5068, in conjunction with a few discrete transistors.
Figure 3: Around the controller IC,
the discrete transistors and passive
components are noticeable.
DDR memory. In this state, only
3.3V dual remains alive, receiving
power from the 5V standby via
the linear regulator SL3, with the
switch SS3 open, cutting off the
power from the 5V main.
ACPI controller
All the voltages under ACPI can
be generated and controlled by
a single multifunction controller
chip, such as Fairchild’s FAN5068,
in conjunction with a few discrete
transistors (Figure 2). Table 2
lists the main components of the
BOM, including the controller IC,
discrete transistors and main passive components.
At the heart of the controller
is the logic block implementing
the ACPI control, as well as all the
voltage regulation circuitry. The
application circuit in Figure 1 is
customized to DDR2 memories.
Compared to the older DDR,
the DDR2 power supply Vddq is
reduced from 2.5V down to 1.8V
and Vtt from 1.25V down to 0.9V.
Accordingly, DDR2 memories end
up consuming much less than
the first-generation DDR.
For example, a DDR2-533
ends up consuming roughly
half of a DDR-400. The termination scheme for DDR2 is slightly
different from the one for DDR
and the termination resistors
are on-chip, not on the motherboard. However, an external
Vtt termination voltage is still
necessary. At the much lower
levels of DDR2 power consumption, linear regulators for Vtt can
be used, especially if simplicity
and cost are prevailing consider-
Electronic Engineering Times-Asia | September 1-15, 2006 | eetasia.com
Description
Qty
Reference
Vendor
2
C13, C14,
Fujitsu
FP-6R3RE821M-SU
Capacitor 820µF, 20%, 6.3V,
MBZ, 8X11.5
4
C1,C7,C12,C15
Rubycon
6.3MBZ820M8X11.5
Capacitor 1µF, 10%,
16VDC, X7R, 1206
2
C2, C4
KEMET
C1206C105K4RACTU
Capacitor 820µF , 2.5V,
PSA, 8X11.5, 7mΩ
3
C16, C17, C20
Nippon
Chemicon
PSA2.5VB820MH11
IC System Regulator,
MLP24Pin_5X5, FSID:
FAN5068
1
U2
Fairchild
FAN5068
1
L1
InterTechnical
SC5018-1R8M
Inductor 0.47µH, 2.8mΩ,
15A, 20%, 0.25" SMD
1
L2
InterTechnical
SC7232-R47M
MOSFET N-CH, 8.8
mΩ, 30V, 50A, D-PAK,
FSID: FDD6296
1
Q1
Fairchild
FDD6296
MOSFET N-CH, 6mΩ,
30V, 75A, D-PAK, FSID:
FDD6606
1
Q2
Fairchild
FDD6606
MOSFET N-CH, 21mΩ,
20V, 36A, D-PAK, FSID:
FDD6512A
2
Q3, Q6
Fairchild
FDD6512A
MOSFET P-CH, 35mΩ,
-20V, -5.5A, SSOT-6,
FSID: FDC602P
1
Q4
Fairchild
FDC602P
MOSFET N-CH, 24mΩ,
20V, 6.2A, SSOT-6, FSID:
FDC637AN
1
Q5
Fairchild
FDC637AN
MOSFET N-CH, 4Ω,
25V, SOT23, FSID:
FDV301N
2
Q7, Q8
Fairchild
FDV301N
Capacitor 820µF, 20%, 6.3V,
FPCAP, 10X12.5, 7mΩ
Inductor 1.8µH,
3.24mΩ, 16Å, 20%
0.5"
,
Part number
Table 2: Listed are the main components of the BOM, including the controller
IC, discrete transistors and main passive components.
A separate VRD (voltage regulator down the motherboard)
will be necessary for the CPU.
For example, Fairchild’s chipset
FAN5019 PWM controller and
FAN5009 driver ICs are recommended for VRM10 class of moth-
erboards, while a buck converter
like the FAN6522A will power the
graphics card.
ACPI power management—in
conjunction with on-board implementation of effective voltage
regulation schemes that skillfully
use a combination of linear regulators, switching regulators and
saturated pass transistors—produce a best-in-class power management scheme that yields optimum power distribution with low
power dissipation at minimum
cost. In the example discussed in
this article, all the power sources
under ACPI are controlled by a
single multifunction IC, and only
two other regulator controller ICs
are necessary to power the entire
motherboard.
Electronic Engineering Times-Asia | September 1-15, 2006 | eetasia.com