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The University of Jordan
Digital Electronics
Sample Questions
Eng. Bashar Haddad
Sample Exam 2
References:
Electronic circuit and analysis, 2nd edition. Donald Neamen.
Digital Electronics Principles, Devices and applications, 1st edition. Anil K. Maini
Digital Electronics
Sample Exam 2
Eng. Bashar Haddad
For all questions consider the following parameters if not others mentioned:
β=100, βR=0.2, VCE(sat)=0.2, VBE=VBE(sat)=0.6, VBC(sat)=0.8
Forward Barrier voltage of Diode Vb=0.6 volt.
Question #1: TTL inverter
BR = 0.1, BF = 30, VBE(OFF) < 0.5V, VBE(ON) = 0.7V,
VCE(sat) = 0.2V, τS = 10 ns, R1 = 1kΩ.
Vcc = 5V.
a. Find VIL
b. Find IIL @ Vi = VIL
c. Find VIH
d. Find IIH @ Vi = VIH
e. IB2F @ Vi = VIH
f. IB2(EOS) @Vi = VIH
Question #2: TTL Nand Gate
VBE(Sat) = 0.7V, VCE(Sat) = 0.2V, BF = 20, BR = 0.2, VD1(On) =
VD2(on) = 0.3V, VD3(on) = 0.7V
a. Find IIL if Vi = 0.2V and both inputs are low.
b. Find IIH if Vi = 3V and both inputs are high.
c. Find Io(Max) @ Vi = 3V.
d. Find Io(Max) @ Vi = 0.2V and Vo = 3V.
e. Find Fan Out Low with worst case input condition.
f. Find Fan Out High for Vo = 3V.
Question #3: TTL Gate
B = 50, BR = 0, VCE(sat) = 0.2V, VBE(on) = 0.7V, VBE(Off) < 0.5V, VD(on) = 0.7V, VD(off) = < 0.7V
a. Find VIL.
b. Find IIL, if Vi1 = 0.1V and Vi2 = 0.1V.
c. Find IIL, if Vi1 = 0.1V and Vi2 = 5V.
d. Find VIH (Minimum).
e. Find Io(MAX) if Vi1 = Vi2 = 5V (Do not neglect RB3 and RC3).
f. Find Io(MAX) if Vi1 = 0.1V, Vi2 = 5V (Do not neglect RB3 and RC3).
g. Find Fan Out Low with conditions of part b. and part f.
The University of Jordan
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Digital Electronics
Sample Exam 2
Eng. Bashar Haddad
Question #4: DTL gate. VBE(cut-in) = 0.5V, VBE(Sat) = 0.7V, VCE(Sat) = 0, B = 20,
VD(on) = 0.7V.
a. Find VIL.
b. Find VIH for Io = 0, and one input high.
c. Repeat part B for both inputs high and Io = 10mA.
d. What is the Fan Out for the output low state?
e. What is the Fan Out for the output High State driving similar gates with
the input conditions (VIH) of part B.
Question #5: TTL Gate
VCE(sat) = 0.2V, VD(ON) = VBE(On) = 0.7V, VBE(off) < 0.5V, BR = 0.5V,
BF = 20.
a. Find VIL (maximum).
b. Find the worst case IIL when Vi = 0.3V.
c. Find Vo when Vi1 = Vi2 = 0V and Io = +5mA
d. Find the Maximum Io if Vi1 = 3V and Vi2 is open circuited.
e. What would the fan out to be for the conditions of part B
combined with part D.
Question #6: TTL Gate
The output of the TTL gate shown is accidentally
shorted to ground. Determine the short circuit
current when: B = 20, VD(on) = 0.7V, VCE(Sat) = 0.2V,
VBE(on) = 0.7V
a. All inputs are at logic "1"
b. At least one input is at logic "0"
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Digital Electronics
Sample Exam 2
Eng. Bashar Haddad
Question #7: Fan Out:
The inverter shown has the following parameters: BF = 25, BR = 0.5,
VCE(sat) = 0.3V, VD(on) = 0.7V, VBE(sat) = 0.7V, VBE(off) < 0.7V.
a. Determine the maximum VI and the associated II for a Vo = 5V
where Q2 is off.
b. Determine IE1 ad IB2 for VI = 3 to 5 Volts.
c. Determine the logic "0" fan out to N identical gates where VI =
5V and Vo equals the voltage value calculated for VI in part A.
d. Determine the logic "1" fan out to N identical gates when VI = 0
and Vo = 3V.
Question #8: DTL Gate
VBE(on) = 0.7V, VBE(off) < 0.5V, VCE(sat) = 0.2V, B = 10, VD(On) = 0.2V
a. Find VIL.
b. Find IIL worst case @ VI = 0V (Hint: Q1 = sat)
c. Find VIH
d. Find IIH at VI = 5V
e. Find IB2 when VI1 = VI2 = 5V
Question #9: TTL Gate. VCE(sat) = 0.2V, VD(ON) = VBE(on) =
0.7V, VBE(off) < 0.5V, BL (lateral) = 1, BF = 20, BR = 0.5.
a. Find VIL
b. Find VIH
c. Determine the states of each of the four
transistors when all inputs are at a logic one.
d. Find Io when the output is shorted to ground and
the conditions of Part C are applied.
e. Determine the states of each of the four
transistors when at least one of the inputs is at logic
zero.
f. Find Io when the output is shorted to ground and
the conditions of part E are applied.
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Digital Electronics
Sample Exam 2
Eng. Bashar Haddad
Question #10: for the following circuit:
a. What is the logical function of this circuit?
b. Find the state of each transistor and diode for
all the possible inputs.
c. Why D1, D2, D3 are added?
d. Why R3, R5 are added?
e. Redesign the circuit to achieve higher fan out?
Question #11: for the following circuit:
a. What is the logical function of this circuit?
b. The pair transistors T3, T4 called the Darlington pair
transistors, what are the basic advantages of used this
construction?
c. Another construction called the squaring network:
Redesign the circuit to add this network?
Why this network used?
d. Discuss the basic difference between the low power and
the high power TTL circuit?
e. Discuss the problem of entering the deep saturation?
f. How we can solve this problem?
Question #12:
A very important concept to understand in digital circuitry is the
difference between current sourcing and current sinking. For
instance, examine this TTL inverter gate circuit, connected to a
load: The output circuitry of this particular gate is commonly
referred to as "totem-pole". Is a gate circuit with a totem-pole
output stage able to source load current, sink load current, or do
both?
The University of Jordan
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Digital Electronics
Sample Exam 2
Eng. Bashar Haddad
Question #13:
Totem-pole TTL gates usually differ greatly in their maximum source current versus maximum sink
current (IOH versus IOL). Identify which current rating is usually greater, and also explain why this is.
Question #14:
A very important concept to understand in digital circuitry is
the difference between current sourcing and current sinking.
For instance, examine this open-collector TTL inverter gate
circuit, connected to a load: Open-collector gates are
specially designated in their schematic symbols by a marker
within the gate shape:
Is this gate circuit able to source load current, sink load
current, or do both?
Question #15: Predict how the operation of this logic gate
circuit will be affected as a result of the following faults.
Consider each fault independently (i.e. one at a time, no
multiple faults)
• Diode D1 fails open.
• Diode D1 fails shorted.
• Diode D2 fails open.
• Resistor R1 fails open.
• Resistor R2 fails open.
• Resistor R4 fails open.
For each of these conditions, explain why the resulting effects
will occur.
Question #16:
Explain why it is generally a very bad design practice to connect the outputs of different logic gates
together, like this:
The University of Jordan
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Digital Electronics
Sample Exam 2
Eng. Bashar Haddad
Question #17:
In high-speed digital circuits, a very important logic gate parameter is propagation delay: the delay
time between a change-of-state on a gate's input and the corresponding change-of-state on that gate's
output. Explain what causes propagation delay in logic gates. Why isn't the change in output state
instantaneous when an input changes states?
Question #18:
Logic gates are limited in the number of gate inputs which one output
can reliably drive. This limit is referred to as fan-out:
Explain why this limit exists. What might happen if this limit is
exceeded?
Question #19:
An important parameter of logic gate circuitry is noise margin. What exactly is "noise margin," and how
is it defined for logic gates?
Question # 20:
A basic subfamily of TTL circuits is the schottky TTL
family.
a. What are the basic differences between
schottky diode and the normal diode?
b. Why schottky transistors are used instead the
normal transistors in TTL circuits?
c. Using schottky transistors instead of normal
transistors will affect which of the circuit
characteristics power dissipation or
propagation delay?
d. Why transistor Q5 is not replaced by a
schottky transistor?
e. What is the combination (R6-Q6-R4) called and why it used?
The University of Jordan
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Digital Electronics
Sample Exam 2
Eng. Bashar Haddad
Question #21: Open Collector
An open collector gate in TTL is one that is
without a totem-pole output stage. The output
stage in this case does not have the active pullup transistor. An external pull-up resistor needs
to be connected from the open collector
terminal of the pull-down transistor to the VCC
terminal. The pull-up resistor is typically 10 kΩ.
It may be mentioned here that the outputs of
totem-pole TTL devices cannot be tied
together. Although a common tied output may
end up producing an ANDing of individual
outputs, such a connection is impractical.
Demonstrate that the following circuit is two
inputs NAND?
Question #22: For the following circuit:
a. What is the logical function of this
circuit?
b. What is the basic advantage of
using open collector circuits?
c. Redesign circuit to have a totempole output?
The University of Jordan
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Digital Electronics
Sample Exam 2
Eng. Bashar Haddad
Question #23:
Implement all the following functions using nMos and CMOS technologies?
1. AND, NAND
2. OR, NOR
3. XOR
4. 2-Inputs MUX.
5. 4- Inputs MUX.
6. (A.B.C)+(A)
7. Half-Adder
Question #24:
What is the logical function of each of the following circuits?
Circuit 1
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Circuit 2
Circuit 3, 4
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Digital Electronics
Sample Exam 2
Eng. Bashar Haddad
Question #25:
Design the following logical functions using CMOS technology:
a) A 2:4 decoder defined by
Y0 = A0 · A1
Y1 = A0 · A1
Y2 = A0 · A1
Y3 = A0 · A1
b) A 3:2 priority encoder defined by
Y0 = A0 · (A1 + A2)
Y1 = A0 · A1
c) A 3-input majority function, returns a true output if at least two of the inputs are true.
Y = AB + BC + AC (majority)
d) Minority gate (The complement of the Majority).
Definitions:
•
•
•
•
•
Propagation delay time, tpd = maximum time from the input crossing 50% to the output crossing
50%.
Contamination delay time, tcd = minimum time from the input crossing 50% to the output
crossing 50%.
Rise time, tr = time for a waveform to rise from 20% to 80% of its steady-state value.
Fall time, tf= time for a waveform to fall from 80% to 20% of its steady-state value.
Edge rate, trf= (tr + tf)/2.
The University of Jordan
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Digital Electronics
Sample Exam 2
Eng. Bashar Haddad
Question #26:
Design the following logical functions such that the worst case of pull up and pull down resistors R.
a. Inverter
b. (A+B)
c. (A.B)
d. (A+B+C).D.E
e. 2-inputs MUX
Question #27:
Redo Question 26 for all gates in 25, 24, 23.
Question #28:
Sketch a 3-input NAND gate with transistor widths chosen to achieve effective rise and fall
resistance equal to that of a unit inverter (R). Annotate the gate with its gate and diffusion
capacitances.
Question 29:
Redo Question 28 for all gates in 26, 25, 24, 23 (unity pull up and unity pull down resistors)
Question 30:
For all gates in 26, 25, 24, 23 find the best and the worst rising/falling time?
Good luck
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