DIGITAL CIRCUITS AND LOGIC
DESIGN LABORATORY MANUAL
Spring, 2014
Jack Ou
Engineering Science
Sonoma State University
A SONOMA STATE UNIVERSITY PUBLICATION
CONTENTS
1
Linux Tutorial
1
1.1
1.2
1
1
1
2
2
3
3
4
4
5
1.3
2
Login to Redhat
Basic Stuffs
1.2.1
Finding Your Way with pwd
1.2.2
Listing Directories and Files with ls
1.2.3
Changing Directories with cd
1.2.4
Creating Directories with mkdir
1.2.5
Removing Directories with rmdir
1.2.6
To copy a file
1.2.7
Removing a file
Starting Cadence
Your First Verilog Program
7
2.1
2.2
2.3
2.4
7
7
8
8
References
Objectives
Procedure
Submission Checklist
iii
iv
3
CONTENTS
Model a NAND Based NOR Gate with Verilog
3.1
3.2
3.3
3.4
4
5
6
7
8
References
Objectives
Procedure
Submission Checklist
9
9
9
10
10
NAND Based Logic Gates
11
4.1
4.2
4.3
4.4
4.5
4.6
11
11
11
12
13
13
Reference
Objectives
Parts
NAND-based Inverter
NAND-based NOR Gate
Submission Checklist
Half Adder
15
5.1
5.2
5.3
5.4
5.5
5.6
15
15
15
16
16
17
Reference
Objectives
Parts
Modeling a Half Adder with Verilog
Implement a Half Adder Using 74XX Logic Gates
Submission Checklist
Two-Bit Binary Multiplier
19
6.1
6.2
6.3
6.4
Reference
Objectives
Description
Submission Checklist
19
19
20
21
2-Line to 4-Line Decoder
23
7.1
7.2
7.3
7.4
7.5
7.6
7.7
23
23
24
24
25
26
26
Reference
Objectives
Parts
Analysis
Verilog Modeling
Implement the 2-line to 4-line decoder using 74LS155 chip
Submission Checklist
Verilog Modeling Styles
27
CONTENTS
8.1
8.2
8.3
8.4
9
10
12
27
27
28
28
28
28
29
Pseudo Random Number
31
9.1
9.2
9.3
9.4
9.5
9.6
31
31
31
32
32
33
Reference
Objectives
Parts
Circuit Implementation
Display the Wave on the Mixed Signal Scope
Submission Checklist
Flip-Flops
35
10.1
10.2
10.3
10.4
10.5
35
35
36
36
36
36
36
38
38
10.6
11
Reference
Objectives
Analysis
Design Verification
8.4.1
Gate-Level Modeling
8.4.2
Dataflow Modeling
8.4.3
Behavioral Modeling
v
Reference
Objectives
Parts
Before You Start
Flip-flops
10.5.1 D flip-flop
10.5.2 JK flip-flop
10.5.3 T flip-flop
Post lab
Clocked Sequential Circuit
39
11.1
11.2
11.3
39
39
40
Verilog Modeling
Hardware Implementation
Submission Checklist
Universal Shift Register
43
12.1
12.2
12.3
12.4
12.5
43
43
44
44
45
Reference
Objectives
Parts
Model the Universal Shift Register in Verilog Model
Hardware Implementation
vi
CONTENTS
12.6
13
Submission Checklist
45
Synchronous Counter
47
13.1
13.2
13.3
47
48
48
Datasheet
Hardware Implementation
Submission Checklist
CHAPTER 1
LINUX TUTORIAL
1.1
Login to Redhat
Start the machine in the Redhat environment with the following user name and password:
User: r2d2
Password: student
1.2
1.2.1
Basic Stuffs
Finding Your Way with pwd
pwd displays the path and name of the directory you are currently in, giving you the
full picture of where you are. (Right Click ⇒ Open Terminal)
[r2d2@localhost ˜]$ pwd
/home/r2d2
Digital Circuits and Logic Design Laboratory Manual, First Edition.
c 2014 ,J. Ou.
Copyright 1
2
1.2.2
LINUX TUTORIAL
Listing Directories and Files with ls
Your Linux system is made up of directories and files that store a variety of information. Using the ls, you can find out exactly what is in your Linux system and
thereby find out what is available to you. You can list the files and directories of a
directory you are currently in.
[r2d2@localhost ˜]$ pwd
/home/r2d2
[r2d2@localhost ˜]$ ls
ade_viva.log CDS.log.CDSHOME
cadence
class
cdb2oa.log
design
CDS.log
Desktop
CDS.log.1
download
[r2d2@localhost ˜]$
1.2.3
instruct
libManager.log
linux.tutorial.text
mentor
mgc
models
panic.log
share
simulation
start
store
Changing Directories with cd
To explore Linux and its capabilities, you’ll need to move around among the directories. You do so using the cd command, which takes you from the directory you
are currently in to one that you specify. To move to a specific directory, type cd plus
the name of the directory. In the example below, we move down in the directory to a
subdirectory called design.
[r2d2@localhost ˜]$ pwd
/home/r2d2
[r2d2@localhost ˜]$ ls
ade_viva.log CDS.log.CDSHOME
cadence
class
cdb2oa.log
design
CDS.log
Desktop
CDS.log.1
download
[r2d2@localhost ˜]$ pwd
/home/r2d2
[r2d2@localhost ˜]$ ls
ade_viva.log CDS.log.CDSHOME
cadence
class
cdb2oa.log
design
CDS.log
Desktop
CDS.log.1
download
[r2d2@localhost ˜]$ cd design
[r2d2@localhost design]$ pwd
/home/r2d2/class
[r2d2@localhost design]$
instruct
libManager.log
linux.tutorial.text
mentor
mgc
models
panic.log
share
simulation
start
store
instruct
libManager.log
linux.tutorial.text
mentor
mgc
models
panic.log
share
simulation
start
store
BASIC STUFFS
3
Type cd .. to move up one level.
[r2d2@localhost class]$ pwd
/home/r2d2/design
[r2d2@localhost design]$ cd ..
[r2d2@localhost ˜]$ pwd
/home/r2d2
[r2d2@localhost ˜]$ ls
ade_viva.log CDS.log.CDSHOME
cadence
class
cdb2oa.log
design
CDS.log
Desktop
CDS.log.1
download
[r2d2@localhost ˜]$
1.2.4
instruct
libManager.log
linux.tutorial.text
mentor
mgc
models
panic.log
share
simulation
start
store
Creating Directories with mkdir
You might think of directories as being drawers in a file cabinet; each drawer contains
a bunch of files that are somehow related. For example, you might have a couple
of file drawers for your unread magazines, one for your to-do lists, and maybe a
drawer for your work projects. Similarly, directories in your Linux system act as
containers for other directories and files. You create new directories using the mkdir
command.
[r2d2@localhost ˜]$ pwd
/home/r2d2
[r2d2@localhost ˜]$ mkdir drawer
[r2d2@localhost ˜]$ ls
ade_viva.log CDS.log.CDSHOME drawer
cadence
class
instruct
cdb2oa.log
design
libManager.log
CDS.log
Desktop
linux.tutorial.text
CDS.log.1
download
mentor
[r2d2@localhost ˜]$ cd drawer
[r2d2@localhost drawer]$ pwd
/home/r2d2/drawer
[r2d2@localhost drawer]$
1.2.5
Removing Directories with rmdir
You can remove a directory using rm -r followed by the directory name.
[r2d2@localhost ˜]$ pwd
mgc
models
panic.log
share
simulation
start
store
4
LINUX TUTORIAL
/home/r2d2
[r2d2@localhost ˜]$ mkdir drawer
[r2d2@localhost ˜]$ cd drawer/
[r2d2@localhost drawer]$ pwd
/home/r2d2/drawer
[r2d2@localhost drawer]$ cd ..
[r2d2@localhost ˜]$ rm -r drawer
[r2d2@localhost ˜]$ ls
ade_viva.log CDS.log.CDSHOME instruct
cadence
class
libManager.log
cdb2oa.log
design
linux.tutorial.text
CDS.log
Desktop
mentor
CDS.log.1
download
mgc
[r2d2@localhost ˜]$
1.2.6
models
panic.log
share
simulation
start
store
instruct
libManager.log
linux.tutorial.text
mentor
mgc
CDS.log.bak
models
panic.log
share
simulation
start
store
download
instruct
libManager.log
linux.tutorial.text
mentor
mgc
models
panic.log
share
simulation
start
store
mgc
start
To copy a file
You can copy a file by using the following syntax.
cp existingfile new file
[r2d2@localhost ˜]$ pwd
/home/r2d2
[r2d2@localhost ˜]$ ls
ade_viva.log CDS.log.CDSHOME
cadence
class
cdb2oa.log
design
CDS.log
Desktop
CDS.log.1
download
[r2d2@localhost ˜]$ cp CDS.log
[r2d2@localhost ˜]$ ls
ade_viva.log CDS.log.bak
cadence
CDS.log.CDSHOME
cdb2oa.log
class
CDS.log
design
CDS.log.1
Desktop
[r2d2@localhost ˜]$
1.2.7
Removing a file
Use rm followed by the name of the file to be deleted.
[r2d2@localhost ˜]$ ls
ade_viva.log CDS.log.bak
download
STARTING CADENCE
cadence
CDS.log.CDSHOME instruct
cdb2oa.log
class
libManager.log
CDS.log
design
linux.tutorial.text
CDS.log.1
Desktop
mentor
[r2d2@localhost ˜]$ rm CDS.log.bak
[r2d2@localhost ˜]$ ls
ade_viva.log CDS.log.CDSHOME instruct
cadence
class
libManager.log
cdb2oa.log
design
linux.tutorial.text
CDS.log
Desktop
mentor
CDS.log.1
download
mgc
[r2d2@localhost ˜]$
1.3
5
models
panic.log
share
simulation
store
models
panic.log
share
simulation
start
store
Starting Cadence
1. Start a NEW terminal.(Right click → Open Terminal)
2. Go to the design directory.
3. Type rm -rf cmrf7sf.V1.9.0.2.ML to remove the existing start-up
directory.
4. Open the course webpage with a FireFox browser.
5. Download cmrf7sf.tar from the course website.
6. Type tar -xvf cmrf7sf.tar to extract the tar file.
7. Go to the cmrf7sf.V1.9.0.2.ML directory.
8. Type virtuoso & at the command prompt to start Cadence.
[r2d2@localhost ˜]$ pwd
/home/r2d2
[r2d2@localhost ˜]$ cd design
[r2d2@localhost design]$ pwd
/home/r2d2/design
[r2d2@localhost design]$ ls
AMSDesigner cmrf7sfML
envexp
AMSDInADE
cmrf7sf.V1.9.0.2.ML libConvert.txt
AnaSimTech
cmrf8sfDM
mentor
[r2d2@localhost design]$ cd cmrf7sf.V1.9.0.2.ML
[r2d2@localhost cmrf7sf.V1.9.0.2.ML]$ pwd
/home/r2d2/design/cmrf7sf.V1.9.0.2.ML
[r2d2@localhost cmrf7sf.V1.9.0.2.ML]$ virtuoso &
[1] 16648
spb16.5
tmpCphMsg
CHAPTER 2
YOUR FIRST VERILOG PROGRAM
2.1
References
1. Section 3.10, M. M. Mano and M. D. Ciletti, Digital Design, 4th edition, Upper
Saddle River, NJ.
2. ES210 lecture notes from January 15.
2.2
Objectives
After completing this lab, you will be able to:
1. Create a Cadence design library.
2. Use Verilog to model a simple combinational circuit.
3. Compile and run a verilog file.
4. Use SimVision to view waveforms.
Digital Circuits and Logic Design Laboratory Manual, First Edition.
c 2014 ,J. Ou.
Copyright 7
8
YOUR FIRST VERILOG PROGRAM
2.3
Procedure
1. Start virtuoso and create a library called es210.
2. Open a terminal, and create a folder called verilogSandBox. This is where
you will store Verilog files and execute Verilog simulations.
3. Use either emacs or vi to create fig3p37.v. The complete program is given
on slide 18 of the lecture notes.
4. Execute fig3p37.v according to the instructions in the lecture notes.
5. Are you able to get the same results?
6. What is D when A = B = C = 0?
7. What is E when A = B = C = 1?
8. Replace G3 in fig3p37.v with an XOR gate and execute the simulation. Are
the results of the simulation different?
2.4
Submission Checklist
1. With G3 set to an OR gate, what is D when A = B = C = 0? (1 point)
2. With G3 set to an OR gate, what is D when A = B = C = 1? (1 point)
3. Replace G3 with an XOR gate, re-run the simulation, are the results of the
simulation different? Why or why not? (2 points)
4. Please submit fig3p37.v with G3 changed to an XOR gate? (2 points)
5. Please submit a screen capture of the SimVision simulation. (2 points)
CHAPTER 3
MODEL A NAND BASED NOR GATE
WITH VERILOG
3.1
References
1. Section 3.10 and section 4.12, M. M. Mano and M. D. Ciletti, Digital Design,
4th edition, Upper Saddle River, NJ.
2. ES210 lecture notes from January 23,2014.
3.2
Objectives
After completing this lab, you will be able to:
1. Read a random test vector from a file.
2. Test a digital circuit with a random test vector.
3. Model the behavior of a NAND based NOR gate with Verilog.
Digital Circuits and Logic Design Laboratory Manual, First Edition.
c 2014 ,J. Ou.
Copyright 9
10
3.3
MODEL A NAND BASED NOR GATE WITH VERILOG
Procedure
1. Go to the course webpage and download the following files to the verilogSandBox
directory.
(a) flip_me.v and flip_me_tb.v: You will not use these files directly in
this lab. You can, however, use them (along with the lecture notes) to learn
how to generate random test vectors.
(b) bit_str_a_0.txt and bit_str_a_1.txt: random test vectors. You
can use these files test the behavior of the NAND based NOR gate.
(c) nor_with_nand.v and nor_with_nand_tb.v: Use these files as
starting templates.
A
G1
C
G3
B
Figure 3.1
G2
E
G4
F
D
A NOR gate constructed using only NAND gates.
2. Figure 3.1 shows the construction of a NOR gate using only NAND gates. G1,
G2, G3 and G4 are instance names of the NAND gates. A and B are the inputs
and F is the output. C, D and E are wire names assigned to the nodes indicated
in Figure 3.1.
3. Edit nor_with_nand.v so that we can model the behavior of the NAND
based NOR. Please do not use any NOR gate in your verilog code. Please use
the instance names and wire names indicated in Figure 3.1.
4. Next, construct the test bench for the NOR gate. You may use nor_with_nand_tb.v
as a starting point. You may also wish to take a look at flip_me_tb.v.
5. Apply the random test vectors and show that the circuit does indeed behave as
a NOR gate.
3.4
Submission Checklist
1. A print-out of nor_with_nand.v. (2 points)
2. A print-out of nor_with_nand_tb.v. (2 points)
3. A screen capture of waveforms of A, B, and F. (3 points)
CHAPTER 4
NAND BASED LOGIC GATES
4.1
Reference
1. Yannis Tsividis, “A First Lab in Circuits and Electronics,” John Wiley and Sons.
2. 7400 Quad 2-input NAND Gates. (ES 210 webpage → datasheets)
4.2
Objectives
After completing this experiment, you will be able to
1. Build a NOT gate with a NAND gate.
2. Learn to characterize a NOT gate.
3. Build a NAND based NOR gate.
4.3
Parts
A digital multimeter
Digital Circuits and Logic Design Laboratory Manual, First Edition.
c 2014 ,J. Ou.
Copyright 11
12
NAND BASED LOGIC GATES
+5 V power supply, a second power supply (e.g. ± 25 V supply)
A breadboard
Wires
1 HD74LS00 (TTL NAND gates)
4.4
NAND-based Inverter
1. Figure 4.1 shows the implementation of a NOT gate using a 2-input NAND
gate.
2. Build the NOT gate with one of the four NAND gates in the HD74LS00 chip.
The numbers in Figure 4.1 represent the pin numbers of one of NAND gates in
the HD74LS00 chip. For example, pin 14 is the power supply pin that should
be connected to a 5 V power supply. Pin 7 should be connected to ground.
3. Sweep the input from 0 to 5 V and record your results in Table 4.1. Does this
circuit behave as a NOT gate?
Figure 4.1
A NAND gate implementation of a NOT gate
VA
Vout
0.0 V
1.0 V
2.0 V
3.0 V
4.0 V
5.0 V
Table 4.1
Vout vs. VA
NAND-BASED NOR GATE
4.5
13
NAND-based NOR Gate
1. The symbol and truth table for a NOR (i.e. NOT OR) gate are shown in Figure
4.2. Figure 4.3 shows the implementation of a NOR gate using only NAND
gates.
2. Use the Boolean algebra to prove that the circuit in Figure 4.3 is indeed a NOR
gate.
3. Build the NOR gate as shown in Figure 4.3. Verify the functionality of your
circuit by checking the voltages at the pins indicated in Table 4.2.
Figure 4.2
Figure 4.3
Table 4.2
4.6
The truth table for a NOR gate
The NAND implementation of a NOR gate
1
4
0.0 V
0.0V
0.0 V
5.0V
5.0 V
5.0V
5.0 V
0.0V
3
6
11
8
Voltages of a NOR gate. Pin numbers are shown in the top row.
Submission Checklist
1. Submit Table 4.1. (2 points)
14
NAND BASED LOGIC GATES
2. Use the Boolean algebra to prove that the circuit in Figure 4.2 is indeed a NOR
gate. (3 points)
3. Submit Table 4.2. (2 points)
CHAPTER 5
HALF ADDER
5.1
Reference
1. 7408 Quad 2-input AND Gate data sheet. (ES 210 webpage → datasheets)
2. 7486 Quad 2-input XOR Gate data sheet. (ES 210 webpage → datasheets)
5.2
Objectives
After completing this experiment, you will be able to
1. Model a half adder using Verilog.
2. Build a Verilog test bench for a half adder circuit.
3. Implement a half adder circuit on a breadboard with 74XX logic gates.
5.3
Parts
A digital multimeter
Digital Circuits and Logic Design Laboratory Manual, First Edition.
c 2014 ,J. Ou.
Copyright 15
16
HALF ADDER
+5 V power supply
A breadboard
Wires
1 74LS86 (XOR gate)
1 74LS08 (AND gate)
5.4
Modeling a Half Adder with Verilog
A
B
S
C
Figure 5.1
A half adder circuit.
1. Figure 5.1 shows the gate level implementation of a half adder circuit. Please
develop the Verilog model for this half adder. You can start by downloading the
half_adder.v template from the course website.
2. Next, write the Verilog test bench for half_adder.v. Name the test bench
half_adder_tb.v. You can start with either flip_me_tb.v template or
nand_based_nor_tb.v from last week. Your test bench should have the
following capabilities:
(a) It should be able to read random binary numbers as inputs.
(b) It should write the inputs (A and B) and the outputs (S and C) to an output
file called half_adder_tb.out.
5.5
Implement a Half Adder Using 74XX Logic Gates
1. Implement the half adder circuit shown in Figure 5.1. You may use 74LS86 as
the XOR gate and the 74LS08 as the AND gate.
(a)
(b)
(c)
(d)
(e)
(f)
According to the 74LS86 data sheet, what is the nominal supply voltage?
What should be the DC voltage at pin #14 of the 74LS86 chip?
What should be the DC voltage at pin #7 of the 74LS86 chip?
According to the 74LS08 data sheet, what is the nominal supply voltage?
What should be the DC voltage at pin #14 of the 74LS08 chip?
What should be the DC voltage at pin #7 of the 74LS08 chip?
2. Complete the truth table in Table 5.1. Does this circuit behave a s half adder?
SUBMISSION CHECKLIST
VA
VB
0.0 V
0.0V
0.0 V
5.0V
5.0 V
5.0V
5.0 V
0.0V
Table 5.1
5.6
VC
17
VS
Truth table of a half adder circuit.
Submission Checklist
You may work on this lab with a partner. The lab is due in the beginning of the next
lab. (i.e. 02.13.14)
1. A copy of half_adder.v. (1 point)
2. A copy of half_adder_tb.v. (2 points)
3. A copy of half_adder_tb.out. (3 points)
4. The answer to the following questions: (1 point)
(a) According to the 74LS86 data sheet, what is the nominal supply voltage?
(b) What should be the DC voltage at pin #14 of the 74LS86 chip?
(c) What should be the DC voltage at pin #7 of the 74LS86 chip?
(d) According to the 74LS08 data sheet, what is the nominal supply voltage?
(e) What should be the DC voltage at pin #14 of the 74LS08 chip?
(f) What should be the DC voltage at pin #7 of the 74LS08 chip?
5. Submit Table 5.1. (4 points)
6. Please provide some feedback about this lab. e.g. Were you able to finish the
lab on time? Is the instruction clear? Are there any typos or errors about this
experiment? Any comment to help improve this lab is helpful? (4 points)
CHAPTER 6
TWO-BIT BINARY MULTIPLIER
6.1
Reference
1. Section 4.5 and section 4.7, M. M. Mano and M. D. Ciletti, Digital Design, 4th
edition, Upper Saddle River, NJ.
2. ES210 lecture notes from February 12,2014.
6.2
Objectives
After completing this experiment, you will be able to
1. Model a two-bit multiplier using Verilog.
2. Build a Verilog test bench for a two-bit multiplier circuit.
Digital Circuits and Logic Design Laboratory Manual, First Edition.
c 2014 ,J. Ou.
Copyright 19
20
TWO-BIT BINARY MULTIPLIER
A0
B1
B0
A1
B1
G3
G2
W3
W1
G0
W0
C0
HA1
HA2
C3 C2
W2 C1
Figure 6.1
6.3
G1
B0
Two-bits Multiplier.
Description
1. Figure 6.1 shows the gate level implementation of a two-bit multiplier circuit.
A0 , A1 , B0 and B1 are inputs of the multiplier. C0 , C1 , C2 and C3 are the
outputs. Please develop the Verilog model for this multiplier. You can start by
downloading the half_adder.v template from the course website. Please
observe the following naming convention as you develop the model.
(a) Use G0, G1, G2, and G3 to identify instances of the AND gate in Figure
6.1.
(b) Use HA0 and HA1 to identify instances of the half-adder cell in Figure 6.1.
(c) Use W0, W1, W2 and W3 to identify the wires indicated in Figure 6.1.
(d) The multiplier module should be named: mult_2_2_4.v
2. Please use the following questions to guide your thought process as you develop
the model for the two-bit multiplier, i.e. mult_2_2_4.v.
(a) Module Declaration
i.
ii.
iii.
iv.
What are the inputs?
What are the outputs?
How should the input ports be connected to the AND gates?
How should the outputs be connected to the AND gates and the
half-adder cells?
(b) Program Body
i. How should the AND gate be implemented?
SUBMISSION CHECKLIST
21
ii. How should instances of the half adder cells be called?
3. Next, write the Verilog test bench for mult_2_2_4.v. Name the test bench
mult_2_2_4_tb.v. You can start with with any test bench you have used
previously. Your test bench should have the following features:
(a) It should be able to read random binary numbers as inputs.
(b) It should write the input values and the output values to an output file
called mult_2_2_4.out. Please use the following questions to guide
your thought process.
i. What should be declared as the outputs of the test bench?
ii. How many bit files do you need?
iii. How should mult_2_2_4.v module be invoked?
6.4
Submission Checklist
You may work on this lab with a partner. The lab is due in the beginning of the next
lab.
1. A copy of mult_2_2_4.v. (1 point)
2. A copy of mult_2_2_4_tb.v. (2 points)
3. A copy of mult_2_2_4.out. (3 points)
4. Please provide some feedback about this lab. e.g. Were you able to finish
the lab on time? Are you becoming more comfortable with writing code in
Verilog? Are there any typos or errors about this experiment? Any comment to
help improve this lab is helpful? (4 points)
CHAPTER 7
2-LINE TO 4-LINE DECODER
7.1
Reference
1. Dual 74LS155 Decoders/Demultiplexers data sheet. (ES 210 web page →
datasheets)
7.2
Objectives
After completing this experiment, you will be able to
1. Use Karnaugh map to deduce the gate level implementation of a 2-line to 4-line
decoder.
2. Model the 2-line to 4-line decoder using Verilog.
3. Implement a 2-line to 4-line decoder with a 74LS155 chip.
Digital Circuits and Logic Design Laboratory Manual, First Edition.
c 2014 ,J. Ou.
Copyright 23
24
7.3
2-LINE TO 4-LINE DECODER
Parts
A digital multimeter
+5 V power supply
A breadboard
Wires
1 74LS155 (2-line to 4-line decoder)
4 200 Ω resistors
4 red LEDs
7.4
Analysis
1. The truth table for a 74LS155 2-line to 4-line decoder is shown in Figure 7.1.
You may assume that G1=L and C1=H for this experiment. The inputs of the
decoder are Select A and Select B and the outputs are 1Y0, 1Y1, 1Y2
and 1Y3.
Figure 7.1
The truth table for a 2-line to 4-line decoder.
2. Please repeat the following steps for each of the outputs.
(a) Draw the Karnaugh map for Select A, Select B and one of the outputs
(e.g. 1Y0 ).
(b) Use the ones in the Karnaugh map to determine the Boolean expression for
the output.
(c) Simplify the Boolean expression so that it can be implemented with an
NAND gate and inverter(s). (Hint: Use DeMorgan’s theorem.)
3. Draw the gate level implementation of the decoder.
VERILOG MODELING
7.5
25
Verilog Modeling
1. You will model the 2-line to 4-line decoder in Verilog. Please follow the following naming convention for the Verilog module:
(a) The module should be called decode24.v.
(b) The inputs of the module are A and B.
(c) The output of the module is Y, which is an array of four elements.
(d) Please use the assign statements to implement the Boolean expressions.
(e) Prepare a test bench for the decode24.v. The test bench should be called
decode24_tb.v. The test bench should produce an output file called
decode24.out.
(f) You can download encode83.v and encode83_tb.v from the course
website for your reference.
1
2
3
4
5
RLED
VCC +
−
6
RLED
VB +
−
7
RLED
8
RLED
C1
VCC
G1
C2
B
G2
1Y3
A
1Y2
2Y3
1Y1
2Y2
1Y0
2Y1
GND
2Y0
74LS156
Figure 7.2
Schematic of a 2-line-to 4-line decoder.
16
15
14
13
12
11
10
9
VA +
−
26
7.6
2-LINE TO 4-LINE DECODER
Implement the 2-line to 4-line decoder using 74LS155 chip
1. Implement the decoder circuit shown in Figure 7.2 with a 74LS155 chip and
record the results in Table 7.1.
VA
VB
0.0 V
0.0V
0.0 V
5.0V
5.0 V
5.0V
5.0 V
0.0V
Table 7.1
7.7
VY 0
VY 1
VY 2
VY 3
Truth table of the decoder.
Submission Checklist
You may work on this lab with a partner. The lab is due in the beginning of the next
lab.
1. The Karnaugh map associated with each output (4 point)
2. Gate level schematic of the decoder. (6 points)
3. A copy of decode24.v. (2 points)
4. A copy of decode24_tb.v. (2 points)
5. A copy of decode24.out. (2 points)
6. Submit Table 7.1. (4 points)
7. Please provide some feedback about this lab. e.g. Were you able to finish the
lab on time? Is the instruction clear? Are there any typos or errors about this
experiment? Any comment to help improve this lab is helpful? (4 points)
CHAPTER 8
VERILOG MODELING STYLES
8.1
Reference
1. Section 4.11-4.12, M. M. Mano and M. D. Ciletti, Digital Design, 4th edition,
Upper Saddle River, NJ.
2. Lecture notes from 02.24.14.
8.2
Objectives
After completing this experiment, you will be able to
1. Perform gate-level modeling, dataflow modeling and behavioral modeling.
2. Implement a Boolean function with a MUX.
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VERILOG MODELING STYLES
8.3
Analysis
1. We will implement the following Boolean function with an 8-to-1 MUX in this
lab.
X
F (A, B, C, D) =
(0, 2, 5, 7, 11, 14)
(8.1)
2. Start by constructing the truth table for F . You may use A, B, C as the selector
bits for the MUX, D as the input, and F as the output. (1 point)
3. Construct a schematic for implementing F with an 8-to-1 MUX. You may use
D along with D and ”0” as inputs to the 8-to-1 MUX. (1 point)
8.4
Design Verification
We will verify the functionality of the circuit through simulation. We will simulate
the circuit three times, each time with a different model of 8-to-1 MUX. To help you
focus on learning the differences of the three modeling styles, we will provide test
bench files and templates for this exercise. You will, however, have to write some
code.
8.4.1
Gate-Level Modeling
1. Please download chap4p32a_tb.v from the course website. This test bench
uses mux81a, which is an 8-to-1 MUX implemented with gate-level modeling.
S is an array of bits that correspond to A, B, C, and D. The output of the
simulation is stored in chap4p32a_tb.out. Please answer the following
questions about the test bench: (1 point)
(a) How are the assign statements related to the schematic of F ?
(b) Why do we only pass S[0:2] to mux81a?
2. You will develop a gate-level Verilog model for mux81a. The name for the 8to-1 MUX is mux81a.v. You may use the 2-to-1 MUX model from the course
website. Please submit a print-out of mux81a.v (3 points)
3. Execute the test bench and submit a print-out of chap4p32a_tb.out. (1
point)
8.4.2
Dataflow Modeling
1. Please download chap4p32b_tb.v from the course website. This test bench
uses mux81b, which is an 8-to-1 MUX implemented with dataflow modeling.
2. Please download mux81b.v from the course website. mux81b.v is a template that you can use. The program body has been removed. Please use the
DESIGN VERIFICATION
29
assign keyword along with the conditional operator (?:) to implement the
MUX. You will only have to write one line of code. Submit a print-out of
mux81b.v. (2 points)
3. Please save the output in chap4p32b_tb.out and submit it. (1 point)
8.4.3
Behavioral Modeling
1. Please download chap4p32c_tb.v from the course website. This test bench
uses mux81c, which is an 8-to-1 MUX implemented using behavioral modeling.
2. Please download mux81c.v from the course website. mux81c.v is a template that you can use. The program body has been removed. Please use the
always keyword along with the if-else staetment to implement the MUX.
(2 points)
3. Please save the output in chap4p32c_tb.out and submit it. (1 point)
CHAPTER 9
PSEUDO RANDOM NUMBER
9.1
Reference
1. http://en.wikipedia.org/wiki/Linear_feedback_shift_register
9.2
Objectives
After completing this experiment, you will be able to
1. Generate a 4-bit pseudo number sequence.
2. Use a universal shift register.
3. Use Agilent DSO-X 2002A mixed signal scope/function generator.
9.3
Parts
1. 1 74LS194 4-bit bi-directional universal shift register
Digital Circuits and Logic Design Laboratory Manual, First Edition.
c 2014 ,J. Ou.
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32
PSEUDO RANDOM NUMBER
2. 1 74LS86 XOR gate
3. Agilent DSO-X 2002A
9.4
Circuit Implementation
We will implement the 4-bit pseudo random number circuit shown in Figure 9.1. The
pseudo random sequence is created by continuously feeding the output of the XOR
gate back to the input of the shift register (i.e. Shift Right Serial)). In order to shift
the bits (i.e. QA , QB , QC , and QD ) to the right by one bit, S0 is connected to VCC
and S1 is connected to ground. The output of the shift register is updated at the rising
edge of the clock. We will use the pseudo random number circuit later in the course.
If you do not wish to take apart the circuit at the end of the lab, you can check out
the 74LS194 chip and 74LS86 chip and return them at the end of the semester.
1
2
3
4
VCC +
−
5
6
7
8
CLR
SR SER
VCC 16
Q 15
A
QB 14
Q 13
A
B
C
D
SL SER
GND
C
QD 12
11
CLK
10
S1
9
S0
74LS86
74LS194
Figure 9.1
9.5
A 4-bit pseudo random generator.
Display the Wave on the Mixed Signal Scope
1. We will examine the waveforms at the outputs (QA , QB , QC and QD ) of the
shift register. We will start by generating a clock and feeding it to pin #11 of
the 74LS194 chip.
(a) Press default setup.
CLK
SUBMISSION CHECKLIST
33
(b) Press Wave Gen.
(c) Set Waveform to square.
(d) Set Frequency to 1 kHz.
(e) Set Amplitude to 5.00 Vpp.
(f) Set Offset to 2.5 V.
(g) Set Duty Cycle to 50 percent.
2. Connect the output of the function generator (i.e. Gen Out) to pin #11 of the
74LS194 chip.
3. Connect the digital probes to QA , QB , QC and QD of the 74LS194 chip.
4. Press Auto Scale.
5. Press Trigger
(a) Set trigger type to Edge.
(b) Set the source to WaveGen.
(c) Set the edge to rising.
6. Press Mode/Coupling.
(a) Set Mode to normal.
(b) Adjust the Hold-off until the waveforms are triggered properly.
9.6
Submission Checklist
Please submit brief responses to the following questions:
1. What is the relationship between QA , QB , QC and QD ? (1 point)
2. According to the 74LS194 data sheet, what is QA when CLEAR is set to “0”?
(1 points)
3. What are the appropriate values for S0 and S1 if we want to shift content of the
shift register to the left? (2 points)
4. The circuit function will not function correctly if QA = QB = QC = QD = 0.
What can you do to force the circuit to produce the correct result? (hint: read
the wikipedia entry on linear feedback shift register in addition to the data sheet
for 74LS194) (2 points)
CHAPTER 10
FLIP-FLOPS
10.1
Reference
1. The experiment on pseudo random number circuit.
2. Section 5.4, M. M. Mano and M. D. Ciletti, Digital Design, 4th edition, Upper
Saddle River, NJ.
3. ES210 lecture notes from March 12,2014.
10.2
Objectives
After completing this experiment, you will be able to
1. Use a D flip-flop.
2. Use a JK flip-flop.
3. Use a T flip-flop.
Digital Circuits and Logic Design Laboratory Manual, First Edition.
c 2014 ,J. Ou.
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36
FLIP-FLOPS
4. Model flip-flops in Verilog.
10.3
Parts
1. 1 74LS194 4-bit bit-directional universal shift register
2. 1 74LS86 XOR gate
3. Agilent DSO-X 2002A
4. 1 74LS76A Dual JK flip-flop with set and clear (Look under the datasheet
link)
5. 1 74HC175 Quad D flip-flop with reset, positive-edge trigger (Look under the
list of 7400 TTL logic family link)
10.4
Before You Start
Please make sure your 4-bit pseudo random number circuit is functional before coming to the lab. You can verify that you have a functional circuit by observing the
waveforms on the digital scope. Please review the experiment from last week as necessary. If you have borrowed 74LS194 and 74LS86, please fill out the appropriate
paperwork and return it to the instructor.
10.5
10.5.1
Flip-flops
D flip-flop
We will use 74HC175 as the D flip-flop in this experiment. There are four D flipflops on this chip. We will use only one of them in this experiment. The supply
voltage (i.e. VCC ) for this chip is 5 V. The chip comes with a master reset input. We
set M R to VCC to enable the chip. Please build the circuit shown in Figure 10.1.
Observe D0 , CLK and Q on the mixed signal scope. Do a screen capture and attach
the image as part of the submission for this lab. Please comment on the waveforms
you have observed in this experiment. Does the circuit behave as a D flip-flop? (3
points)
10.5.2
JK flip-flop
We will use Motorola’s dual JK flip-flop (74LS76A) for this experiment. This chip
comes with a set and a clear feature. In order to place the chip in its “normal”
operation, we need to set SD and CD to high. Please also note that pin 5 and 13
are designated as VCC and and ground respectively. Before you build the circuit as
FLIP-FLOPS
1
2
3
VCC +
−
4
5
6
7
8
CLR
SR SER
A
B
VCC 16
Q 15
Q
A
C
QD
D
CLK
GND
1
QB 14
Q 13
C
SL SER
37
S1
S0
12
11
MR
2 Q
0
3
Q0
4 D
0
74LS86
10
CLK
9
5 D
1
6
Q1
7 Q
1
8
74LS194
Figure 10.1
GND
VCC 16
Q 15
3
Q3
14
D3 13
D 12
2
Q2
11
Q2 10
9
CP
74HC175
D flip-flop.
shown in Figure 10.2, please study the mode select truth table in the data sheet. We
will use QA and the output of the XOR gate as the the inputs to J and K of the flipflop. Build the circuit as shown in figure 10.2. Do a screen capture as before. Save
the image and comment on the waveforms you observe. Are you able to explain what
happen to the output at each negative edge of the clock? (3 points)
1
2
3
VCC +
−
4
5
6
7
8
CLR
SR SER
A
B
C
D
SL SER
GND
VCC 16
Q 15
1
CP
2 S
D
3 C
A
QB
14
QC 13
Q 12
D
CLK
S1
S0
11
D
4
9
74LS194
Figure 10.2
5 V
CC
6
74LS86
10
J
CLK
16
Q 15
14
Q
13
GN D
12
11
7
10
8
9
74LS76A
JK flip-flop.
K
Q
38
FLIP-FLOPS
10.5.3
T flip-flop
A JK flip-flop can easily be configured to a T flip-flop by connecting the J terminal
to the K terminal as shown in Figure 10.3. Are you able to deduce the mode select
truth table for a T flip-flop from a JK flip-flop? Build the circuit as shown in Figure
10.3. Capture the screen and save it to a file. Analyze the waveforms and comment
on whether the T flip-flop is functional. What do you expect to see when T is equal
to 0? What do you expect to see when T is equal to 1? (3 points)
1
2
3
VCC
4
+
−
5
6
7
8
CLR
SR SER
A
B
C
D
SL SER
GND
VCC 16
Q 15
1
2 S
D
3 C
A
QB 14
Q 13
D
4
C
QD 12
11
CLK
10
S1
9
S0
10.6
J
5 V
CC
6
74LS86
CLK
74LS194
Figure 10.3
CP
Post lab
We will to use use flip-flops in Verilog simulation later in the semester. Therefore, it
is important that you know how to model the flip-flops in Verilog.
1. Build the behavioral model for a JK flip-flop (i.e. using case.....endcase. )
Please take a look at the lecture notes for more details. Submit a print-out of the
Verilog module. (1 point)
2. Test it with a test bench. Submit a print-out of the test bench. (1 point)
3. Prove that you have a working model for the JK flip-flop by showing the appropriate waveforms. Submit a screen capture of the waveforms. (1 point)
4. Next, build the Verilog model for T flip-flop using an existing model of a JK
flip-flop. Submit a print-out of the module. (1 point)
5. Test it with a test bench and show that the T flip-flop is functional by showing
the appropriate waveforms. (2 points)
16
Q 15
14
Q
13
GN D
12
11
7
10
8
9
74LS76A
T flip-flop.
K
Q
CHAPTER 11
CLOCKED SEQUENTIAL CIRCUIT
11.1
Verilog Modeling
1. Using fig5p16.v and fig5p16_tb.v as a starting point, modify the verilog files in order to model the operation of the sequential circuit in Figure 11.1.
11.2
Hardware Implementation
1. We have shown in class that the state diagram in Figure 11.1 can be converted
into the schematic in Figure 11.2.
2. Please build the circuit shown in Figure 11.2. To generate the input (x), you will
need to build the same random number generator you built last week. You will
need generate the clock signal from the mixed signal scope and use it to drive
both the random number generator and the flip-flops. Please use the datasheets
available from google doc.
Digital Circuits and Logic Design Laboratory Manual, First Edition.
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40
CLOCKED SEQUENTIAL CIRCUIT
Figure 11.1
The state diagram of a sequential circuit.
(a) Use 74LS175N as the D flip-flop. What should be the voltage supplied to
terminal 1?
(b) Use 74LS32N as the OR gate.
(c) Use 74LS08 as the AND gate.
11.3
Submission Checklist
1. Submit a print-out of state, next state, x, y, and clock used in verilog simulation. (10 points)
2. Display A, B, clock, x and y on the mixed signal scope, save the waveform as
a graphic file, and submit a print out of the waveform. (10 points)
SUBMISSION CHECKLIST
Figure 11.2
The state diagram of the sequential dircuit in Figure 11.1
41
CHAPTER 12
UNIVERSAL SHIFT REGISTER
12.1
Reference
1. The experiment on pseudo random number circuit.
2. Section 6.1-6.2, M. M. Mano and M. D. Ciletti, Digital Design, 4th edition,
Upper Saddle River, NJ.
3. ES210 lectures from 4.2.2014.
12.2
Objectives
After completing this experiment, you will be able to
1. Generate a behavioral model in Verilog for the universal shift register.
2. Build a universal shift register from D flip-flop and 4-to-1 MUX.
3. Troubleshoot and debug a non-trivial sequential circuit.
Digital Circuits and Logic Design Laboratory Manual, First Edition.
c 2014 ,J. Ou.
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44
UNIVERSAL SHIFT REGISTER
12.3
Parts
1. MC74HC175N (D flip-flop)
2. 74LS153 (4-to-1 MUX)
12.4
Model the Universal Shift Register in Verilog Model
1. We are going to model the universal shift register shown in Figure 12.1. The
universal shift register has four distinct modes of operations shown in Figure
12.2.
Figure 12.1
Construction of a Universal Shift Register.
Figure 12.2
Mode Control of the shift register.
2. Use the lecture notes as a guide and build the Verilog models associated with the
universal shift register. The shift register can be modeled both behaviorally and
structurally. In this experiment, you will model the shift register behaviorally.
HARDWARE IMPLEMENTATION
45
3. Please go to the course website and download the bit files required for this experiments. You will also be able to download the templates for the shift register
and the test bench. Please modify the templates before you execute the program.
12.5
Hardware Implementation
1. Please build a shift-right register using only D flip-flops and 4-to-1 MUXs
shown in Figure 12.1. In particular,
(a) Use MC74HC175N as the D flip-flop.
(b) Use 74LS153 as the 4-to-1 MUX.
(c) Please read the spec sheet carefully and determine the voltage that must be
supplied to terminal 15 of the MUX chip. Also read the data sheet carefully
so as to set the MUX to read binary numbers from C1 .
12.6
Submission Checklist
1. A hard-copy of shift_register_4_beh.v, as well as the waveform generated with the test bench. (10 points)
2. Demonstrate the shift-right property of the shift register on the mixed signal
oscilloscope. Save and printout the waveform displayed on the mixed signal
scope. (10 points)
CHAPTER 13
SYNCHRONOUS COUNTER
13.1
Datasheet
1. You will learn to operate DM74LS193 as an “up” counter in this experiment.
Please download the datasheet from the google drive for this experiment.
2. According to the datasheet, “the direction of counting is determined by which
count input is pulsed while the other count input is held HIGH.”
(a) We will build a synchronous counter that counts up from 0000.
(b) Using the connection diagram on page 1 of the datasheet as a reference,
what should be connected to pin #4? What should be connected to pin #5?
Please assume that a clock of 1 KHz with a low of 0V and a high of 5 V is
available for pulsing an input.
3. According to the “Recommended Operating Conditions” section of the datasheet,
what value should be used for VCC ?
4. What bias voltage should provided for pin #8?
Digital Circuits and Logic Design Laboratory Manual, First Edition.
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48
SYNCHRONOUS COUNTER
5. According to the datasheet, this “counter was designed to be cascaded without
the need for external circuitry”. What outputs are used for this purpose? Are
they needed in this experiment?
6. What is the purpose of the “clear” input? Should it be set to a high level or a
low level? According to the timing diagram on page 3 of the datasheet, how are
QA , QB , QC and QD affected by the “clear” input?
Figure 13.1
Partial Logic Diagram
7. You will use the paritial Logic Diagram in Figure 13.1 to answer the following
question.
(a)
(b)
(c)
(d)
13.2
What is w1 if CLEAR=1? What is w1 if CLEAR=0 and LOAD=1?
What is the output of gate X in Figure 13.1 if LOAD=1?
What is w2 if CLEAR =0?
Replace the circuitry in the red retangle in Figure 13.1 by applying the DeMorgan’s theorem. What is the signal provided to the reset terminal of the
T flip-flop when LOAD=1 and CLEAR=0?
Hardware Implementation
1. Build a frequency divider with DM74LS193. Observe the outputs at QA , QB ,
QC , and QD . Does the circuit behave as a frequency divider?
13.3
Submission Checklist
1. A screen shot of the divider outputs. (10 points)
2. Please answers all the questions in this lab. (20 points)