1. No category

Telecommunications
Communications Technologies
Courseware Sample
39865-F0
A
TELECOMMUNICATIONS
COMMUNICATIONS TECHNOLOGIES
COURSEWARE SAMPLE
by
the Staff
of
Lab-Volt Ltd.
Copyright © 2009 Lab-Volt Ltd.
All rights reserved. No part of this publication may be reproduced,
in any form or by any means, without the prior written permission
of Lab-Volt Ltd.
Printed in Canada
April 2009
Table of Contents
Introduction
Courseware Outline
Quadrature Phase Shift Keying (QPSK/DQPSK)
Sample Exercise
(QPSK/DQPSK)
Extracted
from
Quadrature
Phase
Shift
Keying
Exercise 1 QPSK Modulation
Sample Exercise
(QAM/DQAM)
Extracted
from
Quadrature
Amplitude
Modulation
Exercise 1 QAM Modulation
Sample Exercise Extracted from Asymmetric Digital Subscriber Line (ADSL)
Exercise 1 ADSL Signal Spectral Analysis
Instructor Guide Sample Exercise Extracted from Asymmetric Digital
Subscriber Line (ADSL)
Exercise 1 ADSL Signal Spectral Analysis
Bibliography
III
IV
Introduction
Digital communication offers so many advantages over analog communication that
the majority of today's communications systems are digital.
Unlike analog communication systems, digital systems do not require accurate
recovery of the transmitted waveform at the receiver end. Instead, the receiver
periodically detects which waveform is being transmitted, among a limited number
of possible waveforms, and maps the detected waveform back to the data it
represents. This allows extremely low error rates, even when the signal has been
corrupted by noise.
The digital circuits are often implemented using application specific integrated
circuits (ASIC) and field-programmable gate arrays (FPGA). Although this
"system-on-a-chip" approach is very effective for commercial and military
applications, the resulting systems do not allow access to internal signals and data
and are therefore poorly suited for educational use. It is for this reason that Lab-Volt
designed the Communications Technologies Training System.
The Lab-Volt Communications Technologies Training System, Model 8087, is a
state-of-the-art communications training system. Specially designed for hands-on
training, it facilitates the study of many different types of digital
modulation/demodulation technologies such as PAM, PWM, PPM, PCM, Delta
Modulation, ASK, FSK, and BPSK as well as spectrally efficient technologies such
as QPSK, QAM, and ADSL. The system also enables the study of direct-sequence
and frequency-hopping spread spectrum (DSSS and FHSS), two key technologies
used in modern wireless communication systems (CDMA cellular-telephony
networks, Global Positioning System, Bluetooth interface for wireless connectivity,
etc.) to implement code-division multiple access (CDMA), improve interference
rejection, minimize interference with other systems, etc. The system is designed to
reflect the standards commonly used in modern communications systems.
Unlike conventional, hardware-based training systems that use a variety of physical
modules to implement different technologies and instruments, the Communications
Technologies Training System is based on a Reconfigurable Training Module (RTM)
and the Lab-Volt Communications Technologies (LVCT) software, providing
tremendous flexibility at a reduced cost.
Each of the communications technologies to be studied is provided as an application
that can be selected from a menu. Once loaded into the LVCT software, the selected
application configures the RTM to implement the communications technology, and
provides a specially designed user interface for the student.
The LVCT software provides settings for full user control over the operating
parameters of each communications technology application. Functional block
diagrams for the circuits involved are shown on screen. The digital or analog signals
at various points in the circuits can be viewed and analyzed using the virtual
instruments included in the software. In addition, some of these signals are made
available at physical connectors on the RTM and can be displayed and measured
using conventional instruments.
The courseware for the Communications Technologies Training System consists of
a series of student manuals covering the different technologies as well as instructor
guides that provide the answers to procedure step questions and to review
questions. The Communications Technologies Training System and the
accompanying courseware provide a complete study program for these key
information-age technologies.
V
VI
Courseware Outline
QUADRATURE PHASE SHIFT KEYING (QPSK/DQPSK)
Introduction
Phase Shift Keying (PSK) Modulation
Digital modulation. M-ary signaling. Phase shift keying. Quadrature
Phase Shift Keying. Bandwidth efficiency. Constellation diagrams.
Exercise 1
QPSK Modulation
The QPSK waveform. QPSK constellations. A typical QPSK
modulator. Symbol rate and bandwidth.
Exercise 2
QPSK Demodulation
Demodulation and detection. QPSK demodulation. Carrier recovery.
Detection of the demodulated signals. Phase ambiguity.
Exercise 3
Differential QPSK (DQPSK)
Review of phase ambiguity. Using differential encoding to overcome
phase ambiguity. Differential encoding applied to PSK. Advantages
and disadvantages of differential encoding. Differential encoding in
the QPSK/DQPSK application.
Exercise 4
Data Scrambling and Descrambling
The purpose of data scrambling and descrambling. Scrambling and
descrambling circuits. The choice of polynomial. Descrambler
impulse response. Scrambling and descrambling in the
QPSK/DQPSK application.
Exercise 5
Troubleshooting a QPSK/DQPSK Modem
Signal flow tracing. A systematic troubleshooting procedure.
VII
Courseware Outline
QUADRATURE AMPLITUDE MODULATION (QAM/DQAM)
Introduction
Quadrature Amplitude Modulation
Digital modulation. M-ary signaling. Quadrature Amplitude
Modulation. Bandwidth efficiency. Constellation diagrams.
Exercise 1
QAM Modulation
The QAM waveform. QAM constellations. A typical QAM modulator.
Symbol rate and bandwidth.
Exercise 2
QAM Demodulation
Demodulation and detection. QAM demodulation. Carrier recovery.
Detection of the demodulated signals. Phase ambiguity.
Exercise 3
Differential QAM (DQAM)
Review of phase ambiguity. Using differential encoding to overcome
phase ambiguity. DQAM using v.22 bis. Advantages and
disadvantages of differential encoding. Differential encoding in the
QAM/DQAM application.
Exercise 4
Data Scrambling and Descrambling
The purpose of data scrambling and descrambling. Scrambling and
descrambling circuits. The choice of polynomial. Descrambler
impulse response. Scrambling and descrambling in the QAM/DQAM
application.
Exercise 5
Troubleshooting a QAM/DQAM Modem
Signal flow tracing. A systematic troubleshooting procedure.
VIII
Courseware Outline
ASYMMETRIC DIGITAL SUBSCRIBER LINE (ADSL)
Introduction
ADSL Basics
ADSL Data Transmission Rates. ADSL Deployment. ADSL
Concept. Orthogonal Frequency Division Multiplexing (OFDM).
Discrete Multitone (DMT) Modulation.
Exercise 1
ADSL Signal Spectral Analysis
ADSL Subcarrier Distribution. ADSL Maximum Data Transmission
Rates. Quadrature Amplitude Modulation of the Subcarriers. The
Lab-Volt ADSL Application.
Exercise 2
ADSL Signal Generation
ADSL Signal Generation Using DMT Modulation. ATU Transmitter
Block Diagram. Tone Ordering and Constellation Encoder.
Hermitian Symmetry. Inverse Fast Fourier Transform (IFFT). Cyclic
Prefix. Conversion of the Time-Domain Samples into an Analog
Signal.
Exercise 3
ADSL Signal Demodulation
Introduction. ATU Receiver Block Diagram. ADSL Signal Sampling
and Frame Synchronization. Cyclic Prefix Removal. Fast Fourier
Transform (FFT). Constellation Decoder. Data Transmission Rate
Adaptation.
Exercise 4
Framing, Synchronization, and Error Detection
ADSL Superframe Structure. Frame Synchronization. Superframe
Synchronization. Error Detection. Net Data Rate versus Aggregate
Data Rate.
Exercise 5
Forward Error Correction Using Reed-Solomon Codes
Introduction to Error Control. Error Detection. Error Correction.
Forward Error Correction. FEC using Reed-Solomon Codes.
Reed-Solomon Error Correction in ADSL Applications. Total Data
Rate versus Aggregate Data Rate.
Exercise 6
Data Interleaving
The Concept of Data Interleaving. Enhancing Forward Error
Correction using Data Interleaving. Data Interleaving in ADSL
Applications. Reed-Solomon Error Correction Enhancement using
Data Interleaving.
IX
Courseware Outline
ASYMMETRIC DIGITAL SUBSCRIBER LINE (ADSL)
Exercise 7
Convolutional Coding in ATU Transmitters
Convolutional-Coding Forward Error Correction. Bit Extractor and
Trellis Encoder in ATU Transmitters. Convolutional Encoder Used
in the Trellis Encoder of ATU Transmitters. Convolutional Coding of
Data Bits u1 and u2 in ATU Transmitters.
Exercise 8
Trellis-Coded Modulation in ATU Transmitters
Introduction to the Trellis-Coded Modulation. Mapping by Set
Partitioning. Selecting Points in Constellations for Each Pair of
Tones. The Enhanced Immunity of TCM against Noise-Caused
Errors. Trellis Encoder Block Diagram. 4-D Cosets Used in ADSL
Applications.
Exercise 9
Viterbi Decoding in ATU Receivers
Introduction to Viterbi Decoding. Error Correction Capability of the
Viterbi Decoder in ATU Receivers. Summary of the Error Correction
Capability of ATU Receivers.
Appendix A
Convolutional Coding
Introduction. A Simple Convolutional Encoder. Encoder Operation
Analysis. Convolutional Coding Example.
Appendix B
Decoding Convolutionally-Encoded Data
Introduction. Decoding Example. Finding the Continuous Path in the
Trellis Diagram. Error Correction Example.
Appendix C
Viterbi Decoding
Introduction. Error Correction Example. Introduction to the Viterbi
Decoding. The Viterbi Decoding Algorithm.
X
Sample Exercise
Extracted from
Quadrature Phase Shift Keying
(QPSK/DQPSK)
Exercise
1
QPSK Modulation
EXERCISE OBJECTIVE
When you have completed this exercise, you will be familiar with QPSK
modulation, with the characteristics of QPSK signals and with the QPSK signal
constellation. You will also be familiar with the LVCT software and the use of the
virtual instruments.
DISCUSSION OUTLINE
The Discussion of this exercise covers the following points:
ƒ
ƒ
ƒ
ƒ
The QPSK waveform
QPSK constellations
A typical QPSK modulator
Symbol rate and bandwidth
DISCUSSION
The QPSK waveform
* Filters are usually used
near the output of a QPSK
modulator in order to restrict
the bandwidth. This results
in amplitude variations in
the QPSK signal. Although
these amplitude variations
facilitate timing recovery in
the demodulator, they do
not convey data. Only the
phase of the waveform
conveys the data.
With quadrature phase shift keying modulation (also called quaternary PSK,
quadriphase PSK or 4-PSK), a sinusoidal waveform is varied in phase while
keeping the amplitude* and frequency constant. The term quadrature indicates
that there are four possible phases.
Equation (3) shows the general expression for a QPSK waveform.
s i (t ) = A cos[ω c t + ϕ 0 + ϕ i (t )]
where
si
t
A
ωc
φ0
φi
i
(3)
is the PSK signal waveform for phase i
is time
is the peak amplitude
is the carrier frequency in radians/s ( ω c = 2πfc )
is the reference phase angle
is phase i
ranges from 1 to 4
The instantaneous phase has discrete values equal to ϕ 0 +
2πi
, where i = 1, 2,
4
3, or 4.
QPSK constellations
The ideal PSK constellation has M equidistant phase states and constant
amplitude, resulting in a circular symmetry. With QPSK, therefore, M = 4 and the
phases are separated by 90°, as shown in Figure 4.
Quadrature Phase Shift Keying (QPSK/DQPSK)
9
Exercise 1 – QPSK Modulation  Discussion
Figure 4 shows two common representations of the QPSK constellation. The
constellation points are arbitrarily labeled A, B, C and D, each of which
represents one of the four possible dibits 00, 01, 10, and 11. The mapping
between the dibits and the constellation points depends on the modulator circuit.
Beside each constellation in Figure 4 is a plot showing all four phases
(modulation symbols) as sinusoids. In each of these representations, the four
phases are spaced 90° (π/2 radians) apart. The only difference between these
representations is the choice of the reference phase angle (φ0 in Equation (3)).
A
Q
B
B
C
D
A
I
C
D
a) QPSK (φ = π/4, 3π/4, 5π/4, 7π/4)
B
A
Q
B
C
D
A
I
C
D
b) QPSK (φ = 0, π/2, π, 3π/2)
Figure 4. QPSK constellation and waveforms.
A typical QPSK modulator
A QPSK signal can be generated by independently modulating two carriers in
quadrature (cos ωt and sin ωt), as shown in Figure 5.
The Serial to Parallel Converter groups the incoming data into dibits (groups of
two consecutive bits). Each time two bits have been clocked serially into its
buffer, the Serial to Parallel Converter outputs one dibit in parallel at its two
outputs.
One bit of each dibit is sent to the I channel of the modulator; the other bit is sent
to the Q channel of the modulator. Each channel of the modulator works
independently to processes the stream of bits it receives.
10
Quadrature Phase Shift Keying (QPSK/DQPSK)
Exercise 1 – QPSK Modulation  Discussion
The starting point for grouping bits into dibits is completely arbitrary. For
educational purposes, the Serial to Parallel Converter in the QPSK application
has a Drop 1 Bit button. Clicking this button causes the Serial to Parallel
Converter to ignore one bit in the data sequence. This changes the grouping of
all subsequent data bits into dibits.
The Level Converter in each channel converts the data into a (baseband) bipolar
pulse stream that can be applied to one input of the mixer. To restrict the
bandwidth of the QPSK signal, a Low-Pass Filter is usually used before the mixer
in each channel of the modulator in order to provide the desired spectral shaping.
In addition, a bandpass filter (not shown in Figure 5) may be used to filter the
QPSK signal before transmission.
Level
Converter
Binary
Data
Input
I Channel
Low-Pass
Filter
Serial to
Parallel
Converter
cos ωt
Level
Converter
Low-Pass
Filter
Σ
QPSK
Signal
Q Channel
sin ωt
Figure 5. Simplified block diagram of a QPSK modulator.
The I- and Q-channel sinusoidal carriers cos ωt and sin ωt are in quadrature (90°
out of phase). Each mixer performs modulation by multiplying the carrier by the
bipolar data signal in order to produce a BPSK signal. The effect of the mixer is
to shift the frequency spectrum of the baseband signal up to the frequency of the
carrier.
Orthogonal signals can be
summed, transmitted in a
channel and (theoretically)
perfectly separated in the
demodulator without any
mutual interference.
If the levels of the bipolar
pulses d0, d1, etc. are +1
and -1, the peak amplitude
of the waveform represented by Equation (4) is
2 . The factor 1
2
could be included in this
equation to normalize the
amplitude to unity.
The two BPSK signals are summed to produce the QPSK signal. Because these
two BPSK signals are generated using two carriers in phase quadrature, the
BPSK signals are orthogonal, and the QPSK demodulator will be able to
demodulate them separately.
The output signal of the modulator is a sinusoidal carrier with four possible
phases, each of which represents a two-bit symbol. This signal can be
represented by Equation (4).
s(t ) = d I (t ) cos(ωt ) + d Q (t ) sin(ωt )
where
s(t)
dI(t)
dQ(t)
ω
(4)
is the QPSK signal waveform
is the I-channel bipolar pulse stream d0, d2, d4 …
is the Q-channel bipolar pulse stream d1, d3, d5 …
is the angular frequency
Figure 6 shows the waveforms present in a modulator with no filtering. The
bipolar I-channel and Q-channel pulses have levels of +1 and -1. The QPSK
signal shown in Figure 6 has discontinuities which increase the bandwidth of the
signal. The Low-Pass Filters shown in Figure 5 smooth the discontinuities and
decrease the effective bandwidth.
Quadrature Phase Shift Keying (QPSK/DQPSK)
11
Exercise 1 – QPSK Modulation  Discussion
Note: Figure 6 shows all waveforms synchronized in time. In a real system,
processing delays will cause successive signals to be slightly offset in time.
Figure 6 shows the dibit 11 mapped to the constellation point in the first
quadrant. Other mappings are possible. Such mappings usually use a Gray code
to ensure that only one bit changes between adjacent symbols. As a result,
QPSK modulators map the dibits 00 and 11 to opposite quadrants.
Data Bit Stream b0, b1, b2 …
1
b0
b1
b2
b3
b4
b5
b6
b7
b8
b9
0
I-Channel Pulses d0, d2, d4 …
(even bits)
Q-Channel Pulses d1, d2, d5 …
(odd bits)
1
0
−1
1
0
−1
d0
d2
d4
d6
d8
d1
d3
d5
d7
d9
I-Channel BPSK Signal
Q-Channel BPSK Signal
QPSK Signal
11
Constellation Points and Dibits
(This is an example, other
mappings are possible)
01
11
10
00
Figure 6. QPSK signal generation from two BPSK signals.
Symbol rate and bandwidth
Because each symbol represents two bits, the rate that the symbols occur in the
QPSK signal (the symbol rate) is one half the bit rate. Table 2 compares the
symbol rates (and bandwidths) for BPSK and QPSK.
Table 2. Symbol rate and bandwidth for BPSK and QPSK.
12
Modulation
Bits per symbol
Symbol rate vs. Bit rate
First-nulls bandwidth
BPSK
1
Rs = Rb
2R b
QPSK
2
Rs =
Rb
2
Rb
Quadrature Phase Shift Keying (QPSK/DQPSK)
Exercise 1 – QPSK Modulation  Discussion
The bandwidth of a modulated signal depends on the rate of change in the signal
(i.e. the symbol rate) and not on the magnitude of each change. For this reason,
using QPSK rather than BPSK will reduce by one-half the bandwidth required for
a given bit rate. Alternatively, using QPSK can double the bit rate for a given
signal bandwidth. This is illustrated in Figure 7, where fc is the carrier frequency.
Bandwidth
BPSK
fc − 2Rb
fc − Rb
fc
fc + Rb
fc + 2Rb
Bandwidth
QPSK
fc − 4Rs
fc − 3Rs
fc − 2Rs
fc − Rs
fc
fc + Rs
fc + 2Rs
fc + 3Rs
fc + 4Rs
Figure 7. BPSK and QPSK magnitude spectrum (for equal bit rates).
Figure 7 shows that the first-nulls bandwidth of a BPSK signal is 2Rb and that of
R
a QPSK signal with the same bit rate is 2Rs = Rb. Since R s = b for QPSK, the
2
bandwidth efficiency of QPSK is twice that of BPSK.
The modulated signal is called a double-sideband suppressed-carrier signal,
since its bandwidth is twice that of the baseband signal and there is no isolated
signal at the carrier frequency.
Quadrature Phase Shift Keying (QPSK/DQPSK)
13
Exercise 1 – QPSK Modulation  Procedure Outline
PROCEDURE OUTLINE
The Procedure is divided into the following sections:
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
PROCEDURE
Set up and connections
Observing binary sequences on the Oscilloscope
Observing binary sequences on the Spectrum Analyzer
Using the Logic Analyzer
The Serial to Parallel Converter
Level Converter
The Filters and mixers
The summer
Signal constellations
Set up and connections
1. Turn on the RTM Power Supply and the RTM and make sure the RTM power
LED is lit.
File f Restore Default Settings
returns all settings to their
default values, but does not
deactivate activated faults.
2. Start the LVCT software. In the Application Selection box, choose
QPSK/DQPSK and click OK. This begins a new session with all settings set
to their default values and with all faults deactivated.
Tip:
If the software is already running, choose Exit in the File menu and restart
LVCT to begin a new session with all faults deactivated.
3. Make the Default external connections shown on the System Diagram tab of
the software. For details of connections to the Reconfigurable Training
Module, refer to the RTM Connections tab of the software.
Tip:
Click the Default button to show the required external connections.
4. As an option, connect a conventional oscilloscope to the BSG CLOCK
OUTPUT and the BSG DATA OUTPUT, using BNC T-connectors. Use the
BSG SYNC./2 OUTPUT as an external trigger.
Tip:
On-line help is accessible from the Help menu of the software and the Help
menu of each instrument.
You can print out the screen of any instrument by choosing File f Print in that
instrument.
Observing binary sequences on the Oscilloscope
5. Make the following Generator Settings:
Generation Mode........................Pseudo-Random
n..................................................4
Bit Rate.......................................2000 bit/s
14
Quadrature Phase Shift Keying (QPSK/DQPSK)
Exercise 1 – QPSK Modulation  Procedure
Settings
This application has tables of settings that allow you to change various software
parameters in order to configure the system. Two Settings tables are provided –
QPSK Settings and Generator Settings. By default, these tables are located at
the right side of the main window and only one of these tables is visible at a time.
Two tabs at the bottom allow you to select which table is visible and the name of
the visible table is displayed at the top. (Refer to on-line help for more
information.)
Settings tables have two columns: the name of each setting is shown in the left
column and the current value of each setting is shown in the right column. The
column separator can be moved using the mouse, and the entire table can be
resized as desired.
Some settings have a drop list of possible values. To change this type of setting,
click the setting and then click the down arrow to display the drop list and select a
new value. You can also double-click the setting name or value to cycle through
the available values.
Some settings contain an editable numerical value. To change a numerical
setting, simply select or delete the current value in the settings table, type a new
value and press Enter or Tab.
When you change the value of a numerical setting, the focus remains on that
setting until you click elsewhere in the software. To immediately change the
setting to another value, you can simply type the new value and press Enter.
6. Click the QPSK Modulator tab in order to display the QPSK Modulator
diagram.
Show the Probes bar (click
in the toolbar or choose View f Probes Bar).
Connect the Oscilloscope probes as follows:
Oscilloscope Probe
Connect to
Signal
1
TP2
CLOCK INPUT
2
TP1
DATA INPUT
E
TP3
BSG (Binary Sequence Generator)
SYNC. OUTPUT
Tip:
To move a probe from the Probes bar to a test point, click the probe and
release the mouse button. Then move the mouse until the tip of the probe is
over the test point and click the mouse button to connect the probe.
To move a probe from one test point to another, move the mouse pointer over
. Then click the
the probe until the pointer changes into a grasping hand
probe and without releasing the mouse button, drag the probe to another test
point and then release the mouse button.
7. Show the Oscilloscope (click
in the toolbar or choose Instruments f
Oscilloscope). Figure 8 shows an example of settings and what you should
observe.
Quadrature Phase Shift Keying (QPSK/DQPSK)
15
Exercise 1 – QPSK Modulation  Procedure
Note: Unless you are instructed to make specific settings, you can use any system
and instrument settings that will allow you to observe the phenomena of
interest. As a guide, important settings that were used to produce a figure may
be shown beside the figure.
Generator Settings:
Generation Mode.......... Pseudo-Random
n ..............................................................4
Bit Rate .....................................2000 bit/s
Oscilloscope Settings:
Channel 1.......................................5 V/div
Channel 2.......................................5 V/div
Channel E ......................................5 V/div
Time Base................................... 1 ms/div
Trigger: Slope .................................Rising
Trigger: Level...................................... 1 V
Trigger: Source ................................... Ext
Figure 8. Clock, Sync. and PRBS Data digital (TTL level) signals.
Tip:
To view Channel 1 and Channel 2 on the Oscilloscope, you must set the
corresponding Input settings to On. To view Channel E (designed for external
triggering), you must set Visible to On.
Channel 1 on the Oscilloscope shows the clock signal. Channel E (External)
shows the BSG SYNC. signal, which is used as the trigger source for the
Oscilloscope. This signal goes high for one clock period at the beginning of
each sequence period. Note that the level changes of the pulses in the other
signals align with the rising edges of the clock signal.
Channel 2 shows a pseudo-random binary sequence (PRBS). With, n = 4 in
the Generator Settings, the length L = 24-1 = 15. Count the number of clock
cycles from one sync. pulse to the next to verify that this is the case. Note
that the PRBS begins to repeat at the second sync. pulse.
Tip:
To refresh and freeze the display, click the
button in the instrument toolbar.
This refreshes the display once and freezes it. You can also press F5 or
, press F6 or choose View f
choose View f Single Refresh. Click
Continuous Refresh to resume normal operation.
8. Experiment with the Binary Sequence Generator by changing the value of n
and the Bit Rate. Adjust the Time Base on the Oscilloscope as necessary.
Tip:
16
In order for the Oscilloscope to trigger properly, the Time Base must be set so
that at least one complete period of the Trigger Source signal is displayed on
the screen.
Quadrature Phase Shift Keying (QPSK/DQPSK)
Exercise 1 – QPSK Modulation  Procedure
Observing binary sequences on the Spectrum Analyzer
9. Minimize the Oscilloscope. Connect the Spectrum Analyzer probe to TP1
(you do not need to disconnect the Oscilloscope probe).
Show the Spectrum Analyzer (click
in the toolbar or choose
Instruments f Spectrum Analyzer). Figure 9 shows an example of settings
and what you should observe. In the Generator Settings, vary the value of n
and the Bit Rate and observe the effect on the spectrum.
Tip:
To reduce fluctuations in the displayed spectrum, set Averaging to the number
of consecutive spectra to be averaged. The higher the setting, the lower the
fluctuations, however, the spectrum will take longer to stabilize after a change.
Generator Settings:
Generation Mode.......... Pseudo-Random
n ..............................................................3
Bit Rate .....................................5000 bit/s
Spectrum Analyzer Settings:
Maximum Input .............................10 dBV
Scale Type.............................Logarithmic
Scale ..........................................10 db/div
Averaging................................................4
Time Window ................................Square
Frequency Span ........................2 kHz/div
Reference Frequency .............................0
Cursors .........................................Vertical
Figure 9. Spectrum of a PRBS.
Theoretically, the spectral
lines have an infinitesimal
width. On a spectrum analyzer, however, they appear
as bars or peaks. If the
spectral lines are very close
together, they are not resolved by the Spectrum
Analyzer and the spectrum
appears to be continuous.
Tip:
Use a vertical cursor, as shown in the figure, to determine the approximate
frequency of various spectral elements. You can position each cursor by
dragging it with the mouse.
Describe the spectrum of a baseband PRBS.
10. In the Generator Settings, set the Generation Mode to User Entry. Enter
different binary sequences in the Binary Sequence setting and observe the
result using both the Oscilloscope and the Spectrum Analyzer.
Tip:
When the Generation Mode is set to User Entry, the Binary Sequence
Generator generates a repeating binary sequence defined by the Binary
Sequence setting. You can enter up to 32 binary digits (1s and 0s) in this
setting. You can include spaces in this setting to make the pattern more legible
(the software ignores spaces in this setting).
Quadrature Phase Shift Keying (QPSK/DQPSK)
17
Exercise 1 – QPSK Modulation  Procedure
Using the Logic Analyzer
11. Connect the Logic Analyzer probes as follows:
Logic Analyzer Probe
Connect to
Signal
C
TP2
CLOCK INPUT
2
TP1
DATA INPUT
1
TP3
BSG SYNC. OUTPUT
Show the Logic Analyzer (click
in the toolbar or choose Instruments f
Logic Analyzer). Make the Logic Analyzer settings shown in Figure 10.
Make the following Binary Sequence Generator settings:
Generation Mode........................Pseudo-Random
n..................................................4
Bit Rate.......................................2000 bit/s
Click
in the Logic Analyzer toolbar to record data. Figure 10 shows an
example of settings and what you should observe. Compare the signals as
displayed on the Logic Analyzer with the same signals as displayed on the
Oscilloscope.
Generator Settings:
Generation Mode.......... Pseudo-Random
n ..............................................................4
Bit Rate .....................................2000 bit/s
Logic Analyzer Settings:
Display Width..................................10 ms
Clock Grid ............................ Falling Edge
Source............................................... Ch 1
Source Edge ...................................Rising
Clock Edge .................................... Falling
S1 Data .............................................[ch1]
S2 Data .............................................[ch2]
Figure 10. Clock, sync. and data on Logic Analyzer.
Note that the signals displayed on the Oscilloscope and on the Logic
Analyzer are very similar. With the Logic Analyzer settings shown in
Figure 10, however, the level changes of the pulses in the Sync. signal
(Ch 1) and in the Data signal (Ch 2) align with the falling edges of the Clock
signal.
Logic Analyzer operation
The Logic Analyzer does not display data in real time. Instead, after you click ,
it waits for the trigger and then begins recording data. When its memory is full, it
stops recording and displays the recorded data.
18
Quadrature Phase Shift Keying (QPSK/DQPSK)
Exercise 1 – QPSK Modulation  Procedure
The Source setting determines which signal is used to trigger the recording and
the Source Edge setting determines whether the rising edge or the falling edge
of this signal triggers the recording.
When recording data, the Logic Analyzer samples each channel only once per
clock period. The display shows either a high level (1) or a low level (0) in the
corresponding trace for each sample taken. The Clock Edge setting determines
whether the sampling instants correspond to the rising edges or the falling edges
of the clock signal. (For this reason, the Logic Analyzer cannot display the
precise timing relationship between signals as does the Oscilloscope.)
The following sequence shows how the Logic Analyzer records data:
•
The user clicks
•
The Logic Analyzer waits for the selected Source Edge (Rising or Falling) of
the trigger Source signal.
•
The Logic Analyzer takes one sample of each channel at each selected
Clock Edge (Rising or Falling) until 256 samples of each channel have been
recorded. It then updates the display.
or presses F5 or selects View f Record.
The Oscilloscope shows that the transitions in the DATA INPUT signal occur on
the rising edges of the clock signal. Therefore it is preferable to set Clock Edge to
Falling as this ensures that the signal will be sampled in the middle of each bit,
where the signal voltage is not changing. (Setting Clock Edge to Rising would
cause the Logic Analyzer to sample the DATA INPUT signal exactly where the
transitions occur, which could result in ambiguous values.)
To observe the output of a functional block that is falling-edge triggered, as
indicated by the symbol
at the clock input, it is preferable to set Clock Edge
to Rising.
The Serial to Parallel Converter
12. Make the following Binary Sequence Generator settings:
Generation Mode........................User Entry
Binary Sequence ........................1001 1000 1110 1110
Bit Rate.......................................2000 bit/s
The Serial to Parallel Converter groups the input data stream into dibits and
sends the first bit of each dibit to the I Channel of the modulator and the
second bit to the Q Channel of the modulator. Since the Serial to Parallel
Converter is not synchronized with the data, the grouping into dibits can start
at any bit. Because the above Binary Sequence consists of an even number
of bits, there are two possible conditions: A) the grouping starts with the first
bit of the sequence shown above, giving dibits 10, 01, 10, etc. or B) the
grouping starts with the second bit of the sequence shown above, giving
dibits 00, 11, 00, etc.
Note: If the grouping starts with any other bit, the result is equivalent to condition A
or B, since the sequence repeats indefinitely.
Quadrature Phase Shift Keying (QPSK/DQPSK)
19
Exercise 1 – QPSK Modulation  Procedure
The first row of Table 3 shows the data bits from this Binary Sequence. After
16 bits, the sequence begins to repeat. A and B in the table represent two
ways the data bits can be grouped into dibits. Complete the two Dibit rows of
this table, grouping the data bits into dibits, starting with 10 for condition A
and 00 for condition B.
Logic Analyzer symbols are
hexadecimal values derived
from combinations of binary
data in selected channels.
They should not be confused
with the symbols used in
M-aray signaling.
In this manual, the channel
selections for each Logic
Analyzer symbol, and the
hexadecimal symbol values,
are shown in square brackets.
Channels and symbols
The Logic Analyzer display includes a Clock channel, eight data channels
Ch 1 to Ch 8, each of which displays the sampled binary data (1s and 0s)
from one probe, as well as two “symbol” channels S1 and S2. Each of these
symbol channels displays a series of hexadecimal numbers that result from
combining the binary data from selected data channels.
The data channels that contribute to each symbol channel are selected using
the Symbol buttons near the bottom of the screen. By default, all Symbol
buttons are up (no channels are selected). Each selected channel
contributes one bit to the hexadecimal symbol value; the most significant bit
(MSB) corresponding to the leftmost pressed-down button and the least
significant bit (LSB) corresponding to the rightmost pressed-down button.
For example, if channels [ch1, ch3, ch6, ch7] are selected for Symbol 1, the
hexadecimal values displayed in the S1 channel correspond to 23 × Ch 1 +
22 × Ch 3 + 21 × Ch 6 + 20 × Ch 7. In this case, since four data channels are
combined into one symbol, the symbol values can range from [0] to [F]
(00002 to 11112). If only two data channels are combined into one symbol,
the symbol values can range from [0] to [3] (002 to 112).
Represent each of the dibits in Table 3 as a hexadecimal value where, if the
two digits of the dibit are (b1, b0), the hexadecimal value is 2 × b1 + b0. This
will help in interpreting the symbols displayed by the Logic Analyzer.
Table 3. Serial to Parallel Converter inputs and outputs.
Data Bits
1
0
Dibit
1
0
A
B
Hex
0
1
1
0
0
0
1
1
1
0
1
1
1
0
1
2
Dibit
0
Hex
0
0
13. Connect two more Logic Analyzer probes as follows:
Note: Connect the probes exactly as shown so that the Logic Analyzer will display
the symbols as shown in Table 3.
20
Logic Analyzer Probe
Connect to
Signal
3
TP6
Serial to Parallel Converter output (MSB)
4
TP7
Serial to Parallel Converter output (LSB)
Quadrature Phase Shift Keying (QPSK/DQPSK)
Exercise 1 – QPSK Modulation  Procedure
Tip:
To make it easier to connect the probes, you may wish to zoom into this region
of the diagram. To zoom in a diagram, right-click on the diagram and choose
.
Zoom in the context-sensitive menu. This changes the mouse pointer to
Drag the mouse pointer up or down to zoom in or out. Another way to zoom is
to click the diagram and roll the mouse wheel.
14. Record data with the Logic Analyzer and examine the data. Using the
Symbol buttons, set Symbol 1 to [ch2] and Symbol 2 to [ch3, ch4].
Examine the data displayed by the Logic Analyzer. Figure 11 and Figure 12
show the two possible conditions, depending on how the Serial to Parallel
Converter groups the data sequence into dibits.
Click the Drop 1 Bit button once only in the Serial to Parallel Converter and
perform another recording. Ch 2 and S1, the input data, will not change but
the results in Ch 3, Ch 4 and S2 should be different.
Under each of Figure 11 and Figure 12, identify which of the two possible
conditions (A or B) from Table 3 the figure represents.
Note: Because the Serial to Parallel Converter operates on two bits at a time, it
introduces a slight delay in the output bit streams. The timing relationship
changes slightly after clicking Drop 1 Bit.
Logic Analyzer Settings:
Display Width..................................10 ms
Source............................................... Ch 1
Source Edge ...................................Rising
Clock Edge .................................... Falling
S1 Data .............................................[ch2]
S2 Data .....................................[ch3, ch4]
Figure 11. Serial to Parallel Converter input (Ch 2) and outputs (Ch 3 and Ch 4).
Figure 11 represents:
Quadrature Phase Shift Keying (QPSK/DQPSK)
… Condition A
… Condition B
21
Exercise 1 – QPSK Modulation  Procedure
Figure 12. Serial to Parallel Converter input (Ch 2) and outputs (Ch 3 and Ch 4).
Figure 12 represents:
… Condition A
… Condition B
15. Use the oscilloscope to determine the exact timing relationship of the
different signals. Since this requires observing several signals at a time, it will
be helpful to use the memory of the Oscilloscope.
Tip:
Click M1 or M2 in the instrument toolbar to store the current display in
Memory 1 or Memory 2. Use the Memories setting to show the contents of
Memory 1, Memory 2, or both.
Is the output of the Serial to Parallel Converter triggered by the rising edge or
the falling edge of the clock signal? Does this correspond to the symbol used
at the clock input of the Serial to Parallel Converter?
Level Converter
16. Connect the Oscilloscope probes as follows:
Oscilloscope Probe
Connect to
Signal
1
TP6
Serial to Parallel Converter output (MSB)
2
TP10
I-channel Level Converter output
E
TP5
Frequency Divider output
Tip:
22
To disconnect a probe and return it to the Probes bar, you can right-click the
probe and choose Disconnect Probe in the context-sensitive menu.
Alternatively, you can double-click the probe’s place holder in the Probes bar.
Quadrature Phase Shift Keying (QPSK/DQPSK)
Exercise 1 – QPSK Modulation  Procedure
Note: The Frequency Divider divides the BSG SYNC. signal frequency in order to
generate a signal that can be used as a trigger for the Oscilloscope or the
Logic Analyzer. This is necessary when observing the Serial to Parallel
Converter output with a binary sequence having an odd number of bits. (All
pseudo-random sequences have an odd number of bits.)
Figure 13 shows an example what you may observe.
Generator Settings:
Generation Mode.......... Pseudo-Random
n ..............................................................3
Bit Rate .....................................1500 bit/s
Oscilloscope Settings:
Channel 1.......................................5 V/div
Channel 2.......................................2 V/div
Channel E ......................................5 V/div
Time Base................................... 1 ms/div
Trigger: Source ................................... Ext
Figure 13. Level Converter input and output signals.
Explain the operation of the Level Converter.
The Filters and mixers
17. On the Oscilloscope, store the current waveforms in Memory 1. Then
connect the probes as follows.
Oscilloscope Probe
Connect to
Signal
1
TP12
I-channel Filter output
2
TP16
I-channel mixer output
Figure 14 shows what you could observe.
Quadrature Phase Shift Keying (QPSK/DQPSK)
23
Exercise 1 – QPSK Modulation  Procedure
QPSK Settings:
Carrier Frequency....................... 3000 Hz
Generator Settings:
Generation Mode.......... Pseudo-Random
n ..............................................................3
Bit Rate .....................................1500 bit/s
Oscilloscope Settings:
Channel 1.......................................2 V/div
Channel 2.......................................2 V/div
Channel E ............................................Off
Time Base................................... 1 ms/div
Trigger: Source ................................... Ext
Memories ..................................Memory 1
Figure 14. Level Converter and mixer inputs (Ch 1) and outputs (Ch 2).
What is the effect of the filter on the bipolar data signal and on the mixer
output signal? What is the advantage of filtering the data signal before
modulation?
18. Using a PRBS as input data to the modulator, use the Spectrum Analyzer to
compare the spectra of the following signals (see Figure 15):
•
The DATA INPUT signal (TP1)
•
The data signal at the MSB output of the Serial to Parallel Converter
(TP6)
•
The bipolar data in the I-channel (TP12) with the Low-Pass Filters both
On and Off.
a. What is the frequency spacing of the nulls in the Input Data spectrum.
What does this correspond to?
b. What is the frequency spacing of the nulls in the spectrum of the Serial to
Parallel output. Explain.
24
Quadrature Phase Shift Keying (QPSK/DQPSK)
Exercise 1 – QPSK Modulation  Procedure
c.
What effect have the Level Converter and the low-pass Filter on the
signal spectrum?
Generator Settings:
Generation Mode ......Pseudo-Random
n ......................................................... 5
Bit Rate................................. 4000 bit/s
Spectrum Analyzer Settings:
Maximum Input......................... 10 dBV
Scale Type ........................ Logarithmic
Scale ..................................... 10 dB/div
Frequency Span.................... 2 kHz/div
Averaging ......................................... 16
Time Window............................ Square
Input Data
I-channel data
I-channel filtered data
Figure 15. Spectra of input data and I-channel bipolar data.
19. Connect Oscilloscope probe E to TP13 (the I-channel carrier signal). Turn
the Low-Pass Filters Off and observe the signals using settings that allow
you to see detail. Then turn the Low-Pass Filters On (see Figure 16 and
Figure 17).
QPSK Settings:
Carrier Frequency....................... 2000 Hz
Generator Settings:
Generation Mode.......... Pseudo-Random
n ..............................................................3
Bit Rate .....................................1500 bit/s
Oscilloscope Settings:
Channel 1.......................................2 V/div
Channel 2.......................................2 V/div
Channel E ......................................2 V/div
Time Base................................... 1 ms/div
Trigger: Source ................................... Ext
Figure 16. I-channel carrier, bipolar data and BPSK signal (Low-Pass Filters Off).
Quadrature Phase Shift Keying (QPSK/DQPSK)
25
Exercise 1 – QPSK Modulation  Procedure
Oscilloscope Settings:
Channel 1.......................................2 V/div
Channel 2.......................................2 V/div
Channel E ......................................2 V/div
Time Base................................... 1 ms/div
Trigger: Source ................................... Ext
Figure 17. I-channel carrier, bipolar data and BPSK signal (Low-Pass Filters On).
Describe how the phase of the BPSK signal changes when the filters are Off
and when they are On.
20. Use the oscilloscope to observe the I- and Q-channel carrier signals. How
are these signals related?
21. Observe the operation of the mixers in both the I and Q channels using
different Carrier Frequency values.
The summer
22. Use the Oscilloscope to observe the signals at the input and output of the
summer (TP16, TP17, and TP18). Figure 18 shows an example.
As an option, use a conventional oscilloscope to observe the signal at the
QPSK Modulator OUTPUT (refer to the RTM Connections tab of the
software).
26
Quadrature Phase Shift Keying (QPSK/DQPSK)
Exercise 1 – QPSK Modulation  Procedure
QPSK Settings:
Carrier Frequency..................... 10000 Hz
Low-Pass Filters ..................................Off
TP16
Oscilloscope Settings:
Channel 1.......................................1 V/div
Channel 2.......................................1 V/div
Channel E ......................................1 V/div
Time Base..................................50 μs/div
Trigger: Source ................................. Ch 1
TP17
TP18
Figure 18. Summer input (BPSK) and output (QPSK) signals.
Describe the operation of the summer.
23. Use the Spectrum Analyzer to observe the spectrum of the QPSK signal and
compare this with the spectrum of the I-channel BPSK signal.
Express the bandwidth of the QPSK signal in terms of the bit rate and the
symbol rate.
Compare the bandwidths and bit rates of the I-channel BPSK signal and the
QPSK signal. Explain why QPSK is considered to be a bandwidth efficient
modulation technique.
Signal constellations
24. Connect the Oscilloscope probes as follows:
Oscilloscope Probe
Connect to
Signal
1
TP10
I-channel Level Converter output
2
TP11
Q-channel Level Converter output
Quadrature Phase Shift Keying (QPSK/DQPSK)
27
Exercise 1 – QPSK Modulation  Procedure
The Logic Analyzer probes should be connected as follows:
Logic Analyzer Probe
Connect to
Signal
C
TP2
CLOCK INPUT
2
TP1
DATA INPUT
1
TP3
BSG SYNC. OUTPUT
3
TP6
Serial to Parallel output (MSB)
4
TP7
Serial to Parallel output (LSB)
Make the following Binary Sequence Generator settings:
Generation Mode........................Pseudo-Random
n..................................................3
Bit Rate.......................................2000 bit/s
Use the Oscilloscope in the X-Y mode to observe the constellation, as shown
in Figure 19.
As an option, connect a conventional oscilloscope to the QPSK Demodulator
I-CHANNEL OUTPUT and QPSK Demodulator Q-CHANNEL OUTPUT (refer
to the RTM Connections tab of the software). Use the conventional
oscilloscope in the X-Y mode to observe the constellation. (The Low-Pass
filters in the QPSK Modulator must be set to On.)
Oscilloscope Settings:
Channel 1.......................................1 V/div
Channel 2.......................................1 V/div
Display Mode .................................... Dots
X-Y .......................................................On
Sampling Window...........................50 ms
Figure 19. QPSK constellation.
What information does this constellation provide?
28
Quadrature Phase Shift Keying (QPSK/DQPSK)
Exercise 1 – QPSK Modulation  Procedure
25. Set the Generation Mode to User-Entry. Set the Binary Sequence to each of
the following two-bit sequences (dibits): 00 and 11. For each sequence,
record data using the Logic Analyzer and note which dibit is present at the
outputs of the Serial to Parallel Converter (see Figure 20).
Display Width.................................10 ms
Source............................................... Ch 1
Source Edge ...................................Rising
Clock Edge .................................... Falling
S1 Data .............................................[ch3]
S2 Data .............................................[ch4]
TP6 (MSB of dibit) is always 0
TP7 (LSB of dibit) is always 0
Figure 20. Logic Analyzer showing the dibit 00 at TP6-TP7.
Observe the Oscilloscope display, for each sequence. Write in the boxes in
Figure 21 the dibits that corresponds to these two constellation points.
[ ]
[ ]
[ ]
[ ]
Figure 21. Dibits in the QPSK constellation.
Set the Binary Sequence to 01. Record data on the Logic Analyzer and note
which dibit is present at the outputs of the Serial to Parallel Converter. Since
TP6 represents the MSB, a 1 at TP6 and a 0 at TP7 represents the dibit 10.
Clicking the Drop 1 Bit button will change this dibit to 01.
Click the Drop 1 Bit button several times, each time observing the dibit using
the Logic Analyzer and observing the display on the Oscilloscope. Then write
in the boxes in Figure 21 the dibits that corresponds to two missing
constellation points. Then write the hexadecimal value for each dibit in the
square brackets.
Quadrature Phase Shift Keying (QPSK/DQPSK)
29
Exercise 1 – QPSK Modulation  Conclusion
26. Enter the Binary Sequence 1100 and observe the constellation. Click the
Drop 1 Bit button and explain what you observe.
27. Enter the Binary Sequence 101. Why does this 3-bit sequence produce three
constellation points, each of which represents two bits?
28. Experiment with various Binary Sequences and observe the results on the
Oscilloscope.
29. When you have finished using the system, exit the LVCT software and turn
off the equipment.
CONCLUSION
In this exercise, you became familiar with the LVCT software and studied the
operation of the basic functional blocks of the QPSK modulator. You observed
that the Serial to Parallel Converter groups the input data stream into dibits that
are processed by two parallel channels, I and Q, and that the starting point of this
grouping is arbitrary. You saw how the Level Converters and the mixers generate
two BPSK signals using two carriers in phase quadrature. You observed that
summing the two BPSK signals produces the QPSK signal. Observing the
spectrum of the QPSK signal showed that QPSK is more bandwidth-efficient than
binary modulation techniques. You also observed the signal constellation on the
oscilloscope for various binary sequences.
REVIEW QUESTIONS
1. Explain what is meant by bandwidth efficiency.
2. How does the bandwidth efficiency of QPSK compare to that of binary
modulation techniques?
30
Quadrature Phase Shift Keying (QPSK/DQPSK)
Exercise 1 – QPSK Modulation  Review Questions
3. What does a constellation diagram represent?
4. What is the role of the mixers in the QPSK modulator?
5. How are the signals at the outputs of the mixers combined to produce the
QPSK signal?
Quadrature Phase Shift Keying (QPSK/DQPSK)
31
Sample Exercise
Extracted from
Quadrature Amplitude Modulation
(QAM/DQAM)
Exercise
1
QAM Modulation
EXERCISE OBJECTIVE
When you have completed this exercise, you will be familiar with QAM
modulation, with the characteristics of QAM signals and with the QAM signal
constellation. You will also be familiar with the LVCT software and the use of the
virtual instruments.
DISCUSSION OUTLINE
The Discussion of this exercise covers the following points:
ƒ
ƒ
ƒ
ƒ
DISCUSSION
The QAM waveform
QAM constellations
A typical QAM modulator
Symbol rate and bandwidth
The QAM waveform
Quadrature Amplitude Modulation or QAM (pronounced “kwam”) is a digital
modulation technique that uses the data to be transmitted to vary both the
amplitude and the phase of a sinusoidal waveform, while keeping its frequency
constant. QAM is a natural extension of binary phase shift keying (BPSK) and
quadrature phase shift keying (QPSK), both of which vary only the phase of the
waveform.
QAM is a type of M-ary
signaling with M equal to
the number of different
symbols.
With 16-QAM, there are
sixteen different symbols
(quadbits):
0000
0100
1000
1100
0001
0101
1001
1101
0010
0110
1010
1110
0011
0111
1011
1111
Each quadbit is represented
by different
modulation
symbol (combination of
phase and amplitude).
The number of different waveforms (unique combinations of amplitude and
phase) used in QAM depends on the modem and may vary with the quality of the
channel. With 16-QAM, for example, 16 different waveforms are available.
64-QAM and 256-QAM are also common. 16,384-QAM is possible in ADSL
modems. In all cases, each different waveform, or amplitude-phase combination,
is a modulation symbol that represents a specific group of bits.
The LVCT Quadrature Amplitude Modulation (QAM/DQAM) application uses
16-QAM. In the modulator, consecutive data bits are grouped together four at a
time to form quadbits and each quadbit is represented by a different modulation
symbol. In the demodulator, each different modulation symbol in the received
signal is interpreted as a unique pattern of 4 bits.
Figure 4 shows all 16 QAM modulation symbols superposed on the same axes.
Four different colors are used in the figure and each color is used for four
different waveforms. Each waveform has a different combination of phase and
amplitude.
Quadrature Amplitude Modulation (QAM/DQAM)
9
Exercise 1 – QAM Modulation  Discussion
Figure 4. All QAM modulation symbols for 16-QAM.
QAM constellations
Figure 5 shows the constellation diagram for 16-QAM. The constellation diagram
is a pictorial representation showing all possible modulation symbols (or signal
states) as a set of constellation points. The position of each point in the diagram
shows the amplitude and the phase of the corresponding symbol. Each
constellation point corresponds (is mapped to) to a different quadbit.
Q
I
Figure 5. 16-QAM constellation (4-bits per modulation symbol).
The Gray code was designed by Bell Labs researcher Frank Gray and
patented in 1953. Gray
codes are widely used in
digital communications.
10
Although any mapping between quadbits and constellation points would work
under ideal conditions, the mapping usually uses a Gray code to ensure that the
quadbits corresponding to adjacent constellation points differ only by one bit.
This facilitates error correction since a small displacement of a constellation point
due to noise will likely cause only one bit of the demodulated quadbit to be
erroneous.
Quadrature Amplitude Modulation (QAM/DQAM)
Exercise 1 – QAM Modulation  Discussion
A typical QAM modulator
A QAM signal can be generated by independently amplitude-modulating two
carriers in quadrature (cos ωt and sin ωt), as shown in Figure 6.
MSB
Quadbits
Binary
Data
Input
Dibits
(dibit pairs)
MSD
D/A
Converter
I Channel
Low-Pass
Filter
LSB
Serial to
Parallel
Converter
QAM Signal
Four-level
analog signals
LSD
MSB
Dibits
D/A
Converter
cos ωt
Low-Pass
Filter
Bi-phase,
bi-level signals
Σ
16 states
(4 phases,
4 levels)
Q Channel
LSB
sin ωt
Figure 6. Simplified block diagram of a QAM modulator.
The Serial to Parallel Converter groups the incoming data into quadbits. Each
time four bits have been clocked serially into the its buffer, the Serial to Parallel
Converter outputs one quadbit in parallel at its four outputs.
Colors (red, green, blue, and
violet) are used in the data
bit stream to help distinguish
the individual bits.
The starting point for grouping bits into quadbits is completely arbitrary. Figure 7
shows an example using the repeating 12-bit binary sequence 1000 0000 0000.
In this figure, the grouping initially starts at the beginning of the sequence
(Condition A). The first quadbit at the output is 1000 followed by two all-zero
quadbits 0000. Then the quadbit pattern repeats.
Serial to Parallel
Converter
Quadbits Out (parallel)
1 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 …
TP6
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 …
Data Bits In (serial)
1000 0000 0000 1000 0000 0000…
TP7
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 …
TP4
TP8
0 0 0 0 0 0 0 0 1 0 0 1 0 0 1 0 0 1 …
Time
Drop 1 Bit
Condition A
Condition B
TP9
One bit dropped
Figure 7. Serial to Parallel Converter operation with repeating sequence 1000 0000 0000.
In the QAM/DQAM application, the Drop 1 Bit button is included in the Serial to
Parallel Converter for educational purposes. Clicking this button causes the
Serial to Parallel Converter to ignore one bit in the data sequence. This changes
the grouping of all subsequent data bits into quadbits (see Condition B in
Figure 7).
Quadrature Amplitude Modulation (QAM/DQAM)
11
Exercise 1 – QAM Modulation  Discussion
Each quadbit consists of a pair of dibits, which can be called the most significant
dibit (MSD) and the least significant dibit (LSD). The MSD is sent to the I-channel
of the modulator; the LSD is sent to the Q-channel of the modulator. Each
channel of the modulator works independently to processes the data it receives.
In the QAM/DQAM application, the MSB input of the
D/A Converter determines
the sign of the output voltage and the LSB input determines the magnitude of
the output voltage.
The D/A Converter in each channel converts the dibit stream into a (baseband)
four-level pulse stream that can be applied to one input of the mixer. Each of the
four levels represents a specific dibit. The four levels used are proportional to -3,
-1, +1, and +3. This makes the distribution of the constellation points uniform.
To restrict the bandwidth of the QAM signal, a low-pass filter is usually used
before the mixer in each channel of the modulator in order to provide the desired
spectral shaping. In addition, a bandpass filter (not shown in Figure 6) may be
used to filter the QAM signal before transmission.
Each mixer performs modulation by multiplying the sinusoidal carrier by the fourlevel data signal. Multiplying the carrier by ±1 causes a 180° phase shifts in the
mixer output signal and is equivalent to BPSK modulation. Multiplying by +3
causes a three-fold increase in peak amplitude and is essentially a type of ASK
modulation. Multiplying the carrier by -3 causes a 180° phase shift and a threefold increase in peak amplitude. The mixer output signal is therefore a bi-phase,
bi-level sinusoidal signal. The effect of the mixer is to shift the frequency
spectrum of the baseband signal up to the frequency of the carrier.
Table 2 shows the mapping used in the QAM/DQAM application from dibit to
relative pulse level (shown in brackets) and the resulting waveforms. In this
mapping, the first bit (MSB) of each dibit determines the phase of the mixer
output signal and the second bit (LSB) determines the amplitude.
Table 2. Mapping of dibit to pulse level to waveform in one channel of the modulator.
Dibit, (Relative Pulse Level), and Waveform
Orthogonal signals can be
summed, transmitted in a
channel and (theoretically)
perfectly separated in the
demodulator without any
mutual interference.
12
0 0 (+1)
0 1 (+3)
1 0 (-1)
1 1 (-3)
The two bi-phase, bi-level signals are summed to produce the QAM signal.
Because these two bi-phase, bi-level signals are generated using orthogonal
carriers (in phase quadrature), the signals themselves are orthogonal, and the
QAM demodulator will be able to demodulate them separately.
The output signal of the modulator is a sinusoidal carrier with 16 possible states,
each of which represents a four-bit symbol (quadbit). This signal can be
represented by Equation (3).
Quadrature Amplitude Modulation (QAM/DQAM)
Exercise 1 – QAM Modulation  Discussion
By convention, the amplitude levels used in the
pulse streams dI(t) and dQ(t)
are proportional to ±1, ±3,
±5, …, up to the number
of different levels required for the type of
QAM used. This makes
the distribution of the constellation points uniform and
ensures optimal error performance in the presence of
noise.
s(t ) = dI (t ) cos(ωt ) + dQ (t ) sin(ωt )
where
s(t)
dI(t)
dQ(t)
ω
(3)
is the QAM signal waveform
is the I-channel four-level pulse stream d0, d2, d4 …
is the Q-channel four-level pulse stream d1, d3, d5 …
is the angular frequency
Symbol rate and bandwidth
With 16-QAM, each symbol represents four bits. Therefore the rate that the
symbols occur in the QAM signal (the symbol rate) is one quarter the bit rate.
Table 3 compares the symbol rates (and bandwidths) for BPSK, QPSK, and
QAM.
Table 3. Symbol rates and bandwidths.
Modulation
Bits per symbol
Symbol rate vs. Bit rate
First-nulls bandwidth
BPSK
1
Rs = Rb
2R b
QPSK
2
Rs =
Rb
2
Rb
QAM
4
Rs =
Rb
4
Rb
2
The bandwidth of a modulated signal depends on the rate of change in the signal
(i.e. the symbol rate) and not on the magnitude of each change. For this reason,
QAM requires one-half as much bandwidth as QPSK and one-quarter as much
as BPSK for a given bit rate. This is illustrated in Figure 8, where fc is the carrier
frequency. Alternatively, using QAM instead of QPSK or BPSK can double or
quadruple the bit rate for a given signal bandwidth.
Figure 8 shows that, for the same bit rate, the first-nulls bandwidth of a QAM
signal is one-half that of a QPSK signal, and one quarter that of a BPSK. Of the
three modulation techniques, QAM has the highest bandwidth efficiency.
Quadrature Amplitude Modulation (QAM/DQAM)
13
Exercise 1 – QAM Modulation  Procedure Outline
Bandwidth
BPSK
fc−2Rb
fc−Rb
fc
fc+Rb
fc+2Rb
Bandwidth
QPSK
fc−4Rs
fc−3Rs
fc−2Rs
fc−Rs
fc
fc+Rs
fc+2Rs
fc+3Rs
fc+4Rs
fc+2Rs
fc+4Rs
fc+6Rs
fc+8Rs
Bandwidth
16-QAM
fc−8Rs
fc−6Rs
fc−4Rs
fc−2Rs
fc
Figure 8. BPSK, QPSK, and 16-QAM magnitude spectrum (for equal bit rates).
PROCEDURE OUTLINE
The Procedure is divided into the following sections:
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
14
Set up and connections
Observing binary sequences using the virtual instruments
The Serial to Parallel Converter
D/A Converter
The Filters and mixers
The summer
Signal constellations
Quadrature Amplitude Modulation (QAM/DQAM)
Exercise 1 – QAM Modulation  Procedure
PROCEDURE
Set up and connections
1. Turn on the RTM Power Supply and the RTM and make sure the RTM power
LED is lit.
File f Restore Default Settings
returns all settings to their
default values, but does not
deactivate activated faults.
2. Start the LVCT software. In the Application Selection box, choose
QAM/DQAM and click OK. This begins a new session with all settings set to
their default values and with all faults deactivated.
Tip:
If the software is already running, choose Exit in the File menu and restart
LVCT to begin a new session with all faults deactivated.
3. Make the Default external connections shown on the System Diagram tab of
the software. For details of connections to the Reconfigurable Training
Module, refer to the RTM Connections tab of the software.
Tip:
Click the Default button to show the required external connections.
4. As an option, connect a conventional oscilloscope to the BSG CLOCK
OUTPUT and the BSG DATA OUTPUT, using BNC T-connectors. Use the
BSG SYNC./4 OUTPUT as an external trigger.
Tip:
On-line help is accessible from the Help menu of the software and the Help
menu of each instrument.
You can print out the screen of any instrument by choosing File f Print in that
instrument.
Observing binary sequences using the virtual instruments
5. Make the following Generator settings:
Generation Mode........................Pseudo-Random
n..................................................4
Bit Rate.......................................2000 bit/s
Settings
This application has tables of settings that allow you to change various software
parameters in order to configure the system. Two Settings tables are provided –
QAM Settings and Generator Settings. By default, these tables are located at the
right side of the main window and only one of these tables is visible at a time.
Two tabs at the bottom allow you to select which table is visible and the name of
the visible table is displayed at the top. (Refer to on-line help for more
information.)
Settings tables have two columns: the name of each setting is shown in the left
column and the current value of each setting is shown in the right column. The
column separator can be moved using the mouse, and the entire table can be
resized as desired.
Quadrature Amplitude Modulation (QAM/DQAM)
15
Exercise 1 – QAM Modulation  Procedure
Some settings have a drop list of possible values. To change this type of setting,
click the setting and then click the down arrow to display the drop list and select a
new value. You can also double-click the setting name or value to cycle through
the available values.
Some settings contain an editable numerical value. To change a numerical
setting, simply select or delete the current value in the settings table, type a new
value and press Enter or Tab.
When you change the value of a numerical setting, the focus remains on that
setting until you click elsewhere in the software. To immediately change the
setting to another value, you can simply type the new value and press Enter.
6. Click the QAM Modulator tab in order to display the QAM Modulator diagram.
Show the Probes bar (click
in the toolbar or choose View f Probes Bar).
Connect the probes as follows:
Tip:
Oscilloscope Probe
Connect to
Signal
1
TP2
CLOCK INPUT
2
TP1
DATA INPUT
E
TP3
BSG SYNC. OUTPUT
Logic Analyzer Probe
Connect to
Signal
C
TP2
CLOCK INPUT
1
TP3
BSG SYNC. OUTPUT
2
TP1
DATA INPUT
Other Probes
Connect to
Signal
Spectrum Analyzer
TP1
DATA INPUT
To move a probe from the Probes bar to a test point, click the probe and
release the mouse button. Then move the mouse until the tip of the probe is
over the test point and click the mouse button to connect the probe.
To move a probe from one test point to another, move the mouse pointer over
. Then click the
the probe until the pointer changes into a grasping hand
probe and without releasing the mouse button, drag the probe to another test
point and then release the mouse button.
7. Show the Oscilloscope (click
in the toolbar or choose Instruments f
Oscilloscope). Figure 9 shows an example of settings and what you should
observe.
Note: Unless you are instructed to make specific settings, you can use any system
and instrument settings that will allow you to observe the phenomena of
interest. As a guide, important settings that were used to produce a figure may
be shown beside the figure.
16
Quadrature Amplitude Modulation (QAM/DQAM)
Exercise 1 – QAM Modulation  Procedure
Generator Settings:
Generation Mode.......... Pseudo-Random
n ..............................................................4
Bit Rate .....................................2000 bit/s
Oscilloscope Settings:
Channel 1.......................................5 V/div
Channel 2.......................................5 V/div
Channel E ......................................5 V/div
Time Base................................... 1 ms/div
Trigger: Slope .................................Rising
Trigger: Level...................................... 1 V
Trigger: Source ................................... Ext
Figure 9. Clock, Sync. and PRBS data signals.
Tip:
Some settings have a drop list of possible values. To change this type of
setting, click the setting and then click the down arrow to display the drop list
and select a new value. You can also double-click the setting name or value to
cycle through the available values.
Tip:
To view Channel 1 and Channel 2 on the Oscilloscope, you must set the
corresponding Input settings to On. To view Channel E (designed for external
triggering), you must set Visible to On.
Channel 1 on the Oscilloscope shows the Clock signal. Channel E (External)
shows the BSG SYNC. signal, which is used as the trigger source for the
Oscilloscope. This signal goes high for one clock period at the beginning of
each sequence period. Note that the level changes of the pulses in the other
signals align with the rising edges of the clock signal.
Channel 2 shows a pseudo-random binary sequence (PRBS). With, n = 4 in
the Generator Settings, the length L = 24-1 = 15. Count the number of clock
cycles from one sync. pulse to the next to verify that this is the case. Note
that the PRBS begins to repeat at the second sync. pulse.
Tip:
To refresh and freeze the display, click the
button in the instrument toolbar.
This refreshes the display once and freezes it. You can also press F5 or
, press F6 or choose View f
choose View f Single Refresh. Click
Continuous Refresh to resume normal operation.
8. Experiment with the Binary Sequence Generator by changing the value of n
and the Bit Rate. Adjust the Time Base on the Oscilloscope as necessary.
Tip:
In order for the Oscilloscope to trigger properly, the Time Base must be set so
that at least one complete period of the Trigger Source signal is displayed on
the screen.
9. Show the Logic Analyzer (click
Logic Analyzer).
Quadrature Amplitude Modulation (QAM/DQAM)
in the toolbar or choose Instruments f
17
Exercise 1 – QAM Modulation  Procedure
Click
in the Logic Analyzer toolbar to record data. Figure 10 shows an
example of settings and what you should observe. Compare the signals as
displayed on the Logic Analyzer with the same signals as displayed on the
Oscilloscope.
Generator Settings:
Generation Mode.......... Pseudo-Random
n ..............................................................4
Bit Rate .....................................2000 bit/s
Logic Analyzer Settings:
Display Width..................................10 ms
Clock Grid ............................ Falling Edge
Source............................................... Ch 1
Source Edge ...................................Rising
Clock Edge .................................... Falling
S1 Data .............................................[ch1]
S2 Data .............................................[ch2]
Figure 10. Clock, sync. and PRBS data on Logic Analyzer.
Note that the signals displayed on the Oscilloscope and on the Logic
Analyzer are very similar. With the Logic Analyzer settings shown in
Figure 10, however, the level changes of the pulses in the Sync. signal (Bit 0)
and in the Data signal (Bit 1) align with the falling edges of the Clock signal.
Logic Analyzer operation
The Logic Analyzer does not display data in real time. Instead, after you click ,
it waits for the trigger and then begins recording data. When its memory is full, it
stops recording and displays the recorded data.
The Source setting determines which signal is used to trigger the recording and
the Source Edge setting determines whether the rising edge or the falling edge
of this signal triggers the recording.
When recording data, the Logic Analyzer samples each channel only once per
clock period. The display shows either a high level (1) or a low level (0) in the
corresponding trace for each sample taken. The Clock Edge setting determines
whether the sampling instants correspond to the rising edges or the falling edges
of the clock signal. (For this reason, the Logic Analyzer cannot display the
precise timing relationship between signals as does the Oscilloscope.)
The following sequence shows how the Logic Analyzer records data:
18
•
The user clicks
•
The Logic Analyzer waits for the selected Source Edge (Rising or Falling) of
the trigger Source signal.
•
The Logic Analyzer takes one sample of each channel at each selected
Clock Edge (Rising or Falling) until 256 samples of each channel have been
recorded. It then updates the display.
or presses F5 or selects View f Record.
Quadrature Amplitude Modulation (QAM/DQAM)
Exercise 1 – QAM Modulation  Procedure
The Oscilloscope shows that the transitions in the DATA INPUT signal occur on
the rising edges of the clock signal. Therefore it is preferable to set Clock Edge to
Falling as this ensures that the signal will be sampled in the middle of each bit,
where the signal voltage is not changing. (Setting Clock Edge to Rising would
cause the Logic Analyzer to sample the DATA INPUT signal exactly where the
transitions occur, which could result in ambiguous values.)
To observe the output of a functional block that is falling-edge triggered, as
indicated by the symbol
at the clock input, it is preferable to set Clock Edge
to Rising.
10. Show the Spectrum Analyzer (click
in the toolbar or choose
Instruments f Spectrum Analyzer). Figure 11 shows an example of settings
and what you should observe. In the Generator Settings, vary the value of n
and the Bit Rate and observe the effect on the spectrum.
Tip:
To reduce fluctuations in the displayed spectrum, set Averaging to the number
of consecutive spectra to be averaged. The higher the setting, the lower the
fluctuations, however, the spectrum will take longer to stabilize after a change.
Generator Settings:
Generation Mode.......... Pseudo-Random
n ..............................................................3
Bit Rate .....................................5000 bit/s
Spectrum Analyzer Settings:
Maximum Input .............................10 dBV
Scale Type.............................Logarithmic
Scale ....................................... 10 dBV/div
Averaging................................................4
Frequency Span ........................2 kHz/div
Reference Frequency .............................0
Cursors .........................................Vertical
Figure 11. Spectrum of a PRBS.
Tip:
Theoretically, the spectral
lines have an infinitesimal
width. On a spectrum analyzer, however, they appear
as bars or peaks. If the
spectral lines are very close
together, they are not resolved by the Spectrum
Analyzer and the spectrum
appears to be continuous.
Use a vertical cursor, as shown in the figure, to determine the approximate
frequency of various spectral elements. You can position each cursor by
dragging it with the mouse.
Note that the spectrum of a PRBS consists of a series of lobes of decreasing
magnitude with nulls at multiples of the Bit Rate Rb. This makes the first-null
bandwidth equal to the bit rate.
Since the data signal is not truly random but consists of a sequence that
repeats every L = 2n-1 bits, the spectrum is not continuous. Instead, it
consists of spectral “lines” spaced at frequencies that are multiples of
R
1
= n b where T is the period of the sequence in seconds.
T
2 −1
Quadrature Amplitude Modulation (QAM/DQAM)
19
Exercise 1 – QAM Modulation  Procedure
11. In the generator Settings, set the Generation Mode to User Entry. Enter
different binary sequences in the Binary Sequence setting and observe the
result using the virtual instruments.
Tip:
When the Generation Mode is set to User Entry, the Binary Sequence
Generator generates a repeating binary sequence defined by the Binary
Sequence setting. You can enter up to 32 binary digits (1s and 0s) in this
setting. You can include spaces in this setting to make the pattern more legible
(the software ignores spaces in this setting).
The Serial to Parallel Converter
12. Make the following Generator settings:
Generation Mode........................User Entry
Binary Sequence ........................1001 1000 1110 1110
Bit Rate.......................................1000 bit/s
The Serial to Parallel Converter groups the input data stream into quadbits
and sends the first dibit of each quadbit to the I Channel of the modulator and
the other dibit to the Q Channel of the modulator. Since the Serial to Parallel
Converter is not synchronized with the data, the grouping into quadbits can
start at any bit. Because the number is bits in the Binary Sequence is a
multiple of 4, there are four possible conditions:
A) The grouping starts with the first bit of the defined Binary Sequence,
giving quadbits 1001 1000 1110 1110, as they appear in the Binary
Sequence setting.
B) The grouping starts with the second bit of the sequence.
C) The grouping starts with the third bit of the sequence.
D) The grouping starts with the fourth bit of the sequence.
Note: If the grouping starts with any other bit, the result is equivalent to one of the
above conditions, since the sequence repeats indefinitely.
The first row of Table 4 shows the data bits from this Binary Sequence. After
16 bits, the sequence begins to repeat. A, B, C, and D in the table represent
the four ways the data bits can be grouped into quadbits.
Complete the four Quadbit rows of this table, grouping the data bits into
quadbits in four different ways.
20
Quadrature Amplitude Modulation (QAM/DQAM)
Exercise 1 – QAM Modulation  Procedure
Table 4. Serial to Parallel Converter inputs and outputs.
Data Bits
A
B
C
D
Quadbit
1
0
0
1
1
0
0
1
Hex
Quadbit
1
0
0
0
1
1
1
0
1
1
1
0
1
0
0
9
0
0
Hex
1
1
3
Quadbit
Hex
Quadbit
Hex
Represent each of the quadbits in Table 4 as a hexadecimal Logic Analyzer
symbol where, if the four digits of the quadbit are (b3, b2, b1, b0), the symbol
value is equal to 2 3 × b3 + 2 2 × b2 + 2 × b1 + b0. This will help in interpreting the
symbols displayed by the Logic Analyzer.
Logic Analyzer symbols are
hexadecimal values derived
from combinations of binary
data in selected channels.
They should not be confused
with the symbols used in
M-aray signaling.
In this manual, the channel
selections for each Logic
Analyzer symbol, and the
hexadecimal symbol values,
are shown in square brackets.
Channels and symbols
The Logic Analyzer display includes a Clock channel, eight data channels
Ch 1 to Ch 8, each of which displays the sampled binary data (1s and 0s)
from one probe, as well as two “symbol” channels S1 and S2. Each of these
symbol channels displays a series of hexadecimal numbers that result from
combining the binary data from selected data channels.
The data channels that contribute to each symbol channel are selected using
the Symbol buttons near the bottom of the screen. By default, all Symbol
buttons are up (no channels are selected). Each selected channel
contributes one bit to the hexadecimal symbol value; the most significant bit
(MSB) corresponding to the leftmost pressed-down button and the least
significant bit (LSB) corresponding to the rightmost pressed-down button.
For example, if channels [ch1, ch3, ch6, ch7] are selected for Symbol 1, the
hexadecimal values displayed in the S1 channel correspond to 23 × Ch 1 +
22 × Ch 3 + 21 × Ch 6 + 20 × Ch 7. In this case, since four data channels are
combined into one symbol, the symbol values can range from [0] to [F]
(00002 to 11112). If only two data channels are combined into one symbol,
the symbol values can range from [0] to [3] (002 to 112).
13. Connect the Logic Analyzer probes as follows:
Note: Connect the probes exactly as shown so that the Logic Analyzer will display
the symbols as shown in Table 4.
Quadrature Amplitude Modulation (QAM/DQAM)
21
Exercise 1 – QAM Modulation  Procedure
Logic Analyzer Probe
Connect to
Signal
C
TP2
CLOCK INPUT
1
TP3
BSG SYNC. OUTPUT
2
TP4
Serial to Parallel Converter input
3
TP6
Serial to Parallel Converter output (MSB)
4
TP7
Serial to Parallel Converter output
5
TP8
Serial to Parallel Converter output
6
TP9
Serial to Parallel Converter output (LSB)
Tip:
To make it easier to connect the probes, you may wish to zoom into this region
of the diagram. To zoom in a diagram, right-click on the diagram and choose
Zoom in the context-sensitive menu. This changes the mouse pointer to
.
Drag the mouse pointer up or down to zoom in or out. Another way to zoom is
to click the diagram and roll the mouse wheel.
14. Record data with the Logic Analyzer and examine the data. Using the
Symbol buttons, set Symbol 1 to [ch2] and Symbol 2 to [ch3, ch4, ch5, ch6].
Examine the data displayed by the Logic Analyzer. Figure 12 to Figure 15
show the four possible conditions, depending on how the Serial to Parallel
Converter groups the data sequence into quadbits.
Click the Drop 1 Bit button once only in the modulator and perform another
recording. Ch 2 and S1, the input data, will not change but the results in Ch 3
to Ch 6 and S2 should be different.
For each of Figure 12 to Figure 15, identify which of the four possible
conditions (A, B, C, or D) from Table 4 the figure represents.
Note: Because the Serial to Parallel Converter operates on four bits at a time, it
introduces a slight delay in the output bit streams. The timing relationship
changes slightly after clicking Drop 1 Bit.
Logic Analyzer Settings:
Display Width..................................38 ms
Clock Grid ............................ Falling Edge
Source............................................... Ch 1
Source Edge ...................................Rising
Clock Edge .................................... Falling
S1 Data .............................................[ch2]
S2 Data ..................... [ch3, ch4, ch5, ch6]
Figure 12. Serial to Parallel Converter input (Ch 2) and outputs (Ch 3 to Ch 6).
22
Quadrature Amplitude Modulation (QAM/DQAM)
Exercise 1 – QAM Modulation  Procedure
Figure 12 represents Condition:
…A
…B
…C
…D
Figure 13. Serial to Parallel Converter input (Ch 2) and outputs (Ch 3 to Ch 6).
Figure 13 represents Condition:
…A
…B
…C
…D
Figure 14. Serial to Parallel Converter input (Ch 2) and outputs (Ch 3 to Ch 6).
Figure 14 represents Condition:
Quadrature Amplitude Modulation (QAM/DQAM)
…A
…B
…C
…D
23
Exercise 1 – QAM Modulation  Procedure
.
Figure 15. Serial to Parallel Converter input (Ch 2) and outputs (Ch 3 to Ch 6).
Figure 15 represents Condition:
…A
…B
…C
…D
15. Use the oscilloscope to determine the exact timing relationship of the
different signals. Since this requires observing several signals at a time, it will
be helpful to use the memory of the Oscilloscope.
Tip:
Click M1 or M2 in the instrument toolbar to store the current display in
Memory 1 or Memory 2. Use the Memories setting to show the contents of
Memory 1, Memory 2, or both.
Is the output of the Serial to Parallel Converter triggered by the rising edge or
the falling edge of the clock signal? Does this correspond to the symbol used
at the clock input of the Serial to Parallel Converter?
D/A Converter
16. Connect the probes as follows:
24
Oscilloscope Probe
Connect to
Signal
E
TP10
I-channel D/A Converter input (MSB)
1
TP11
I-channel D/A Converter input (LSB)
2
TP14
I-channel D/A Converter output
Quadrature Amplitude Modulation (QAM/DQAM)
Exercise 1 – QAM Modulation  Procedure
Logic Analyzer Probe
Connect to
Signal
C
TP2
CLOCK INPUT
E
TP5
Frequency Divider output
1
TP6
Serial to Parallel Converter output (MSB)
2
TP7
Serial to Parallel Converter output
3
TP8
Serial to Parallel Converter output
4
TP9
Serial to Parallel Converter output (LSB)
Tip:
To disconnect a probe and return it to the Probes bar, you can right-click the
probe and choose Disconnect Probe in the context-sensitive menu.
Alternatively, you can double-click the probe’s place holder in the Probes bar.
Note: The Frequency Divider divides the BSG SYNC. signal frequency in order to
generate a signal that can be used as a trigger for the Oscilloscope or the
Logic Analyzer. This is necessary when observing the Serial to Parallel
Converter output with a binary sequence having an odd number of bits. (All
pseudo-random sequences have an odd number of bits.)
Make the following Generator settings:
Generation Mode........................User Entry
Binary Sequence ........................0000 0100 1100 1000
Bit Rate.......................................2000 bit/s
Record data on the Logic Analyzer and observe the signal states. Set
Symbol 1 to [ch1, ch2] and Symbol 2 to [ch3, ch4].
The outputs of the Serial to Parallel Converter should be as shown in
Figure 16, with Ch 1, Ch 2 and S1 changing state and Ch 3, Ch 4 and S2
always zero. This means that the first dibit in each quadbit of the defined
Binary Sequence is sent to the I-channel of the modulator, and the second
dibit (always 00) is sent to the Q-channel. If necessary, click the Drop 1 Bit
button and observe the signals again until the signals are as shown in
Figure 16.
Logic Analyzer Settings:
Display Width..................................20 ms
Clock Grid ............................ Falling Edge
Source................................................. Ext
Source Edge ...................................Rising
Clock Edge .................................... Falling
S1 Data .....................................[ch1, ch2]
S2 Data .....................................[ch3, ch4]
TP6
TP7
TP8
TP9
Figure 16. Desired Serial to Parallel Converter outputs.
Quadrature Amplitude Modulation (QAM/DQAM)
25
Exercise 1 – QAM Modulation  Procedure
Observe the D/A Converter inputs and output on the Oscilloscope. Figure 17
shows an example of what you should see.
Oscilloscope Settings:
Channel 1.......................................5 V/div
Channel 2.......................................2 V/div
Channel E ......................................5 V/div
Time Base................................... 2 ms/div
Trigger: Slope .................................Rising
Trigger: Level...................................... 0 V
Trigger: Source ................................. Ch 2
TP10
TP11
TP14
Figure 17. D/A Converter input and output signals.
You may wish to change the
Channel 2 Scale setting to
increase the precision of the
measurements.
Use the cursors on the Oscilloscope to determine the different D/A Converter
output voltage levels (TP14) for the different input states and enter these into
Table 5. Divide each output level by the minimum positive output level to
obtain the relative levels.
Tip:
When the horizontal cursors are active, the voltage levels corresponding to the
position of each cursor with respect to the Ch 1 and Ch 2 ground levels (as well
as the voltage difference between the two cursors) is shown in the data below
the display.
When the vertical cursors are active, the time position of each cursor (as well
as the time difference between the two cursors) is shown in the data below the
display. The voltage levels shown correspond to the levels at the intersections
of the Ch 1 and Ch 2 traces with each cursor.
Table 5. D/A Converter input states and output levels.
Input Dibit
(TP10, TP11)
Output Level (V)
Relative Level
00
01
11
10
Explain the operation of the D/A Converter.
26
Quadrature Amplitude Modulation (QAM/DQAM)
Exercise 1 – QAM Modulation  Procedure
What determines the sign and the amplitude of the D/A Converter output?
The Filters and mixers
17. Connect the Oscilloscope probes as follows.
Oscilloscope Probe
Connect to
Signal
1
TP16
I-channel mixer input
E
TP17
I-channel carrier
2
TP20
I-channel mixer output
Turn the Low-Pass Filters Off. Figure 18 shows an example of what you may
observe. Then turn the Low-Pass Filters On (see Figure 19).
QAM Settings:
Carrier Frequency....................... 2000 Hz
Low-Pass Filters ..................................Off
Oscilloscope Settings:
Channel 1.......................................2 V/div
Channel 2.......................................1 V/div
Channel E ......................................1 V/div
Time Base................................... 1 ms/div
Trigger: Slope .................................Rising
Trigger: Level...................................... 0 V
Trigger: Source ................................. Ch 1
Figure 18. I-channel carrier, four-level data and mixer output signal (Low-Pass Filters Off).
Quadrature Amplitude Modulation (QAM/DQAM)
27
Exercise 1 – QAM Modulation  Procedure
QAM Settings:
Carrier Frequency....................... 2000 Hz
Low-Pass Filters ..................................On
Oscilloscope Settings:
Channel 1.......................................2 V/div
Channel 2.......................................1 V/div
Channel E ......................................1 V/div
Time Base................................... 1 ms/div
Trigger: Slope .................................Rising
Trigger: Level...................................... 0 V
Trigger: Source ................................. Ch 1
Figure 19. I-channel carrier, four-level data and mixer output signal (Low-Pass Filters On).
Describe the relationship between the amplitude and polarity of the four-level
analog data signal and the amplitude and phase of the mixer output signal.
What is the effect of the low-pass filter on the four-level data signal and on
the mixer output signal? What is the advantage of filtering the data signal
before modulation?
18. Use the oscilloscope to observe the I- and Q-channel carrier signals. How
are these signals related?
19. Use the Spectrum Analyzer to observe the frequency spectrum of the carrier,
the baseband four-level data signal, and the mixer output signal (see
Figure 20). Explain the relationship between the frequency spectra of these
signals.
Tip:
28
Click M1 or M2 in the instrument toolbar to store the current display in
Memory 1 or Memory 2. Use the Memories setting to show the contents of
Memory 1, Memory 2, or both.
Quadrature Amplitude Modulation (QAM/DQAM)
Exercise 1 – QAM Modulation  Procedure
QAM Settings:
Carrier Frequency.................... 10 000 Hz
Low-Pass Filters ..................................On
Generator Settings:
Generation Mode.......... Pseudo-Random
n ..............................................................7
Bit Rate .....................................5000 bit/s
Spectrum Analyzer Settings:
Maximum Input .............................20 dBV
Scale Type.............................Logarithmic
Scale ....................................... 10 dBV/div
Averaging..............................................16
Frequency Span ........................2 kHz/div
Reference Frequency ..................... 0 kHz
Memories .......................................... Both
Figure 20. Frequency spectrum of four-level data signal, carrier and mixer output signal.
The summer
20. Use the Oscilloscope to observe the signals at the input and output of the
summer (TP20, TP21, and TP22). Figure 21 shows an example.
As an option, use a conventional oscilloscope to observe the signal at the
QAM Modulator OUTPUT (refer to the RTM Connections tab of the
software).
QAM Settings:
Carrier Frequency....................... 2000 Hz
Low-Pass Filters ..................................On
TP20
Generator Settings:
Generation Mode.......... Pseudo-Random
n ..............................................................5
Bit Rate .....................................2000 bit/s
Oscilloscope Settings:
Channel 1.......................................1 V/div
Channel 2.......................................1 V/div
Channel E ......................................1 V/div
Time Base................................... 2 ms/div
(Single Refresh)
TP21
TP22
Figure 21. Summer input and output (QAM) signals.
Quadrature Amplitude Modulation (QAM/DQAM)
29
Exercise 1 – QAM Modulation  Procedure
Describe the operation of the summer.
21. Use the Spectrum Analyzer to observe the spectrum of the QAM signal and
compare this with the spectrum of the DATA INPUT signal (see Figure 22).
Tip:
To reduce fluctuations in the displayed spectrum, set Averaging to the number
of consecutive spectra to be averaged. The higher the setting, the lower the
fluctuations, however, the spectrum will take longer to stabilize after a change.
QAM Settings:
Carrier Frequency.................... 10 000 Hz
Low-Pass Filters ..................................On
Generator Settings:
Bit Rate .....................................4000 bit/s
Spectrum Analyzer Settings:
Maximum Input .............................20 dBV
Scale Type.............................Logarithmic
Scale ....................................... 10 dBV/div
Averaging..............................................16
Frequency Span ........................2 kHz/div
Reference Frequency ..................... 0 kHz
Figure 22. Four-level (baseband) signal and QAM signal spectrum.
In Figure 22, identify the features that correspond to the bit rate and the
symbol rate. Express the bandwidth of the QAM signal in terms of the bit rate
and the symbol rate.
Explain why QAM is considered to be a bandwidth efficient modulation
technique.
30
Quadrature Amplitude Modulation (QAM/DQAM)
Exercise 1 – QAM Modulation  Procedure
Signal constellations
22. Connect the Oscilloscope Probes as follows:
Oscilloscope Probe
Test point
Signal
1
TP14
I-channel D/A Converter output
2
TP15
Q-channel D/A Converter output
E
TP5
Frequency Divider output
As an option, connect a conventional oscilloscope to the QAM Demodulator
I-CHANNEL OUTPUT and QAM Demodulator Q-CHANNEL OUTPUT (refer
to the RTM Connections tab of the software). Use the conventional
oscilloscope in the X-Y mode to observe the constellation. (The Low-Pass
filters in the QAM Modulator must be set to On.)
Make the following Generator settings:
Generation Mode........................Pseudo-Random
n..................................................3
Bit Rate.......................................3000 bit/s
Figure 23 shows and example of what you should observe. The Oscilloscope
will display the I- and Q-channel D/A Converter output signals. Each of these
signals is a four-level analog signal that is used, after low-pass filtering, to
modulate one of the sinusoidal carriers.
Oscilloscope Settings:
Channel 1.......................................2 V/div
Channel 2.......................................2 V/div
Time Base................................... 2 ms/div
Trigger Slope ..................................Rising
Trigger Level....................................... 1 V
Trigger Source .................................... Ext
Figure 23. I- and Q-channel D/A Converter output signals.
23. Without moving the Oscilloscope probes, put the Oscilloscope in the X-Y
mode. Figure 24 shows an example of what you should observe.
Quadrature Amplitude Modulation (QAM/DQAM)
31
Exercise 1 – QAM Modulation  Procedure
Oscilloscope Settings:
Channel 1 (X).................................1 V/div
Channel 2 (Y).................................1 V/div
Display Mode .................................... Dots
X-Y .......................................................On
Sampling Window.........................100 ms
Figure 24. QAM constellation (7 points shown).
Tip:
The Sampling Window setting determines the time during which the signals
are sampled before each update of the display. In the present case, this
should be 100 ms or greater so that all quadbits being generated appear each
time the display is updated.
The Oscilloscope now displays a number of points in the signal constellation.
What does each point in the constellation represent?
With 16-QAM, the constellation should normally have 16 points. Why are
only 7 points displayed?
24. In the Generator Settings, set n to different values (2, 4, and 5, etc.) and
observe the displayed constellation. What do you observe?
32
Quadrature Amplitude Modulation (QAM/DQAM)
Exercise 1 – QAM Modulation  Procedure
25. Connect the Logic Analyzer probes as follows:
Logic Analyzer Probe
Connect to
Signal
C
TP2
CLOCK INPUT
1
TP3
BSG SYNC. OUTPUT
2
TP4
Serial to Parallel Converter input
3
TP6
Serial to Parallel converter output (MSB)
4
TP7
Serial to Parallel converter output
5
TP8
Serial to Parallel converter output
6
TP9
Serial to Parallel converter output (LSB)
26. Set the Generation Mode to User-Entry. Set the Binary Sequence to the fourbit sequence (quadbit) 0000. Record data using the Logic Analyzer.
Configure Symbol 2 of the Logic Analyzer to display the hexadecimal value
of the quadbit, as shown in Figure 25.
Logic Analyzer Settings:
Display Width..................................10 ms
Clock Grid ............................ Falling Edge
Source............................................... Ch 1
Source Edge ...................................Rising
Clock Edge .................................... Falling
S1 Data .............................................[ch2]
S2 Data ..................... [ch3, ch4, ch5, ch6]
Figure 25. Logic Analyzer showing the quadbit 0000 in Ch 3 to Ch 6 and in S2.
With any four-bit Binary
Sequence, the stream of
quadbits at the output of the
Serial to Parallel Converter is
uniform over time – each
quadbit is identical to the
previous quadbit.
Observe the Oscilloscope display. Figure 26 shows the constellation point
corresponding to the quadbit 0000. Note in Figure 27 that this constellation
point has been identified with the quadbit it represents as well as the
hexadecimal value of the quadbit in square brackets.
Quadrature Amplitude Modulation (QAM/DQAM)
33
Exercise 1 – QAM Modulation  Procedure
Figure 26. Oscilloscope showing the constellation point for the quadbit 0000.
L SD s :
____
[ ]
____
[ ]
____
[ ]
____
[ ]
__
____
[ ]
____
[ ]
_,0
_,0
0
____
[ ]
__
____
[ ]
____
[ ]
____
[ ]
____
[ ]
__
____
[ ]
____
[ ]
____
[ ]
____
[ ]
__
__
__
__
M SD s : _ _
Figure 27. Quadbits [and HEX values] in the QAM constellation.
27. Set the Binary Sequence to 1111 and repeat the previous step. You have
now identified two of the 16 points in the constellation. In the following steps,
you will identify the remaining points.
34
Quadrature Amplitude Modulation (QAM/DQAM)
Exercise 1 – QAM Modulation  Procedure
Identifying constellation points
Identifying the constellation points that are mapped to 0000 and 1111 is
straightforward because with each of these Binary Sequences, the four outputs
of the Serial to Parallel Converter are identical. The bit at which the Serial to
Parallel Converter begins to divide the DATA INPUT stream makes no
difference.
With all other four-bit Binary Sequences, however, the bit at which the Serial to
Parallel Converter begins does make a difference. For example, setting the
Binary Sequence to 0001 will produce a uniform stream of one of the following
quadbits: 0001, 0010, 0100, or 1000. There is no way to predict beforehand
which of these quadbits you will obtain. Clicking the Drop 1 Bit button allows you
to change the quadbit produced.
In the following steps, for each four-bit Binary Sequence you enter, you will use
the Logic Analyzer to observe which quadbit is present at the output of the Serial
to Parallel converter, and observe which constellation point is displayed on the
Oscilloscope. Then you will use the Drop 1 Bit button to obtain all possible
quadbit from that Binary Sequence.
28. Set the Binary Sequence to 0001. Record data on the Logic Analyzer and
note which quadbit is present at the outputs of the Serial to Parallel
Converter. Since TP6 represents the MSB, a 0 at TP6, TP7 and TP8 and a 1
at TP9 represents the quadbit 0001. Clicking the Drop 1 Bit button will
change this quadbit to 0010.
Click the Drop 1 Bit button several times, each time observing the quadbit
using the Logic Analyzer and observing the constellation point displayed on
the Oscilloscope. Then write in Figure 27 the quadbits that correspond to
these four constellation points.
By using different four-bit Binary Sequences and the Drop 1 Bit button, and
by using the Logic Analyzer and the Oscilloscope, complete Figure 27 to
show all 16 quadbits. Enter the hexadecimal value of each quadbit between
the square brackets.
Each quadbit consists of two dibits – the most significant dibit (MSD) and the
least significant dibit (LSD). Below the horizontal axis of Figure 27, write the
MSDs that correspond to each of the columns. To the right of the vertical
axis, write the LSDs that correspond to each of the rows.
Note the order of the MSDs and the LSDs. Are they arranged consecutively?
The smallest distance between neighboring constellation points is the
horizontal or vertical distance between consecutive points. Constellation
points separated by this distance are considered to be adjacent. (The oblique
distance between any two points is greater than this distance.) Note how the
bits values of the quadbits change as you move from one point to any
adjacent point.
Quadrature Amplitude Modulation (QAM/DQAM)
35
Exercise 1 – QAM Modulation  Conclusion
Name the type of coding that is used here and explain the advantage of
encoding the constellation points in this manner.
29. Enter the three-bit Binary Sequence 111 and observe the constellation.
Change the binary Sequence to 101. Click the Drop 1 bit button several
times and observe what happens.
Explain why this 3-bit sequence produces three constellation points, each of
which represents four bits and why the drop 1 bit button seems to have no
effect.
30. When you have finished using the system, exit the LVCT software and turn
off the equipment.
CONCLUSION
In this exercise, you became familiar with the LVCT software and studied the
operation of the basic functional blocks of the QAM modulator. You observed that
the Serial to Parallel Converter groups the input data stream into quadbits that
are processed by two parallel channels, I and Q, and that the starting point of this
grouping is arbitrary. You saw how the A/D Converters and the mixers generate
two bi-phase, bi-level signals using two carriers in phase quadrature. You
observed that summing these two signals produces the QAM signal. You also
observed the signal constellations on the oscilloscope for various binary
sequences.
REVIEW QUESTIONS
1. Explain what is meant by bandwidth efficiency.
2. How does the bandwidth efficiency of QAM compare to that of other
modulation techniques?
36
Quadrature Amplitude Modulation (QAM/DQAM)
Exercise 1 – QAM Modulation  Review Questions
3. What does a constellation diagram represent?
4. What is the role of the mixers in the QAM modulator?
5. How are the signals at the outputs of the mixers combined to produce the
QAM signal?
Quadrature Amplitude Modulation (QAM/DQAM)
37
Sample Exercise
Extracted from
Asymmetric Digital Subscriber Line
(ADSL)
Exercise
1
ADSL Signal Spectral Analysis
EXERCISE OBJECTIVE
When you have completed this exercise, you will be familiar with the distribution
of the subcarriers used in ADSL. You will be able to analyze the ADSL signal
frequency spectrum and identify each subcarrier in this signal. You will also be
familiar with the Lab-Volt Communications Technologies (LVCT) software, the
Lab-Volt ADSL application, and the Spectrum Analyzer used in this application.
DISCUSSION OUTLINE
The Discussion of this Exercise covers the following points:
ƒ
ƒ
ƒ
ƒ
ADSL Subcarrier Distribution
ADSL Maximum Data Transmission Rates
Quadrature Amplitude Modulation of the Subcarriers
The Lab-Volt ADSL Application
DISCUSSION
ADSL Subcarrier Distribution
The subcarriers in ADSL
are also referred to as
tones. Both terms can be
used interchangeably.
As mentioned in the Introduction of this manual, ADSL can be viewed, in the
upstream and downstream directions of transmission, as a number of QAM
modulators operating simultaneously at different frequencies spread across the
available bandwidth of the telephone line. Figure 8 shows the distribution of the
subcarriers used in ADSL. The subcarriers are numbered 0 to 255 and the
frequency separation between each subcarrier is 4.3125 kHz. The frequency of
each subcarrier can be determined by multiplying the subcarrier number by
4.3125 kHz (e.g., the frequency of subcarrier 10 is 43.125 kHz).
Figure 8. Distribution of the ADSL subcarriers (tones) over the telephone line bandwidth.
Asymmetric Digital Subscriber Line (ADSL)
11
Exercise 1 – ADSL Signal Spectral Analysis  Discussion
When in the training mode,
an ADSL modem determines the quality of the
transmission
medium
(mainly the telephone line
and the POTS splitter), and
sets a number of parameters accordingly.
The pilot tone (tone 16) is
used in the ATU-C Receiver
for clock recovery. The recovered clock must be
properly synchronized with
the
ATU-R
Transmitter
clock to ensure that the
ADSL signal is properly
sampled at the ATU-C Receiver. A similar pilot tone
(tone 64) is transmitted by
the ATU-C for clock recovery at the ATU-R.
Not all subcarriers can be used by ADSL. The frequency band from 0 to 4 kHz is
reserved for POTS, thereby eliminating subcarriers 0 (DC) and 1. In order to limit
mutual interference between POTS and the ADSL service, a certain number of
the subsequent subcarriers (typically subcarriers 2 to 6) are also discarded. The
actual number of subcarriers discarded mainly depends on the characteristics of
the filters used in the POTS splitter, and is determined by the ADSL modem
when it is in the training mode.
Subcarriers 7 to 31 in Figure 8 are allocated to data transmission in the upstream
direction. The transmitter in the ATU-R can apply quadrature amplitude
modulation to each of these subcarriers to transmit data toward the ATU-C.
Notice, however, that subcarrier 16 is left unmodulated because it is reserved to
transmit a 69-kHz pilot tone (16 x 4.3125 kHz = 69 kHz). Subcarriers 32 to 255
are allocated to data transmission in the downstream direction. The transmitter in
the ATU-C can apply quadrature amplitude modulation to each of these
subcarriers to transmit data toward the ATU-R. Notice, however, that
subcarrier 64 is left unmodulated because it is reserved to transmit a 276-kHz
pilot tone (64 x 4.3125 kHz = 276 kHz). This subcarrier distribution scheme
reveals that the number of subcarriers allocated to data transmission in the
downstream direction is much higher than the number of subcarriers allocated to
data transmission in the upstream direction, thereby illustrating the asymmetric
nature of ADSL.
Note that the ADSL subcarrier distribution shown in Figure 8 applies when
frequency-division multiplexing (FDM) is used to separate the upstream and
downstream data transmissions. When echo cancellation is used in the ATU-C
and ATU-R instead of FDM to separate the two directions of transmission, all
subcarriers dedicated to data transmission (subcarriers 7 to 255 except
subcarriers 16 and 64) can be used for downstream data transmission at the
same time as subcarriers 7 to 31 (except subcarrier 16) are used for upstream
data transmission.
ADSL Maximum Data Transmission Rates
In ADSL, the nominal symbol rate is 4 kbaud and a maximum of 15 bit can be
transported by each subcarrier every symbol interval. The maximum theoretical
data rate for the upstream data transmission, according to the subcarrier
distribution shown in Figure 8, is thus equal to 4000 x 15 x 24 = 1.44 Mbit/s.
Similarly, the maximum theoretical data rate for the upstream data transmission,
according to the subcarrier distribution shown in Figure 8, is equal to
4000 x 15 x 223 = 13.38 Mbit/s. However, additional data is required during
transmission to support various functions of ADSL, and the maximum number of
bits that can be transported by each subcarrier every symbol interval is often less
than 15 in actual systems. This decreases the maximum data rates that can be
achieved to the approximate values stated in the introduction of this manual. The
length and imperfections of the telephone line further reduce the maximum data
transmission rates that can actually be achieved.
12
Asymmetric Digital Subscriber Line (ADSL)
Exercise 1 – ADSL Signal Spectral Analysis  Discussion
Quadrature Amplitude Modulation of the Subcarriers
In ADSL, each data frame
contains a certain number
of bytes. The number of bits
per frame is thus an integer
multiple of 8. Furthermore,
all subcarriers are modulated simultaneously, that is,
the symbol rate is the same
for all subcarriers.
In ADSL, the data to be transmitted is organized into frames (the structure of
these frames will be discussed later in this manual). The data contained in each
frame is separated into n groups of bits, n being equal to the number of
subcarriers used. The number of bits in each group may be different. Referring to
the ADSL subcarrier distribution shown in Figure 8, the data would be separated
into 24 groups of bits for the upstream data transmission, and into 223 groups for
the downstream data transmission. Each group of bits is used to apply
quadrature amplitude modulation to a particular subcarrier. A QAM signal is thus
produced at each subcarrier frequency. This process repeats every symbol
interval, that is, the data in the next frame is separated into n groups of bits, and
each group modulates a particular subcarrier. The modulated subcarriers are
then combined together to obtain the ADSL signal. Figure 9 is a simplified block
diagram that illustrates the quadrature amplitude modulation of the subcarriers in
an ATU-R (upstream data transmission). In this figure, the QAM modulator
number corresponds to the subcarrier number. Notice that the number of bits in
each group of bits varies from one QAM modulator to another. This indicates that
certain subcarriers carry more data bits than others.
Figure 9. Quadrature amplitude modulation of the subcarriers in an ATU-R.
The nominal symbol rate in ADSL is 4 kbaud. However, the actual symbol rate,
i.e., the rate at which the subcarriers are modulated, is 4.059 kbaud for reasons
that will be explained later in this manual. For each subcarrier, this results in a
QAM signal whose frequency spectrum has the traditional sin x/x shape, with a
mainlobe that is 8.118 kHz wide. The frequency spectra of adjacent, quadrature
amplitude modulated subcarriers thus overlap severely because the frequency
separation between the subcarriers in ADSL is only 4.3125 kHz, as shown in
Figure 10.
Asymmetric Digital Subscriber Line (ADSL)
13
Exercise 1 – ADSL Signal Spectral Analysis  Discussion
Figure 10. Spectra of adjacent modulated ADSL subcarriers.
One would be tempted to say that this leads to severe interference between
adjacent subcarriers and compromises the viability of the system. However, the
subcarriers used in ADSL are mathematically orthogonal, that is, they are all
integer multiples of the base frequency 4.3125 kHz. Therefore, no inter-carrier
interference (ICI) occurs and demodulation can take place without any problems.
ADSL is in fact an OFDM-based application. You can refer to the introduction of
this manual to learn more about OFDM.
The Lab-Volt ADSL Application
The Lab-Volt ADSL application is designed to be used with the Lab-Volt
Reconfigurable Training Module. The application allows study of ADSL data
transmission in the upstream direction, that is, from the CPE to the local CO. The
application thus consists of the transmitter of an ATU-R and the receiver of an
ATU-C, as shown in Figure 11. Note that data transmission in the other direction
is basically the same except for differences in specifications such as the
maximum data transmission rate, number of subcarriers, number of time-domain
samples per symbol interval, etc.
Figure 11. The Lab-Volt ADSL application allows study of data transmission in the upstream
direction.
14
Asymmetric Digital Subscriber Line (ADSL)
Exercise 1 – ADSL Signal Spectral Analysis  Discussion
The subcarrier distribution
in the Lab-Volt ADSL application is as shown in
Figure 8. Therefore, subcarriers 7 to 31, except subcarrier 16 (pilot tone), can be
used to carry data.
Due to technical constraints, the frequency separation between the subcarriers in
the Lab-Volt ADSL application is 4.439 kHz instead of 4.3125 kHz, as defined in
Recommendation G.992.1
of
the
International
Telecommunication
Union - Telecommunication Standardization Sector (ITU–T). The frequency of
any subcarrier in the ADSL application can therefore be calculated by multiplying
the subcarrier number by 4.439 kHz. Furthermore, the actual symbol rate in the
Lab-Volt ADSL application is 4.178 kbaud instead of 4.059 kbaud as defined in
ITU-T Recommendation G.992.1. Also, the maximum number of bits that can
modulate a subcarrier is 8 instead of 15 as stated in ITU-T Recommendation
G.992.1. These minor deviations from ITU-T Recommendation G.992.1 have no
significant impacts on the principles studied.
The transmitter in the ATU-R of the ADSL application does not include the
interface with the customer’s data terminal equipment (generally a personal
computer). Instead, a data table included in the transmitter of the ATU-R in the
Lab-Volt ADSL application provides the data to be transmitted (see Figure 12).
Similarly, the receiver in the ATU-C does not include the interface with the CO’s
broadband data switching equipment. Instead, the recovered data is simply made
available in a table included in the receiver of the ATU-C in the Lab-Volt ADSL
application (see Figure 13). These interfacing aspects of ADSL are not covered
in this manual.
Figure 12. Tx Data table in the ATU-R Transmitter.
Asymmetric Digital Subscriber Line (ADSL)
15
Exercise 1 – ADSL Signal Spectral Analysis  Procedure Outline
Figure 13. Rx Data table in the ATU-C Receiver.
PROCEDURE OUTLINE
The Procedure is divided into the following sections:
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
ƒ
PROCEDURE
Equipment Setup and Connections
The Pilot Tone
QAM Applied to a Tone
Subcarrier Mainlobe Bandwidth and Actual Symbol Rate
Subcarrier Separation
Subcarrier Separation versus Subcarrier Mainlobe Bandwidth
ADSL Signal Frequency Spectrum
Equipment Setup and Connections
1. Turn on the RTM Power Supply and the RTM and make sure the RTM power
LED is lit.
2. Turn on the host computer. Make sure that the system has been installed
and configured as described in the Communications Technologies Training
System User Guide.
3.
Start the LVCT software (choose Start f All Programs f Lab-Volt f LVCT).
Tip:
If the software is already running, click Exit in the File menu and then restart
the LVCT software to begin a new session.
In the Application Selection dialog box, choose ADSL and click OK. This
begins a new session with all settings set to their default values and with all
16
Asymmetric Digital Subscriber Line (ADSL)
Exercise 1 – ADSL Signal Spectral Analysis  Procedure
faults deactivated. The System Diagram appears showing the ATU-R
Transmitter and the ATU-C Receiver.
Figure 14. Clicking the Default button in the System Diagram displays the default external
connections to be made.
4. Make the Default external connections shown on the System Diagram tab of
the ADSL application. For details of connections to the Reconfigurable
Training Module, refer to the RTM Connections tab of the software.
Tip:
Click the Default button in the System Diagram to show the default external
connections.
On-line help is accessible from the Help menu of the software and the Help
menu of each instrument.
You can print out the screen of any instrument by choosing File f Print in that
instrument.
The Pilot Tone
5. Display the block diagram of the ATU-R Transmitter by clicking the
corresponding tab in the ADSL application.
Tip:
To display the block diagram of the ATU-R Transmitter or ATU-C Receiver,
you can also place the mouse pointer over the corresponding block in the
System Diagram and double click the left mouse button.
6. Locate the Bit/Tone Table in the ATU-R Transmitter block diagram using the
Pan and Zoom commands. These commands are available in the View menu
as well as buttons in the ADSL application toolbar.
Asymmetric Digital Subscriber Line (ADSL)
17
Exercise 1 – ADSL Signal Spectral Analysis  Procedure
Tip:
To pan a diagram, you can also right-click on the
diagram and choose Pan / Select in the contextsensitive menu. Drag the mouse pointer to pan the
diagram.
Tip:
To zoom in a diagram, you can also right-click on
the diagram and choose Zoom in the contextsensitive menu. Drag the mouse pointer up or down
to zoom in or out. Another way to zoom is to click
the diagram and roll the mouse wheel.
Click the Edit button in the Bit/Tone Table. This opens the Bit/Tone Table
window. This window allows you to change the number of bits allocated to
each tone, i.e., the number of bits which a tone carries.
Set the number of bits allocated to all tones to zero by entering 0 in the data
field next to the Apply to All Tones button, click this button, and click the
Apply button located at the bottom of the Bit/Tone Table window.
7. Click the Probes bar button (
) in the ADSL application toolbar. This
displays the Probes bar. This bar contains the probes of the Oscilloscope,
Spectrum Analyzer, and True RMS Voltmeter included in the ADSL
application.
Figure 15. The Probes bar contains the probes of the various instruments included in the
ADSL application.
Connect the Spectrum Analyzer probe to TP1 of the ATU-R Transmitter
(ADSL output signal).
Tip:
18
To move a probe from the Probes
bar to a test point, click the probe
and release the mouse button.
Then move the mouse until the tip
of the probe is over the test point
and click the mouse button to
connect the probe.
Asymmetric Digital Subscriber Line (ADSL)
Exercise 1 – ADSL Signal Spectral Analysis  Procedure
Tip:
To move a probe from one test
point to another, move the mouse
pointer over the probe until the
pointer changes into a grasping
. Then click the probe and
hand
without releasing the mouse
button, drag the probe to another
test point and then release the
mouse button.
) in the ADSL application toolbar to
8. Click the Spectrum Analyzer button (
display the Spectrum Analyzer. Make the settings required on the Spectrum
Analyzer to observe the ADSL signal frequency spectrum. Figure 16 shows
an example of what you should observe on the Spectrum Analyzer.
Note: The noise floor of the ADSL signal frequency spectrum may fluctuate
considerably at a slow rate. Ignore this phenomenon.
Spectrum Analyzer Settings:
Maximum Input ............................... 10 dB
Scale Type.........................................Log.
Scale ....................................... 10 dBV/div
Averaging................................................4
Frequency Span ......................20 kHz/div
Reference Frequency ....................... 0 Hz
Figure 16. ADSL output signal frequency spectrum when the number of bits allocated to all
tones is set to zero.
9. Measure the frequency of the single spectral component in the ADSL signal
spectrum.
Tip:
To accurately measure the frequency of a spectral component, align one of the
vertical cursors of the Spectrum Analyzer with the spectral component of
interest and read the frequency of the corresponding cursor (it is indicated at
the bottom of the Spectrum Analyzer display).
Spectral Component Frequency: ___________ kHz
Asymmetric Digital Subscriber Line (ADSL)
19
Exercise 1 – ADSL Signal Spectral Analysis  Procedure
What does this spectral component represent? Briefly explain why this
component is a single line in the ADSL signal frequency spectrum.
QAM Applied to a Tone
10. In the Bit/Tone Table window, set the number of bits allocated to tone 7 to 8
by entering 8 in the row labeled Tone 7.
Click the Apply button at the bottom of the Bit/Tone Table window while
observing the Spectrum Analyzer display. Notice that new spectral
components having a sin x/x shape appear in the ADSL signal frequency
spectrum, as shown in Figure 17.
Spectrum Analyzer Settings:
Maximum Input ............................... 10 dB
Scale Type.........................................Log.
Scale ....................................... 10 dBV/div
Averaging................................................4
Frequency Span ......................20 kHz/div
Reference Frequency ....................... 0 Hz
Figure 17. ADSL output signal frequency spectrum when data bits are allocated to tone 7 only.
11. Measure the frequency at which these spectral components are centered.
Spectral Component Center Frequency: ____________ kHz
20
Asymmetric Digital Subscriber Line (ADSL)
Exercise 1 – ADSL Signal Spectral Analysis  Procedure
What do these spectral components represent, and why do they have a
sin x/x shape?
Subcarrier Mainlobe Bandwidth and Actual Symbol Rate
12. Use the vertical cursors of the Spectrum Analyzer to measure the mainlobe
bandwidth of the new frequency components that appeared in the ADSL
signal spectrum.
Tip:
Set the frequency span of the Spectrum Analyzer to 10 kHz/div while
measuring the mainlobe bandwidth. This improves the measuring accuracy.
Mainlobe Bandwidth: ______________ kHz
From the above measurement, determine the actual symbol rate used in the
ADSL application.
Subcarrier Separation
13. In the Bit/Tone Table window, set the number of bits allocated to tone 13 to 8
by entering 8 in the row labeled Tone 13.
14. Click the Apply button at the bottom of the Bit/Tone Table window while
observing the Spectrum Analyzer display. Notice that other spectral
components, also having a sin x/x shape, appear in the ADSL signal
frequency spectrum, as shown in Figure 18.
Asymmetric Digital Subscriber Line (ADSL)
21
Exercise 1 – ADSL Signal Spectral Analysis  Procedure
Spectrum Analyzer Settings:
Maximum Input ............................... 10 dB
Scale Type.........................................Log.
Scale ....................................... 10 dBV/div
Averaging.............................. 4 Averaging
Frequency Span ......................20 kHz/div
Reference Frequency ....................... 0 Hz
Figure 18. ADSL output signal frequency spectrum when data bits are allocated to tones 7
and 13 only.
15. Measure the frequency at which these new components are centered.
Spectral Component Center Frequency: ____________ kHz
What do these spectral components represent, and why do they have a
sin x/x shape?
16. Determine the subcarrier separation from the measured frequencies of
tones 7 and 13.
22
Asymmetric Digital Subscriber Line (ADSL)
Exercise 1 – ADSL Signal Spectral Analysis  Procedure
Subcarrier Separation versus Subcarrier Mainlobe Bandwidth
17. Compare the measured subcarrier separation with the subcarrier mainlobe
bandwidth measured previously. What does this imply for the frequency
spectrum of the ADSL signal when bits are allocated to adjacent tones?
18. In the Bit/Tone Table window, set the number of bits allocated to tone 8 to 8,
and click the Apply button while observing the Spectrum Analyzer. Do the
same for tones 9 to 12. Figure 19 shows what you should observe on the
Spectrum Analyzer display when the number of bits allocated to tones 7
to 13 is set to 8.
Spectrum Analyzer Settings:
Maximum Input ............................... 10 dB
Scale Type.........................................Log.
Scale ....................................... 10 dBV/div
Averaging.............................. 4 Averaging
Frequency Span ......................20 kHz/div
Reference Frequency ....................... 0 Hz
Figure 19. ADSL output signal frequency spectrum when data bits are allocated to tones 7
to 13, inclusively.
Observe that the frequency components associated with a particular tone
cannot be distinguished from those associated with the other tones. Briefly
explain why no intercarrier interference occurs.
Asymmetric Digital Subscriber Line (ADSL)
23
Exercise 1 – ADSL Signal Spectral Analysis  Procedure
ADSL Signal Frequency Spectrum
The sample rate used to
generate the ADSL signal is
only twice the maximum
frequency component in this
signal (about 142 kHz). This
results in a replica of the
ADSL signal that extends to
the upper end of the ADSL
signal spectrum. A low-pass
filter is generally used in the
ATU-R Transmitter to remove this undesirable replica. No filter is used in the
ADSL application for pedagogical purposes.
19. In the Bit/Tone Table window, set the number of bits allocated to tone 14
to 8, and click the Apply button while observing the Spectrum Analyzer. Do
the same for tone 15 as well as tones 17 to 31, and observe the evolution of
the ADSL signal spectrum. Figure 20 shows what you should observe on the
Spectrum Analyzer display when the number of bits allocated to tones 7
to 31 (except tone 16) is set to 8.
Note: A replica of the ADSL signal frequency spectrum becomes visible on the
Spectrum Analyzer when bits are allocated to tones 19 to 31.
Spectrum Analyzer Settings:
Maximum Input ................................. 0 dB
Scale Type.........................................Log.
Scale ....................................... 10 dBV/div
Averaging.............................. 4 Averaging
Frequency Span ......................20 kHz/div
Reference Frequency ....................... 0 Hz
Figure 20. ADSL output signal frequency spectrum when data bits are allocated to tones 7
to 31 (except tone 16), inclusively.
20. Measure the frequency of tone 31 using a vertical cursor of the Spectrum
Analyzer.
Frequency of Tone 31: ____________ kHz
Is the frequency of tone 31 virtually equal to 31 times the base
frequency (4.439 kHz) used in the ADSL application?
‰ Yes
‰ No
21. Measure the frequency range covered by the ADSL signal spectrum using
the vertical cursors of the Spectrum Analyzer.
24
Asymmetric Digital Subscriber Line (ADSL)
Exercise 1 – ADSL Signal Spectral Analysis  Conclusion
What is the ADSL signal frequency bandwidth?
22. When you have finished using the system, exit the LVCT software and turn
off the equipment.
CONCLUSION
In this exercise, you learned that ADSL uses a large number of subcarriers to
transport data. You also learned that the number of subcarriers allocated to data
transmission in the downstream direction is much higher than the number of
subcarriers allocated to data transmission in the upstream direction. You saw
that quadrature amplitude modulation (QAM) is applied to each subcarrier.
You observed that when data modulates a subcarrier, spectral components with
the familiar sin x/x shape typical to QAM signals appear in the ADSL signal
frequency spectrum. You observed that the ADSL signal spectrum is equivalent
to several QAM signal spectra added together. You measured the frequency of a
few subcarriers (tones) and saw that they are mathematically orthogonal, i.e.,
integer multiples of a particular base frequency. You determined the subcarrier
separation from the measured subcarrier frequencies. You measured the
mainlobe bandwidth of the spectral components related to a modulated
subcarrier and determined the actual symbol rate from this measurement. You
related the mainlobe bandwidth to the subcarrier separation to highlight the
importance of subcarrier orthogonality in ADSL. Finally, you measured the
frequency range which the ATU-R Transmitter output signal (ADSL signal for
upstream data transmission) covers when data bits are allocated to all
subcarriers.
REVIEW QUESTIONS
1. Describe how the subcarriers are distributed in ADSL according to ITU-T
Recommendation G.992.1.
2. Briefly explain why ADSL is considered to be an OFDM-based application.
Asymmetric Digital Subscriber Line (ADSL)
25
Exercise 1 – ADSL Signal Spectral Analysis  Review Questions
3. Briefly describe the asymmetric nature of ADSL.
4. Briefly explain why the ADSL signal spectrum is continuous and fairly flat
over the complete frequency range it occupies.
5. In OFDM applications, what is the key feature which allows the frequency
components resulting from the modulation of each subcarrier to overlap
without producing intercarrier interference? Explain briefly.
26
Asymmetric Digital Subscriber Line (ADSL)
Instructor Guide
Sample Exercise
Extracted from
Asymmetric Digital Subscriber Line
(ADSL)
Exercise 1
ADSL Signal Spectral Analysis
Exercise 1
ADSL Signal Spectral Analysis
ANSWERS TO
PROCEDURE STEP
QUESTIONS
9. Spectral Component Frequency: 71.3 kHz (see following figure)
Spectrum Analyzer Settings:
Maximum Input ............................... 10 dB
Scale Type.........................................Log.
Scale ....................................... 10 dBV/div
Averaging................................................4
Frequency Span ......................20 kHz/div
Reference Frequency ....................... 0 Hz
Measuring the pilot tone (tone 16) frequency using the Spectrum Analyzer.
The spectral component in the ADSL signal frequency spectrum corresponds
to tone 16 since its frequency is very close to 16 times the base frequency
(4.439 kHz) used in the ADSL application. Tone 16 is used as a pilot tone
and is left unmodulated. This explains why this tone appears as single line in
the ADSL signal frequency spectrum.
11. Spectral Component Center Frequency: 31.4 kHz (see following figure)
Asymmetric Digital Subscriber Line (ADSL)
1
Exercise 1
ADSL Signal Spectral Analysis
Spectrum Analyzer Settings:
Maximum Input ............................... 10 dB
Scale Type.........................................Log.
Scale ....................................... 10 dBV/div
Averaging................................................4
Frequency Span ......................20 kHz/div
Reference Frequency ....................... 0 Hz
Measuring the frequency of tone 7 using the Spectrum Analyzer.
The new spectral components in the ADSL signal frequency spectrum
correspond to tone 7 since the mainlobe of these components is centered at
a frequency that is very close to 7 times the base frequency (4.439 kHz)
used in the ADSL application. The sin x/x shape of these spectral
components results from the quadrature amplitude modulation (QAM)
applied to tone 7. In fact, these frequency components represent the
spectrum of a QAM signal centered at the frequency of tone 7.
12. Mainlobe Bandwidth: 8.3 kHz (see following figure)
2
Asymmetric Digital Subscriber Line (ADSL)
Exercise 1
ADSL Signal Spectral Analysis
Spectrum Analyzer Settings:
Maximum Input ............................... 10 dB
Scale Type.........................................Log.
Scale ....................................... 10 dBV/div
Averaging................................................4
Frequency Span ......................10 kHz/div
Reference Frequency ....................... 0 Hz
Measuring the mainlobe bandwidth of the spectral components that appeared in the ADSL
signal spectrum.
The actual symbol rate is equal to half the mainlobe bandwidth measured,
i.e., 4.15 kbaud, because the observed spectral components result from the
quadrature amplitude modulation of tone 7.
15. Spectral Component Center Frequency: 58.1 kHz (see following figure)
Asymmetric Digital Subscriber Line (ADSL)
3
Exercise 1
ADSL Signal Spectral Analysis
Spectrum Analyzer Settings:
Maximum Input ............................... 10 dB
Scale Type.........................................Log.
Scale ....................................... 10 dBV/div
Averaging.............................. 4 Averaging
Frequency Span ......................20 kHz/div
Reference Frequency ....................... 0 Hz
Measuring the frequency of tone 13 using the Spectrum Analyzer.
The new spectral components in the ADSL signal frequency spectrum
correspond to tone 13 since the mainlobe of these components is centered at
a frequency that is very close to 13 times the base frequency (4.439 kHz)
used in the ADSL application. The sin x/x shape of these spectral
components results from the quadrature amplitude modulation (QAM)
applied to tone 13.
16. The measured frequencies of tones 7 and 13 are 31.4 kHz and 58.1 kHz,
respectively. The subcarrier separation is equal to the difference between
these two frequencies divided by 6 (the number of tones separating tones 7
and 13). The subcarrier separation is thus equal to:
Subcarrier separation = (58.1 − 31.4) ÷ 6 = 4.45 kHz.
17. The measured subcarrier mainlobe bandwidth (8.3 kHz) is nearly twice the
measured subcarrier separation (4.45 kHz). This means that the QAM signal
spectra resulting from the modulation of adjacent subcarriers should overlap
severely.
18. ADSL is an OFDM-based application using orthogonal subcarriers, i.e.,
subcarriers whose frequencies are integer multiples of a particular base
frequency. This base frequency is 4.439 kHz in the ADSL application.
20. Frequency of Tone 31: 138.0 kHz (see following figure)
4
Asymmetric Digital Subscriber Line (ADSL)
Exercise 1
ADSL Signal Spectral Analysis
Spectrum Analyzer Settings:
Maximum Input ................................. 0 dB
Scale Type.........................................Log.
Scale ....................................... 10 dBV/div
Averaging.............................. 4 Averaging
Frequency Span ......................20 kHz/div
Reference Frequency ....................... 0 Hz
Measuring the frequency of tone 31 using the Spectrum Analyzer.
Yes
21. The ADSL signal spectrum covers the frequency range from 27 kHz to
142 kHz, approximately (see following figure).
Asymmetric Digital Subscriber Line (ADSL)
5
Exercise 1
ADSL Signal Spectral Analysis
Spectrum Analyzer Settings:
Maximum Input ................................. 0 dB
Scale Type.........................................Log.
Scale ....................................... 10 dBV/div
Averaging.............................. 4 Averaging
Frequency Span ......................20 kHz/div
Reference Frequency ....................... 0 Hz
Measuring the frequency range covered by the ADSL signal using the Spectrum Analyzer.
The ADSL signal frequency bandwidth is approximately 115 kHz.
ANSWERS TO REVIEW
QUESTIONS
1. There are 256 subcarriers numbered 0 to 255. The frequencies of these
subcarriers are integer multiples of the base frequency 4.3125 kHz, thereby
leading to a subcarrier separation of 4.3125 kHz. The frequency of each
subcarrier is equal to the subcarrier number times 4.3125 kHz. Subcarriers 7
to 31, inclusively, are dedicated to upstream data transmission while
subcarriers 32 to 255 are dedicated to downstream data transmission.
2. ADSL is considered to be an OFDM-based application because the
frequencies of all ADSL subcarriers are integer multiples of the base
frequency 4.3125 kHz. These subcarriers are thus mathematically orthogonal
as required by OFDM.
3. The asymmetric nature of ADSL is due to the fact that the data transmission
rate in the downstream direction is much higher than that in the upstream
direction. This is because the number of subcarriers allocated to the
downstream data transmission is much higher than the number of
subcarriers allocated to the upstream data transmission.
4. This is because the main lobe bandwidth of the spectral components
resulting from the modulation of each subcarrier is about twice the subcarrier
separation. This causes the spectral components related to adjacent
subcarriers to overlap severely, thereby leading to a continuous and fairly flat
6
Asymmetric Digital Subscriber Line (ADSL)
Exercise 1
ADSL Signal Spectral Analysis
frequency spectrum over the complete frequency range occupied by the
ADSL signal.
5. The orthogonality of the subcarriers. When subcarriers are mathematically
orthogonal, the dot product of any two subcarriers, when averaged over a
certain time interval, is zero. This prevents intercarrier interference even if
the spectral components related to adjacent modulated subcarriers overlap.
Asymmetric Digital Subscriber Line (ADSL)
7
.
Bibliography
BELLAMY, John C., Digital Telephony, 3rd edition, New York, John Wiley & Sons,
2000.
ISBN 0-471-34571-7
FREEMAN, Roger L. Telecommunications System Engineering, Third Edition, New
York, John Wiley and Sons, Inc., 1996
ISBN 0-471-13302-7
International Telecommunication Union - Telecommunication Standardization Sector
(ITU-T), Recommendation G.992.1 - Asymmetric digital subscriber line (ADSL)
transceivers
SKLAR, Bernard. Digital Communications Fundamentals and Applications, Second
Edition, Upper Saddle River, N.J., Prentice Hall Inc., 2001
ISBN 978-0-13084-788-1
STREMLER, Ferrel G., Introduction to Communications Systems, Second Edition,
Reading, Mass., Addison-Wesley, 1982.
ISBN 0-201-07251-3